| Thin film transistor and method for fabricating the same -> Monitor Keywords |
|
|
 
Thin film transistor and method for fabricating the sameRelated Patent Categories: Semiconductor Device Manufacturing: Process, Making Field Effect Device Having Pair Of Active Regions Separated By Gate Structure By Formation Or Alteration Of Semiconductive Active Regions, On Insulating Substrate Or Layer (e.g., Tft, Etc.), Having Insulated GateThin film transistor and method for fabricating the same description/claimsThe Patent Description & Claims data below is from USPTO Patent Application 20060003503, Thin film transistor and method for fabricating the same. Brief Patent Description - Full Patent Description - Patent Application Claims
CROSS REFERENCE [0001] This application claims priority to and the benefit of Korean Patent Application No. 10-2004-0050915, filed on Jun. 30, 2004, the content of which is incorporated herein by reference in its entirety. BACKGROUND OF THE INVENTION [0002] 1. Field of the Invention [0003] The present invention relates to a thin film transistor and a method for fabricating the same, more particularly, to a thin film transistor having a channel layer of which no seed exists and no grain boundary exists, or one grain boundary exists, and a method for fabricating the thin film transistor. [0004] 2. Description of Related Art [0005] Generally, a polycrystalline silicon layer is used for various purposes as a semiconductor layer for a thin film transistor. For example, since the polycrystalline silicon layer has a high electric field effect and mobility, it can be applied to circuits operated at high speed, and it enables Complementary Metal Oxide Semiconductor (CMOS) circuit to be constructed. A thin film transistor using the polycrystalline silicon layer can also be used in an active element of an active matrix liquid crystal display (AMLCD) and a switching element and a driving element of an organic light emitting diode (OLED). [0006] The polycrystalline silicon layer used in the thin film transistor is fabricated by direct deposition, high temperature thermal annealing or laser annealing. In case of the laser annealing, while it can be performed at low temperature, and can result in high electric field effect and mobility, many alternative technologies are being studied because of the requirement for expensive laser equipment. [0007] At present, a method for crystallizing amorphous silicon using metal is mostly being studied since the method has merits that the amorphous silicon is promptly crystallized at a lower temperature compared with solid phase crystallization. The crystallization method using metal can be categorized into a metal induced crystallization method and a metal induced lateral crystallization method. Regardless of its category, however, the crystallization method using metal has the problem that characteristics of elements for thin film transistors are deteriorated by metal contamination. [0008] As such, a technology of forming a good polycrystalline silicon layer by controlling concentration of ions of metal through an ion injector has been developed. The technology performs high temperature annealing, rapid thermal annealing or laser irradiation and a method for crystallizing the thin film by thermal annealing after depositing a thin film by spin coating a mixture of organic film having viscous property and liquid phase metal on the polycrystalline silicon layer to flatten the surface of polycrystalline silicon layer as metal induced crystallization are developed to reduce quantity of metal and form a polycrystalline silicon layer of good quality. However, even in this case, there are problems in aspects of scale-up of grain size and uniformity of grain in the polycrystalline silicon layer. [0009] In order to solve the foregoing problems, a method for manufacturing polycrystalline silicon layer as a crystallization method using a capping (or cover) layer has been developed as disclosed in Korean Patent Laid-open Publication No. 10-2003-0060403. The disclosed method uses an amorphous silicon layer that is formed on a substrate, and a capping layer is formed on the amorphous silicon layer. Subsequently, a seed is formed by depositing a metal catalyst layer on the capping layer and diffusing metal catalyst into the amorphous silicon layer through the capping layer by thermal annealing or laser annealing. A polycrystalline silicon layer is obtained using the formed seed. This method has merits in reducing metal contamination because the metal catalyst is diffused through the capping (or cover) layer. [0010] However, the foregoing method has problems in that it is difficult to uniformly control low concentration of crystallization catalyst and control crystallization position and grain size. Particularly, the foregoing method has problems in that it is difficult to control the number of boundaries between the seeds and the grains since characteristics and uniformity of elements for thin film transistors are greatly influenced by the number of boundaries between seeds and grains formed in a channel of the thin film transistor. SUMMARY OF THE INVENTION [0011] It is an aspect of the present invention to provide a thin film transistor for uniformly controlling a concentration of a crystallization catalyst and a crystallization position so that no seed exists and no grain boundary exists in a channel layer of the thin film transistor or for controlling the number of seeds or grain boundaries so that characteristics and uniformity of the thin film transistor are improved, and a method for fabricating the thin film transistor. [0012] One exemplary embodiment of the present invention provides a thin film transistor. The thin film transistor includes a substrate; a semiconductor layer pattern formed on the substrate, the semiconductor layer pattern having a channel layer, the channel layer having no seed and no grain boundary; a gate insulating film formed on the semiconductor layer pattern; and a gate electrode formed on the gate insulating film. [0013] A seed may be formed in a source region or a drain region of the semiconductor layer pattern, and a width and a length of the semiconductor layer pattern may each be shorter than a radius of a grain formed by the seed. [0014] A seed may be formed on an outer part of the channel layer between a source region and a drain region of the semiconductor layer pattern, and a width and a length of the semiconductor layer pattern may each be shorter than a diameter of a grain formed by the seed. [0015] The channel layer may have a crystallinity or a crystallization ratio of about 0.7 to 0.9. [0016] One exemplary embodiment of the present invention provides a thin film transistor. The thin film transistor includes a substrate; a semiconductor layer pattern formed on the substrate, the semiconductor layer pattern has a channel layer, the channel layer having a single grain boundary; a gate insulating film formed on the semiconductor layer pattern; and a gate electrode formed on the gate insulating film. [0017] A seed may be formed in a source region or a drain region of the semiconductor layer pattern, and a length of the semiconductor layer pattern may be about 1.1 to 1.3 times a radius of a grain formed by the seed. [0018] The thin film transistor may further include a buffer layer formed between the substrate and the semiconductor layer pattern. The buffer layer may be formed of a silicon nitride film or a silicon oxide film. [0019] The thin film transistor may be used in a liquid crystal layer (LCD) device or an organic electroluminescence device. [0020] One exemplary embodiment of the present invention provides a method for fabricating a thin film transistor. The method includes forming an amorphous silicon layer on a substrate; forming a semiconductor layer pattern having a channel layer in which no seed exists and no grain boundary exists by crystallizing and patterning the amorphous silicon layer; forming a gate insulating film on the semiconductor layer pattern; and forming a gate electrode on the gate insulating film. [0021] The forming the semiconductor layer pattern may include forming a capping layer on the amorphous silicon layer; forming a grooved part on the capping layer so that a seed is formed in a source region or a drain region of the semiconductor layer pattern; forming a metal catalyst layer on the capping layer; diffusing a metal catalyst of the metal catalyst layer into the amorphous silicon layer; and forming a polycrystalline silicon layer by crystallizing the amorphous silicon layer using the diffused metal catalyst. Continue reading about Thin film transistor and method for fabricating the same... Full patent description for Thin film transistor and method for fabricating the same Brief Patent Description - Full Patent Description - Patent Application Claims Click on the above for other options relating to this Thin film transistor and method for fabricating the same patent application. ###  How KEYWORD MONITOR works... a FREE service from FreshPatents1. Sign up (takes 30 seconds). 2. Fill in the keywords to be monitored. 3. Each week you receive an email with patent applications related to your keywords. Start now! - Receive info on patent apps like Thin film transistor and method for fabricating the same or other areas of interest. ### Previous Patent Application: Method of fabricating thin film transistor using metal induced lateral crystallization by etch-stopper layer patterns Next Patent Application: Crystallization method and apparatus thereof Industry Class: Semiconductor device manufacturing: process ### FreshPatents.com Support Thank you for viewing the Thin film transistor and method for fabricating the same patent info. IP-related news and info Results in 0.10806 seconds Other interesting Feshpatents.com categories: Novartis , Pfizer , Philips , Polaroid , Procter & Gamble , 174 |
 * Protect your Inventions * US Patent Office filing 
PATENT INFO |
|
