CROSS-REFERENCE TO RELATED APPLICATIONS
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This application is a divisional of U.S. patent application Ser. No. 12/766,765 filed Apr. 23, 2010, which is a continuation-in-part of U.S. patent application Ser. No. 12/399,248 filed Mar. 6, 2009, now U.S. Pat. No. 8,030,119 Issued Oct. 4, 2011, which claims the benefit of U.S. Provisional Patent Application Ser. No. 61/068,629, filed Mar. 8, 2008. The foregoing disclosures are incorporated herein by reference in their entirety.
FIELD OF THE INVENTION
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This invention relates generally to solar cells, and more particularly to solar cells with ceramic handling layers, and methods and systems for fabricating said solar cells with ceramic handling layers.
BACKGROUND OF THE INVENTION
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Silicon is the basic ingredient of many solar cell technologies ranging from thin film amorphous silicon solar cells to single-crystal silicon wafer-based solar cells. High efficiency solar cells start with electronic grade polysilicon grown by chemical vapor deposition. The polysilicon is melted and ingots are pulled from the melt in the Czochralski process and often zone refined to produce silicon ingots or ribbons of different degrees of crystal perfection. The silicon ingot is then sliced into thin wafers by sawing or laser cutting, and solar cells are formed on the wafers by traditional semiconductor techniques and interconnected and packaged to last at least 25 years. Such silicon wafers are relatively expensive and thus severely impact the costs of solar cells in formed and packaged in the standard wafers.
Throughout the past quarter century, there have been significant innovations in all aspects of solar cell manufacture and accompanying reduction in cost. For example, from 1990 to 2006, wafers have decreased in thickness from 400 μm to 200 μm. The cost of crystalline silicon still constitutes a significant part of the overall cost, as measured by many of the metrics used to characterize the cost of crystalline solar technology.
A flow chart of a conventional process for manufacturing solar panels is illustrated in FIG. 1. In step 102, stock single-crystal silicon wafers are used as substrates which are cut into shapes that are approximately square, often with rounded corners due to the size and shape of the original wafer (200 mm diameter typically). In step 104, a photovoltaic (PV) cell structure, which is basically a diode, is fabricated on the top surface of the wafers. The fabrication process uses epitaxial or diffusion furnace methods to form the required thin silicon layers doped n-type and p-type and sometimes intrinsic (i-type). The PV cells are then assembled into an X-Y array on a substrate 106 and contacts to the n-type and p-type layers are added, often by soldering tinned copper ribbons to bus bars grown on the PV wafers. It has been difficult or impossible to attain very thin solar cells using the prior art process in which individual PC cells are formed prior to assembly into the final X-Y array needed for a completed solar panel.
The best expectation for further reductions in silicon thickness, and thereby the cost of monocrystalline silicon solar cells, is offered by techniques in which a crystal monocrystalline silicon substrate, often referred to as the base, source or mother wafer, is first treated to form a separation layer, a thin epitaxial silicon layer is then deposited on the treated surface, and finally the deposited epitaxial layer is separated from the source substrate to be used as thin (2-100 μm) single crystal silicon solar cells. The silicon substrate is thereafter sequentially re-used to form several additional such epitaxial layers, each producing its own solar cell. There are several known standard techniques for growing the separation layer, such as forming a composite porous silicon layer by anodically etching a discontinuous oxide masking layer, or by high energy implantation of oxygen or hydrogen to form the separation layer within mother wafer.
The epitaxial silicon layer that is formed has to be separated intact from the mother wafer with little damage in order to thereafter fabricate the eventual solar cell module. The separation may be preceded by formation of the p-n junctions and of part or all of the interconnections while the epitaxial layer is still attached to the mother wafer. We believe that this separation process is preferably done by “peeling” in the case where the separation layer is highly porous silicon. Peeling implies parting of an interface starting from one edge and continuing until complete separation occurs.
One basic process in the prior art for manufacturing epitaxial single crystal silicon solar modules includes the following steps: (1) forming a separation layer on a relatively thick, single crystal silicon substrate; (2) growing a single crystal epitaxial layer; 3) separating the epitaxial layer and fabricating the solar cells on the epitaxial layer and the basic cell interconnections on the solar cells; and (4) assembling and packaging several such cells to form a solar panel. Despite the great potential of this prior art method for producing relatively inexpensive, highly efficient solar cells, the method has eluded commercial success for at least three main reasons: (1) some of the unit processes are deficient and difficult to reproduce especially for thin epitaxial wafers; (2) manufacturing strategy generally starts and ends with making individual wafer-size solar cells and, thereafter, assembling them into solar panels; and (3) thin cells break easily, and their economical processing awaits the development of new tools and equipment.
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OF THE INVENTION
The present invention turns the prior art strategy on its head, starting with the solar panel and rethinking the unit manufacturing steps in panel size, starting from the surface treatment of the source wafers through to module encapsulation, completely eliminating the need for handling individual thin epitaxial silicon cells. According to one aspect of the invention, the manufacturing sequence is reversed from the conventional prior art sequence. In this aspect of the invention, multiple source wafer tiles are bonded to a support prior to the formation of individual cells, thereby enabling the use of large-scale processing for solar cell fabrication, instead of the wafer-by-wafer approach previously used. This rethinking involves key innovations that make these unit processes robust and reliable. This approach has been enabled by some key innovations described in this invention. This essentially fulfills the vision for the 2020 module, where “Cell and module manufacturing is based on process steps applied to whole panels instead of individual cells” articulated by G. Beaucarne et al. at the 21st European PVEC Conference in 2006. More importantly, panel size semiconductor processing enables a significant reduction in the cost of solar energy production.
One aspect of the invention includes mounting multiple wafers on a support plate, often called a susceptor, and processing the wafers in common. Examples of the processing include forming a separation layer, depositing silicon to form the solar cell structure, forming contacts, and separating the solar cells as a unit from the wafers.
Another aspect of the invention includes forming a separation layer in the multiple wafers by anodizing preferably monocrystalline wafers to form a porous silicon layer. Although the anodization may be done on an assembled array of solar cell tiles, it may also be done on individual wafers.
The support plate for anodization may be generally planar or may have windows formed there through for exposing the back side of the wafers supported on the ribs surrounding the windows. Thereby, liquid electrolyte may be used as a backside contact.
The anodization may be performed in a serial arrangement of multiple wafer supports removably disposed and arranged between the anode and cathode in tank containing electrolytic etching solution. The supports are sealed to the tank walls.
The anodization forms a porous silicon layer. If desired, the porosity may be graded by varying the anodization conditions during the anodization.
The porous silicon layer may be smoothed to provide a better epitaxial base, for example, by a high temperature anneal in hydrogen, for example, a temperature of at least 1000 C.
Silicon layers, preferably epitaxial, may be deposited by chemical vapor deposition on the porous silicon layer. Dopant precursors may be included in the deposition to produce a layered semiconductor structure including p-n junctions. The epitaxial deposition may be performed in a radiantly heated reactor with wafers mounted inside of a sleeve formed on two sides by wafer supports each mounting an array of solar cells.
Contacts may be fully or partially added to the silicon structures still attached to the wafer supports. Additional layers may be applied to facilitate further processing.
The fully or partially processed solar cells may be delaminated from the mother wafers across the separation (porous) layer by a progressive peeling action including clamps and a linear array of vertical actuators associated with the clamps. Examples of the clamps are segmented electrostatic clamps or a segmented vacuum clamp.
According to further aspects of the invention, a method of fabricating a solar cell comprises: forming a stack of thin continuous epitaxial solar cell layers on a silicon wafer; forming a handling layer on the stack, wherein the handling layer includes electrical contacts to the stack; and separating the stack from the silicon wafer, wherein the stack remains attached to the handling layer. The handling layer may be a glass/ceramic material, such as a glass, glass-bonded ceramic or glass-ceramic, with a CTE which is greater than or equal to the CTE of the stack over the temperature range from ambient temperatures to processing temperatures experienced during formation of the handling layer. Further, before forming the handling layer on the stack a boundary layer may be formed on the stack—the boundary layer being silicon oxide, silicon nitride or alumina, which may act as diffusion barriers and/or passivation layers.
According to yet further aspects of the invention a solar cell comprises: a stack of thin single crystal solar cell layers; a handling layer; and a boundary layer between the stack and the handling layer, the boundary layer being attached to both the stack and the handling layer, the boundary layer being greater than 10 nanometers thick and parallel to the layers in the stack. The handling layer may be waffle-shaped with an array of either square or circular apertures.
BRIEF DESCRIPTION OF THE DRAWINGS
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These and other aspects and features of the present invention will become apparent to those ordinarily skilled in the art upon review of the following description of specific embodiments of the invention in conjunction with the accompanying figures, wherein:
FIG. 1 is a flow chart of a prior art manufacturing process for solar panels;
FIG. 2 is a schematic side cross-sectional view of mother wafers attached to a susceptor without windows;
FIG. 3 is a schematic side cross-sectional view of mother wafers attached to a susceptor with windows;
FIG. 4 is a schematic isometric view of wafers attached to a susceptor;
FIG. 5 is a schematic isometric view of an anodic etcher capable of simultaneously etching multiplicities of wafers attached in a vertical orientation to each of a plurality of susceptors;
FIG. 6 is a schematic side cross-sectional view of the anodic etcher of FIG. 5;
FIG. 7 is a schematic isometric view of an anodic etcher capable of simultaneously etching a number of wafers, each attached in a vertical orientation to a support frame;
FIG. 8 is a schematic isometric view of a wafer sleeve comprising two susceptors, each with a multiplicity of wafers attached thereto;
FIG. 9 is a schematic side cross-sectional view of two mother wafers attached to a susceptor with PV cell structures formed on the upper surfaces of each mother wafer;
FIG. 10 is a schematic side cross-sectional view of the wafers and susceptor from FIG. 9 with a glue layer and glass layer attached to the upper surfaces of the PV cell structures which will become the backsides of the completed PV cells;
FIG. 11 is a schematic side cross-sectional view of the wafers and susceptor from FIG. 9 with a handling layer attached to the upper surfaces of the PV cell structures which will become the backsides of the completed PV cells;
FIG. 12 is a schematic side cross-sectional view of the wafers and susceptor from FIG. 11 with a glue layer and glass layer attached to the upper surfaces of the handling layers which will become the backsides of the completed PV cells;
FIG. 13 is a schematic isometric view of a solar cell panel showing the metal connection strings;
FIG. 14 is a side cross-sectional view of an array of wafer tiles covered by a flexible film and clamped to a segmented electrostatic chuck prior to separation of the highly porous silicon film. Cross-section A-A is illustrated;
FIG. 15 is a side cross-sectional view of an array of wafer tiles covered by a flexible film and clamped to a segmented electrostatic chuck after the beginning of separation of the highly porous film etched in FIG. 7;
FIG. 16 is a top view through cross-section A-A of the electrostatic chuck in FIGS. 14 and 15;
FIG. 17 is a side cross-sectional view of an array of wafer tiles not covered by a flexible film and clamped to a segmented vacuum chuck prior to the separation of the highly porous silicon film. Cross-section B-B is illustrated;
FIG. 18 is a side cross-sectional view of the array of wafer tiles not covered by a flexible film and clamped to a segmented vacuum chuck after the beginning of separation of the highly porous silicon film;
FIG. 19 is a top view through cross-section B-B of the vacuum chuck in FIGS. 17 and 18;
FIG. 20 is a flow chart of the first part of a manufacturing process for solar panels in a first embodiment of the present invention;
FIG. 21 is a flow chart of the first part of a manufacturing process for solar panels in a second embodiment of the present invention;
FIG. 22 is a flow chart of the first part of a manufacturing process for solar panels in a third embodiment of the present invention;
FIG. 23 is a flow chart of the first part of a manufacturing process for solar panels in a fourth embodiment of the present invention;
FIG. 24 is a flow chart of the final part of a manufacturing process for solar panels using PV cells with backside contacts only;
FIG. 25 is a flow chart of the final part of a manufacturing process for solar panels using PV cells with frontside and backside contacts;
FIG. 26 is top view representation of a solar cell with a waffle-shaped handling layer with square apertures;
FIG. 27 is a top view representation of a solar cell with a waffle-shaped handling layer with circular apertures;
FIG. 28 is a cross-section, along X-X of the solar cell of FIG. 27;
FIG. 29 is a cross-sectional representation of a solar cell with a handling layer and back side contacts;
FIG. 30 is a cross-sectional representation of a solar cell with a handling layer and contacts on both sides; and
FIG. 31 is a cross-sectional representation of another embodiment of a solar cell with a handling layer and contacts on both sides.
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Embodiments of the present invention will now be described in detail with reference to the drawings, which are provided as illustrative examples of the invention so as to enable those skilled in the art to practice the invention. Notably, the figures and examples below are not meant to limit the scope of the present invention to a single embodiment, but other embodiments are possible by way of interchange of some or all of the described or illustrated elements. Moreover, where certain elements of the present invention can be partially or fully implemented using known components, only those portions of such known components that are necessary for an understanding of the present invention will be described, and detailed descriptions of other portions of such known components will be omitted so as not to obscure the invention. In the present specification, an embodiment showing a singular component should not be considered limiting; rather, the invention is intended to encompass other embodiments including a plurality of the same component, and vice-versa, unless explicitly stated otherwise herein. Moreover, applicants do not intend for any term in the specification or claims to be ascribed an uncommon or special meaning unless explicitly set forth as such. Further, the present invention encompasses present and future known equivalents to the known components referred to herein by way of illustration.
In one aspect of the invention, the solar panel includes an array of thin single crystal silicon solar cells, wherein the thin single crystal wafers are epitaxially grown and processed together as an array on a ‘template’. In the array, multiple relatively thick single crystal silicon base or mother wafers are either handled singly or attached to a suitable carrier substrate or susceptor. The assembly of susceptor and array of mother wafers will be called an ‘array template’. After completion of the cell fabrication steps, the entire solar cell array is permanently adhered to a suitable support sheet with an appropriate adhesive and separated as one unit from the array template. The array template may then be reused to fabricate another solar cell array. The array template of this invention may consist of a closely tiled array of circular, rectangular or square, single crystal silicon wafers formed on one of the following three types of substrates: (1) a wafer tile cut from a conventional thin silicon wafers; (2) a wafer tile cut from a thick, zone-refined, single-crystal silicon block; and (3) a wafer tile cut from a composite structure comprising the following two blocks laminated together of (a) a thick, zone-refined, single-crystal silicon block, and (b) a thick, non-device-quality, silicon block.
The assembly onto a support substrate of multiple rectangular or square epitaxial wafer tiles, hereinafter simply referred to as ‘source wafer tiles’, unlike the usual circular wafers, allows for the densest packing of cells in the panel. The machining loss of high quality silicon has no major impact on the overall cost of silicon, while the close-packed array pays great dividends because of the gain in cell density on the panel. As described below, independent of the thickness of the wafer tile, the preferred thickness for the final solar cell is in the preferred range of 10-50 μM, separated from the upper surface of the wafer tiles in the closely tiled array, as described in section below regarding separation.
This section describes the formation of an array template, which is the first step in the large-substrate manufacturing process outlined above. Since the substrate of the template supports the wafers during epitaxial deposition, it also serves as the susceptor for the epitaxial growth process.
FIG. 2 is a schematic side cross-sectional view of wafers 401 attached to a susceptor 403, which in this embodiment may be a flat sheet or generally planar plate without windows. For effective subsequent processing steps, it is important to minimize the width of gaps 402 between the wafer tiles 401. Typically, the wafers 401 are silicon and are doped to be conductive for reasons described below. The wafers 401 should be monocrystalline to allow the subsequent epitaxial growth of generally monocrystalline silicon. Excessively large gaps 402 may result in undesirable particle generation during subsequent processing steps. The lower surfaces of the wafer tiles 401 are bonded to a support substrate 403 to ensure that the upper surfaces of the wafer tiles are approximately co-planar. The co-planarity involves two requirements: (1) the thicknesses of wafer tiles 401 must be uniform, and (2) the thicknesses of a bond layer 504 in FIG. 4 between the back surfaces of the wafer tiles 401 and the top surface of the susceptor 403 must be uniform. The desire for co-planarity arises from the desire to reduce or eliminate deposition on the exposed edges of the wafer tiles at the gaps 402.
To optimize the anodic etching process used to form the porous silicon layer (see FIGS. 5-7), it may be desirable to provide good electrical contact not only between the electrolytic etching solution and the front sides of the wafers but also between the etching solution or other electrolytic liquid and the backsides of the wafer tiles being etched. Thus, FIG. 3 shows a schematic side cross-sectional view of wafers 421 attached to a susceptor 425 with windows 424 between ribs 426 of the susceptor 425 providing good backside contact to the etching solution in addition to separate frontside contact to the etching solution. The same considerations with respect to the gaps 402 in FIG. 2 apply to gaps 422 in FIG. 3. In this embodiment, the backsides 424 of the wafers 421 are open to the etchant solution through the windows 424, which are of the same general shape and only slightly smaller the tiles 421. That is, the ribs 426 form a rectangular grid and the ribs 426 support and are sealed to the peripheries f the wafers 421.
FIG. 4 is a schematic isometric view of wafers 508 attached in a two-dimensional array to a susceptor 502, more generally called a support. The horizontally extending gaps 510 and vertically extending gaps 512 between the wafers 508 should be minimized due to the considerations discussed above with reference to FIGS. 2 and 3. A large number (in the illustrated example, 12×6=72) of wafer tiles 608 are shown attached to the substrate 502.
The susceptor 502 must be fabricated from a material which is compatible with device processing conditions such as chemical vapor deposition, plasma etching, contact formation, and such. Appropriate materials for the susceptor 502 may be ceramic or metal. Examples of ceramics or otherwise robust materials are alumina, aluminum nitride, silicon carbide, silicon-impregnated silicon carbide, silicon, silicon nitride, boron nitride, boron carbide, etc. A planar susceptor needs to be electrically conductive to the anodizing current while a windowed susceptor, though preferably conductive, may be insulating. The wafer tiles 508 can be held to the surface 504 of the susceptor 502 by mechanical clamps, by machined dove tail joints, by gravity, or simply by a bond to the support by field assisted bonding well known in the art. The bonding is needed only once for an array template used in forming a large number of solar cell arrays. Such large area device fabrication is routinely done for large displays, and even for thin film solar panels.
Porous Silicon Layer Process
The next steps in the described process for manufacturing solar panels involve the formation of a porous silicon separation layer. The purpose of this layer is to enable the reuse of the silicon wafer tiles in the tiled array created in FIG. 4 as described above. This reuse is possible because the porous silicon release layer does not use up more than roughly 7 microns of the wafer thickness. Since the thickness of the mother wafer tiles is typically at least hundreds of microns (even for thin silicon wafers) and can be up to 10 mm or greater (for thick silicon blocks or laminated silicon wafers or blocks), it is possible to fabricate a substantial number of solar cell arrays from a single array of wafer tiles. In order to use only a thin slice of the full wafer tile thickness, it is necessary to build the solar cells on top of a porous silicon separation layer. K. V. Ravi in co-pending U.S. patent application Ser. Nos. 12/290,582 and 12/290,588, both filed Oct. 31, 2008, incorporated herein by reference, describes the fabrication processes for backside contact PV cells, and frontside/backside contact PV cells, respectively, and are incorporated by reference herein. The described processes involve the formation of a porous surface layer in the mother wafers and growth of an epitaxial layer over the porous layer, and at least partial development of the solar cell in the epitaxial layer while still attached to the array template. After the array of solar cells has been at least partially fabricated in the epitaxial layer, the tile array can be separated from the bulk silicon material of the source wafer tile array, leaving most of the bulk material remaining in the mother wafers to be used in the formation of additional arrays of solar cells. For subsequent uses of the source wafer tile array to form second, third, fourth, etc., solar cell arrays, the surface of the mother wafers would be the typically rough lower surface of the cleaved porous silicon layer formed in FIGS. 5-7, below.
We have discovered that a lapped surface on the silicon source wafer is especially suited for ease of peeling of the epitaxial layer. Although we are not bound by the theory, we believe that the residual surface damage in the lapped surface pre-disposes the porous layer formed thereon to be easily detached. Lapping produces a surface roughness intermediate that produced by grinding and polishing. Lapping involves rotating a planar surface of a disk, often metal and perhaps textured or grooved, against the surface with typically a lapping powder being disposed between the disk and the surface. It typically produces an RMS (root mean square) surface roughness of 50 to 100 nm. Grinding involves rotating the circular face of an abrasive grinding wheel against the work piece surface. It typically produces an RMS surface roughness of greater than 100 nm. Polishing is similar to lapping but uses a softer polishing powder and a typically softer non-metallic polishing pad to typically produce a surface roughness of less than 50 nm. The rougher ground silicon surface is rougher than a lapped surface and may enable even easier peeling, but the rougher ground surface may lead to too many defects in the epitaxial layer grown thereon. A polished silicon surface, on the other hand, may be nearly free of surface flaws, but we believe that the porous layer formed thereon will be relatively more difficult to detach.
A schematic isometric view of an anodic etcher capable of simultaneously etching multiplicities of wafers attached in a vertical orientation to each of a plurality of susceptors is shown in FIG. 5. The anodic etcher 601 contains within dielectric tank walls two electrodes 604, 605 preferably formed of platinum and electrically connected to a power supply 606 by respective wires 606, 607. One or more susceptors 610, each having a multiplicity of wafer tiles 611 affixed thereto, are removably immersed in the electro-etching solution 603, typically hydrofluoric acid (HF). If the windowed susceptor shown in FIG. 3 is used, then both the front and back sides of the wafer tiles 611 will be exposed to the electrolytic solution, but the wafer tiles 611 need to be sealed to the ribs 425 of the windowed susceptor 426 to electrically isolate the electrolytic solutions at the front and back. A conductive windowed susceptor is preferred for anodization although it presents some challenges. Alternatively, one or more holes through an otherwise planar susceptor for each wafer provides liquid contact to the wafers. Alternatively, the non-windowed susceptor shown in FIG. 2 may be used if the susceptor is electrically conductive and in good electrical contact with the source wafers affixed thereto.
Furthermore, if the edges of the susceptors 610 form a seal against the internal walls of the anodization tank 601 interrupting the electrical path of the electrolytic solution and the etching solution does not extend over the top of the susceptors 610, then the susceptors 610 and their attached wafer 611 will essentially form electrodes in a serial arrangement for the anodic etching process and not require actual electrical connections of the wafers or susceptors to the power supply 606. The liquid backside contact is advantageous in ensuring uniform etching across the surfaces of the wafers 611. With proper bias on the power supply 606, i.e., a positive bias on the fronts of the wafers relative to their backs, only the front surfaces of the wafers 611 will react with the HF solution 603 as is familiar to those skilled in the art. As mentioned above, a top surface of the electrolytic solution 603, typically hydrofluoric acid, is below the tops of the susceptors 610 to ensure that each susceptor 610 and attached wafers 611 form a separate electrode in the electro-etching circuit.
Etching a large array of silicon wafers to produce the needed porous layer structures requires uniform anodic current distribution across individual wafers, and between all wafers in the array. Further, the silicon wafers need to be conductive to the anodization current, for example, having an electrical conductivity in the range of 0.001 to 0.1 ohm-cm, 0.02 ohm-cm being a convenient value. Either p-type or n-type silicon wafers can be anodized. Discrete metal electrode contacts for either the anode or cathode do not yield the desired level of uniformity in etching, leading to non-uniformities even within single wafers. We have observed that using the electrolyte itself as the electrical contact to both sides of the wafers in a vertical etcher virtually eliminates these non-uniformities. Here, the same current density flows through all the wafers in the array. The volumes between each pair of susceptors or between a susceptor and an electrode are essentially like the individual cells in a serially connected battery. Such a scheme also allows for anodic etching of several panels in parallel in a vertical configuration as shown in FIGS. 3-5. This novel scheme produces uniform anodic etching on each wafer surface and the same etching uniformity across all wafers in a panel, an important feature enabling processing at the panel level. When the wafers are attached to the susceptor or support substrate, the support substrate needs to be in good electrical contact with the wafer, and should be a good electrical conductor itself. Alternatively, the susceptor may have openings or slots to allow for the electrolyte to directly contact the wafer back sides. These innovations enable very high throughputs in production.
An embodiment of an anodization tank shown in a schematic side cross-sectional view of FIG. 6 of the anodic etcher 601 of FIG. 5 can contain up to at least five susceptors 610, each having a multiplicity of wafers 611 affixed thereto. The manufacturing sequences described in FIGS. 20 and 21 would employ such an electro-etching arrangement.
However, for the manufacturing sequences described in FIGS. 22 and 23, a different anodization arrangement may be employed. An anodic etcher 621 illustrated in the schematic sectioned isometric view of FIG. 7 is capable of simultaneously etching a number of wafers 631, each attached in a vertical orientation to a support frame 630. Note that in this case, although multiple wafers may be simultaneously etched, thereby improving etching throughput, these wafers are not yet detachably attached to a susceptor, and are, instead, attached to the support frames 630, which form seals against the internal walls of the etch chamber 621. Either round or square wafers 631 may be attached to the support frames 630 mounted within etch chamber 621, which can be much smaller than the etch chamber 601 of FIGS. 5 and 6. Electrodes 624, 625 are electrically connected to a power supply 628 though respective wires 626, 627. The top surface of the etch solution 623, typically hydrofluoric acid, filled into the anodization tank 621 should be below the tops of the support frames 630 and the support frames 630 should be sealed to the sidewalls of the anodization tank 621 to isolate the cells of the serial electro-etching apparatus to ensure that each wafer forms an electrode in the etching circuit.
It may be advantageous to vary the anodization process to form a low porosity film on the upper surfaces of wafers 611 or 631, and a higher porosity film below the low porosity film. Such a graded porosity has the advantage that the low porosity silicon layer may be easier to thermally smooth in the respective steps 203, 223, 243, and 263 in FIGS. 20-23) prior to epitaxial growth of the n-type and p-type layers in the PV cells. The electro-etching process for generating a high porosity film in the wafers has different etch parameters than the electro-etching process for generating a low porosity film, however the configuration of the electro-etching apparatus as shown in FIGS. 5-7 can be used for both cases and for some types of grading one electro-etching apparatus may serially anodize both sub-layers. The ability to modulate porosity by changing etch chemistry, etch current, or both has been an important innovation.
After the electro-etching processes illustrated in FIGS. 5 and 6 to produce the porous silicon surface layer, the wafer tile arrays, still attached to the susceptors 610, are removed from the anodization tank 601 for subsequent processing using various standard semiconductor processes, starting with thermal smoothing followed by epitaxial deposition of silicon in a reactor. In the case of the anodizaton tank 621 of FIG. 7, the wafers are typically remounted onto a susceptor carrying a closely packed array of solar wafer tiles including the mother wafers using the mounting methods described for susceptor 502 of FIG. 4. The windowed susceptor of FIG. 3 may be used in the epitaxial reactor described below if the wafers are sealed to the ribs; however, radiant heating of the wafers through the windowed susceptor presents challenges in accomplishing uniform heating. The planar susceptor of FIG. 2 is more easily used in a radiantly heated epitaxial reactor.
The exposed surface of the anodized porous silicon layer is advantageously smoothed to promote epitaxial growth of silicon on the porous layer. The smoothing may be performed as described in the afore cited 12/290,588 by annealing the mother wafer(s) in a hydrogen ambient at generally atmospheric pressure for a time of about 10 minutes and a temperature of 900 C or higher. Although the thermal smoothing can be done in conventional thermal processing oven, advantageously it is done when the mother wafers are mounted on susceptors, which are assembled into a wafer sleeve and thermally smoothed as a group, for example, using the radiantly heated epitaxial reactor described next.
Epitaxial Silicon Growth
The epitaxial reactor for depositing the silicon onto the conditioned surfaces of the source wafer template array has been described in detail by Sivaramakrishnan et al. in co-pending U.S. patent application Ser. No. 12/392,448, filed Feb. 26, 2008 and incorporated herein by reference. The epitaxial reactor has been designed to rapidly and simultaneously deposit silicon onto a large number of wafers by a thermal chemical vapor deposition (CVD) process using radiant lamps. As shown in the partially sectioned isometric view of FIG. 8, multiple wafers 720 are held on the interior surfaces of each of two susceptors 706 facing each other at close distance to confine the heat and the reacting gases close to the wafer surfaces. The assembly of two susceptors 706 and two end caps 701 forms a “wafer sleeve” with two open ends and having a relatively small interior volume. The two end caps 701 each have a tongue 702 which fits between the two susceptors 706, defining the spacing between the susceptors 706 at each susceptor edge.
The flow direction of the reactor gases flowing though the wafer sleeve between its open ends is reversed frequently in what is called “cross-flow processing” to avoid gas depletion at middle regions of the susceptor, thereby improving deposition thickness and resistivity uniformity. These features provide for excellent uniformity in temperature and reactive gas supply, ensuring highly uniform epitaxial silicon deposition. The reactor may be equipped with two or three reaction chambers in series, the first one to preheat the susceptor, the second for the deposition of the epitaxial silicon, and the last one to cool the susceptor. Dopant species can be bled into the reaction chamber, as necessary, to form as grown junctions. This reactor arrangement greatly enhances the throughput of the epitaxial reactor. Important advantages of the epitaxial reactor and process of this invention are: (1) a large-area vertical reactor with low volume to minimize gas cost and footprint; (2) a high-growth rate (2-10 μm/min) in the mass transport regime at temperatures exceeding 1000 C; (3) multiple wafer processing on two or more wafer susceptors that are processed simultaneously since the gases and incandescent heating lamp array is shared for two susceptors within the wafer sleeve; (4) lamp based heating for fast temperature cycling to enable a quick process sequence; and
(5) efficient flow distribution for the silicon precursor trichlorosilane (TCS) with silicon conversion rates exceeding 50%.
In the case for processing the solar module of this invention, the substrates carrying the wafer arrays will constitute the susceptor. The gas flow is advantageously aligned with the shorter dimension of the solar array, again to minimize gas depletion effects in the center.
FIG. 9 is a schematic side cross-sectional view of two mother or source wafers 801 attached to a susceptor 800 with PV cell structures epitaxially formed on the upper surfaces of each mother wafer 801 in the epitaxial reactor. Each PV cell includes at least one p-type layer 803 and at least one n-type layer epitaxially formed on top of a porous silicon layer 802 formed using the anodic etching process discussed in FIGS. 5-7. Note that if the anodic etching apparatus of FIGS. 5 and 6 is used, the porous silicon layer 802 will have been formed after attachment of the mother wafers 801 to the susceptor 800; but if the electro-etching apparatus of FIG. 7 is used, the porous silicon layer 802 will have been formed prior to attachment of the mother wafer 801 to the susceptor 800.
In either case, the growth process for the PV cells on the different mother wafers 801 proceeds in parallel using the vertical epitaxial reactor described above. After growth of the p-doped layers 803 of the PV cells, an n-doped layer 804 is epitaxially deposited. The order of the p-type and n-type layers can be reversed if desired.
Epitaxial silicon can be deposited with as-grown p-n junctions by adding suitable dopants during portions of the silicon deposition process, as shown in the two co-pending patent applications of K. V. Ravi (U.S. patent application Ser. Nos. 12/290,582 and 12/290,588) and the co-pending patent application of Sivaramakrishnan et al. (U.S. patent application Ser. No. 12/392,448). Such junctions may also be formed after epitaxial growth by well known dopant thermal diffusion methods. The cell fabrication steps, including the contact formation methods described here are for examples only.
Contacts and Surface Layers
The susceptor and attached mother wafers are then removed from the epitaxial reactor and further processed for the formation of contacts and surface layers and separation from the template array and final processing. Depending upon the type of cell structure, some of the contact processing may be performed after the cell array has been removed from the template array.