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Thermally enhanced stacked die package and fabrication methodRelated Patent Categories: Semiconductor Device Manufacturing: Process, Packaging (e.g., With Mounting, Encapsulating, Etc.) Or Treatment Of Packaged Semiconductor, Assembly Of Plural Semiconductive Substrates Each Possessing Electrical Device, Stacked Array (e.g., Rectifier, Etc.)Thermally enhanced stacked die package and fabrication method description/claimsThe Patent Description & Claims data below is from USPTO Patent Application 20070148821, Thermally enhanced stacked die package and fabrication method. Brief Patent Description - Full Patent Description - Patent Application Claims
CROSS-REFERENCE TO RELATED APPLICATION(S) [0001] This is a continuation of co-pending U.S. patent application Ser. No. 10/825,910 filed Apr. 16, 2004. TECHNICAL FIELD [0002] The present invention relates generally to semiconductor packages having stacked dies, and more particularly to a method and apparatus for manufacturing a thermally enhanced stacked die semiconductor package. BACKGROUND ART [0003] Semiconductors, or computer chips, have made their way into virtually every electrical product manufactured today. Chips are used not only in very sophisticated industrial and commercial electronic equipment, but also in many household and consumer items such as televisions, clothes washers and dryers, radios and telephones. As many of these types of products become smaller but more functional, there is a need to include more semiconductors in these smaller products. The reduction in size of cellular telephones is one example of how more and more capabilities find their way into smaller and smaller electronic products. [0004] The popularity of smaller and more complicated electronic products has placed increased demands on the packaging for chips used in such devices. These increased demands have led to new packaging concepts and approaches. Unpackaged chips are referred to as die or dies, and current packaging methods include placing more than one die in a single package. One such approach is to stack one die on top of another and then enclose the stack of dies in one package. The final package for the multiple-stacked semiconductor dies is much smaller than would result if the dies each were packaged separately. In addition to providing a smaller size, these packages offer a number of advantages that relate to the manufacturing of the package such as ease of handling and assembling. [0005] An example of a die stacking technique incorporates a pair of stacked dies encapsulated in a molded plastic package that has connectors or leads extending out from the package that function as input/output terminals of the dies inside the package. The package includes a substrate and a first die mounted on the top surface of the substrate. A second die is then stacked on top of the first die. [0006] The substrate may be comprised of a flexible resin tape, a rigid fiber-glass/copper sheet laminate, a co-fired ceramic coupon, or a flexible metal lead frame, a ball grid array substrate or other well-known types of substrates in the semiconductor industry, depending on the particular type of semiconductor package being used. [0007] The first die is conventionally mounted to the top surface of the substrate with, for example, a layer of an adhesive or an adhesive film, and then electrically connected to the substrate by a plurality of fine, conductive wires, typically gold (Au) or aluminum (Al), that electrically connects the die to the substrate. The wires are attached to the die at the bonding pads of the die, which are located around the periphery of the die. [0008] The second die is mounted on the top surface of the first die with an adhesive layer that is positioned within the central area of the top surface of the first die. The adhesive layer may contact or cover both the bonding pads of the first die and the conductive wires bonded to the first die. The adhesive layer positions the second die sufficiently far above the first die to prevent the dies from contacting each other or any wires connected to the dies. The second die is then wire bonded to the substrate in the same fashion as the first die. One or more additional dies can then be stacked on top of the second die using the same technique. [0009] In a stacked die arrangement, the dies are wire bonded sequentially, typically with automated wire bonding equipment employing well-known thermal-compression or ultrasonic wire bonding techniques. During the wire bonding process, the head of a wire bonding apparatus applies a downward pressure on a conductive wire held in contact with a wire-bonding pad on the die to weld or bond the wire to the bonding pad on the die. [0010] After the dies are wire bonded to the substrate, the dies, substrate, and conductive wires are covered with plastic, or other suitable material, which encapsulates the stacked dies and protects them from moisture and other environmental elements. [0011] Despite efforts to overcome problems resulting in lower yields of semiconductor packages with stacked dies problems still exist. In particular, dies within the stack fail prematurely. [0012] In conventional multi-chip modules, by packing a number of dies in close proximity within a single package, thereby eliminating individual packages for each of the die, electrical performance is improved and the board space occupied by the semiconductor is reduced. Due to the increase in the packing density, however, the power density of the multi-chip module typically is higher than when each die is separately packaged, thus requiring more elaborate thermal design and thermal management schemes to maintain the device temperatures within acceptable ranges. [0013] Consequently, there remains a need for improved, more economical, more efficient, and more readily manufactured and assembled heat sinks, heat sink packages, and fabrication methods for use with semiconductor packages. [0014] Solutions to these problems have been long sought, but prior developments have not taught or suggested satisfactory solutions and, thus, solutions to these problems have long eluded those skilled in the art. DISCLOSURE OF THE INVENTION [0015] The present invention provides a semiconductor package including a substrate. A first die is attached to the substrate. The first die is electrically connected to the substrate. A heat sink having an undercut around its periphery is attached to the first die. A second die is attached to the heat sink. The second die is electrically connected to the substrate, and the first die, the heat sink, and the second die are encapsulated. [0016] The present invention provides a thermally enhanced semiconductor package that is more economical, more efficient, and more readily manufactured and assembled. [0017] Certain embodiments of the invention have other advantages in addition to or in place of those mentioned above. The advantages will become apparent to those skilled in the art from a reading of the following detailed description when taken with reference to the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS [0018] FIG. 1 is a side view of a semiconductor in an intermediate stage of manufacture with a substrate having a first die attached in accordance with an embodiment of the present invention; [0019] FIG. 2 is the structure of FIG. 1 with a heat sink attached to the first die; Continue reading about Thermally enhanced stacked die package and fabrication method... Full patent description for Thermally enhanced stacked die package and fabrication method Brief Patent Description - Full Patent Description - Patent Application Claims Click on the above for other options relating to this Thermally enhanced stacked die package and fabrication method patent application. ###  How KEYWORD MONITOR works... a FREE service from FreshPatents1. Sign up (takes 30 seconds). 2. Fill in the keywords to be monitored. 3. Each week you receive an email with patent applications related to your keywords. Start now! - Receive info on patent apps like Thermally enhanced stacked die package and fabrication method or other areas of interest. ### Previous Patent Application: Microelectronic devices and methods for manufacturing microelectronic devices Next Patent Application: Microelectronic packages and methods therefor Industry Class: Semiconductor device manufacturing: process ### FreshPatents.com Support Thank you for viewing the Thermally enhanced stacked die package and fabrication method patent info. IP-related news and info Results in 0.31538 seconds Other interesting Feshpatents.com categories: Software: Finance , AI , Databases , Development , Document , Navigation , Error 174 |
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