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  Tft array substrate and photo-masking method for fabricating sameUSPTO Application #: 20070249111Title: Tft array substrate and photo-masking method for fabricating same Abstract: An exemplary TFT array substrate (2) includes an insulating substrate (201); a transparent conductive line (221) formed on the insulating substrate; a plurality of gate lines (210) formed on the transparent conductive line, that are parallel to each other and that each extend along a first direction; a plurality of data lines (220) formed on the insulating substrate, that are parallel to each other and that each extend along a second direction orthogonal to the first direction. The gate line at an intersection point of the gate line and the data line are disconnected. (end of abstract) Agent: Wei Te Chung Foxconn International, Inc. - Santa Clara, CA, US Inventor: Yao-Nan Lin USPTO Applicaton #: 20070249111 - Class: 438182 (USPTO) The Patent Description & Claims data below is from USPTO Patent Application 20070249111. Brief Patent Description - Full Patent Description - Patent Application Claims
FIELD OF THE INVENTION [0001]The present invention relates to thin film transistor (TFT) array substrates used in liquid crystal displays (LCDs) and methods of fabricating these substrates, and particularly to a TFT array substrate and a method for fabricating the substrate which efficiently uses minimal photo-masking. GENERAL BACKGROUND [0002]A typical liquid crystal display (LCD) is capable of displaying a clear and sharp image through millions of pixels that make up the complete image. The liquid crystal display has thus been applied to various electronic equipments in which messages or pictures need to be displayed, such as mobile phones and notebook computers. A liquid crystal panel is a major component of the LCD, and generally includes a thin film transistor (TFT) array substrate, a color filter substrate opposite to the TFT array substrate, and a liquid crystal layer sandwiched between the two substrates. [0003]Referring to FIG. 19, part of a typical TFT array substrate is shown. The TFT array substrate 100 includes a substrate 101, a gate electrode 102 formed on the substrate 101, a gate insulating layer 103 formed on the substrate 101 having the gate electrode 102, a semiconducting layer 104 formed on the gate insulating layer 103, a source electrode 105 and a drain electrode 106 formed on the gate insulating layer 103 and the semiconducting layer 104, a passivation layer 107 formed on the gate insulating layer 103, the source electrode 105 and the drain electrode 106, and a pixel electrode 108 formed on the passivation layer 107. [0004]Referring to FIG. 20, this is a flowchart summarizing a typical method for fabricating the TFT array substrate 100. For simplicity, the flowchart and the following description are couched in terms that relate to the part of the TFT array substrate 100 shown in FIG. 19. The method includes: step S10, forming a gate metal layer; step S11, forming a gate electrode; step S12, forming a gate insulating layer and an amorphous silicon (a-Si) and doped a-Si layer; step S13, forming a semiconducting layer on the gate insulating layer; step S14, forming a source/drain metal layer; step S15, forming source/drain electrodes; step S16, forming a passivation material layer; step S17, forming a passivation layer; step S18, forming a transparent conductive layer; and step S19, forming a pixel electrode. [0005]In step S10, an insulating substrate is provided. The substrate may be made from glass or quartz. A gate metal layer and a first photo-resist layer are formed on the substrate. [0006]In step S11, the first photo-resist layer is exposed by a first photo-mask, and then is developed, thereby forming a first photo-resist pattern. The gate metal layer is etched, thereby forming a pattern of the gate electrode 102, which corresponds to the first photo-resist pattern. The residual first photo-resist layer is then removed by an acetone solution. [0007]In step S12, a gate insulating layer 103, an a-Si and doped a-Si layer, and a second photo-resist layer are sequentially formed on the substrate 101 having the gate electrode 102. [0008]In step S13, the second photo-resist layer is exposed by a second photo-mask, and then is developed, thereby forming a second photo-resist pattern. The a-Si and doped a-Si layer is etched, thereby forming a pattern of the semiconducting layer 104, which corresponds to the second photo-resist pattern. The residual second photo-resist layer is then removed by an acetone solution. [0009]In step S14, a source/drain metal layer and a third photo-resist layer are sequentially formed on the semiconducting layer 104. [0010]In step S15, the third photo-resist layer is exposed by a third photo-mask, and then is developed, thereby forming a third photo-resist pattern. The source/drain metal layer is etched, thereby forming a pattern of the source electrode 105 and the drain electrode 106, which corresponds to the third photo-resist pattern. The residual third photo-resist layer is then removed by an acetone solution. [0011]In step S16, a passivation material layer and a fourth photo-resist layer are sequentially formed on the substrate 101 having the three electrodes 102, 105, 106 formed thereon. [0012]In step S17, the fourth photo-resist layer is exposed by a fourth photo-mask, and then is developed, thereby forming a fourth photo-resist pattern. The passivation material layer is etched, thereby forming a pattern of the passivation layer 107, which corresponds to the fourth photo-resist pattern. The residual fourth photo-resist layer is then removed by an acetone solution. [0013]In step S18, a transparent conductive layer and a fifth photo-resist layer are sequentially formed on the passivation layer 107. [0014]In step S19, the fifth photo-resist layer is exposed by a fifth photo-mask, and then is developed, thereby forming a fifth photo-resist pattern. The transparent conductive layer is etched, thereby forming a pattern of the pixel electrode 108, which corresponds to the fifth photo-resist pattern. The residual fifth photo-resist layer is then removed by an acetone solution. [0015]The method includes five photo-mask processes, each of which is rather complicated and costly. Thus, the method for fabricating the TFT array substrate 100 is correspondingly complicated and costly. [0016]What is needed, therefore, is a method for fabricating a TFT array substrate that can overcome the above-described problems. What is also needed is a TFT array substrate fabricated by the above method. SUMMARY [0017]In one preferred embodiment, a method for fabricating a thin film transistor (TFT) array substrate includes providing an insulating substrate; forming a transparent conductive metal layer and a gate metal layer on the insulating substrate; forming a gate electrode, a gate line and a pixel electrode through a first photolithograph process; forming a gate insulating layer, an amorphous silicon pattern, and a doped amorphous silicon pattern through a second photolithograph process; forming a photo-resist pattern on the gate electrode through a third photolithograph process, using the gate electrode as a photo-mask; forming a source/drain metal layer on the insulating substrate, the doped amorphous silicon layer, the photo-resist pattern and the pixel electrode; forming a source/drain metal pattern through removing the photo-resist pattern and a portion of the source/drain metal layer on the photo-resist pattern; and forming a passivation layer pattern, a source/drain electrode through a fourth photolithograph process. [0018]An exemplary TFT array substrate includes an insulating substrate; a transparent conductive line formed on the insulating substrate; a plurality of gate lines formed on the transparent conductive line, that are parallel to each other and that each extend along a first direction; a plurality of data lines formed on the insulating substrate, that are parallel to each other and that each extend along a second direction orthogonal to the first direction. The gate line at an intersection point of the gate line and the data line are disconnected. [0019]Other advantages and novel features will become more apparent from the following detailed description when taken in conjunction with the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS [0020]FIG. 1 is a schematic, top view of a pixel of a TFT array substrate according to an exemplary embodiment of the present invention. Continue reading... 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