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Tessera Lerner David Et Al. patentsThe following is a sampling of recent Tessera Lerner David Et Al. patent applications (USPTO Patent Application #, Patent Title) sorted by month.
June 2009 - Tessera Lerner David Et Al. patents
20090162975 - Method of forming a wafer level package
20090145645 - Interconnection element with posts formed by plating
20090146303 - Flip chip interconnection with double post
20090148594 - Interconnection element with plated posts formed on mandrel
May 2009 - Tessera Lerner David Et Al. patents
20090133254 - Components with posts and pads
20090121351 - Process for forming a bump structure and bump structure
20090115047 - Robust multi-layer wiring elements and assemblies with embedded microelectronic elements
April 2009 - Tessera Lerner David Et Al. patents
20090104736 - Stacked packaging improvements
20090104736 - Stacked packaging improvements
20090104736 - Stacked packaging improvements
March 2009 - Tessera Lerner David Et Al. patents
20090071000 - Formation of circuitry with modification of feature height
20090071707 - Multilayer substrate with interconnection vias and method of manufacturing the same
20090065907 - Semiconductor packaging process using through silicon vias
February 2009 - Tessera Lerner David Et Al. patents
20090045524 - Microelectronic package
20090039528 - Wafer level stacked packages with individual chip selection
20090032913 - Component and assemblies with ends offset downwardly
January 2009 - Tessera Lerner David Et Al. patents
20090023249 - Wire bonded wafer level cavity package
20090014861 - Microelectronic package element and method of fabricating thereof
20090008795 - Stackable microelectronic device carriers, stacked device carriers and methods of making the same
20090002964 - Multilayer wiring element having pin interface
April 2008 - Tessera Lerner David Et Al. patents
20080093108 - Layered metal structure for interconnect element
20080088033 - Microelectronic packages and methods therefor
20080090333 - Microelectronic packages fabricated at the wafer level and methods therefor
20080090427 - Microelectronic component with foam-metal posts
20080083977 - Edge connect wafer level stacking
20080083976 - Edge connect wafer level stacking
March 2008 - Tessera Lerner David Et Al. patents
20080067663 - Wafer level chip package and a method of fabricating thereof
February 2008 - Tessera Lerner David Et Al. patents
20080042249 - Microelectronic package
20080042250 - Stacked microelectronic assemblies and methods therefor
20080042274 - Components, methods and assemblies for stacked packages
20080036060 - Semiconductor chip packages and assemblies with chip carrier units
20080036100 - Solder elements with columnar structures and methods of making the same
20080029879 - Structure and method of making lidded chips
20080032457 - Structure and method of making sealed capped chips
January 2008 - Tessera Lerner David Et Al. patents
20080017879 - Methods and apparatus for packaging integrated circuit devices
20080012115 - Methods and apparatus for packaging integrated circuit devices
20080001241 - Structure and method of making lidded chips
20080002460 - Structure and method of making lidded chips
20080003402 - Fine pitch microcontacts and method for forming thereof
December 2007 - Tessera Lerner David Et Al. patents
20070290316 - Stacked packages and systems incorporating the same
November 2007 - Tessera Lerner David Et Al. patents
20070267730 - Wafer level semiconductor chip packages and methods of making the same
October 2007 - Tessera Lerner David Et Al. patents
20070246820 - Die protection process
20070235856 - Substrate for a microelectronic package and method of fabricating thereof
September 2007 - Tessera Lerner David Et Al. patents
20070221329 - Apparatus and method for distributing a liquid onto a surface of an item
20070205496 - Microelectronic packages and methods therefor
August 2007 - Tessera Lerner David Et Al. patents
20070190691 - Wafer level chip packaging
20070190747 - Wafer level packaging to lidded chips
20070176297 - Reworkable stacked chip assembly
July 2007 - Tessera Lerner David Et Al. patents
20070166876 - Components, methods and assemblies for multi-chip packages
20070152310 - Electrical ground method for ball stack package
June 2007 - Tessera Lerner David Et Al. patents
20070145536 - Compliant terminal mountings with vented spaces and methods
20070145550 - Microelectronic elements with compliant terminal mountings and methods for making the same
20070145560 - Packaged chip having features for improved signal transmission on the package
20070145564 - Sequential fabrication of vertical conductive interconnects in capped chips
20070146894 - Liquid lens with piezoelectric voltage converter
20070147816 - Camera modules with liquid optical elements
20070148819 - Microelectronic assemblies having very fine pitch stacking
20070148822 - Microelectronic packages and methods therefor
20070148824 - Compliant terminal mountings with vented spaces and methods
20070148941 - Microelectronic component with photo-imageable substrate
20070138498 - Methods and apparatus for packaging integrated circuit devices
20070138607 - Lead assemblies with offset portions and microelectronic assemblies with leads having offset portions
20070138612 - Stackable electronic device assembly and high g-force test fixture
20070138644 - Structure and method of making capped chip having discrete article assembled into vertical interconnect
20070124931 - Rigid flex interconnect via
20070126102 - Stacked microelectronic packages
May 2007 - Tessera Lerner David Et Al. patents
20070121305 - Multilayer wiring board for an electronic device
20070108613 - Microelectronic connection component
20070105282 - Micro lead frame packages and methods of manufacturing the same
20070105346 - Small chips with fan-out leads
20070094874 - Methods for forming connection structures for microelectronic devices
20070096160 - High frequency chip packages with connecting elements
20070096295 - Back-face and edge interconnects for lidded package
20070096296 - Manufacture of mountable capped chips
20070096311 - Structure and method of making capped chips having vertical interconnects
20070096312 - Structure and self-locating method of making capped chips
April 2007 - Tessera Lerner David Et Al. patents
20070077677 - Microelectronic packages and methods therefor
February 2007 - Tessera Lerner David Et Al. patents
20070040180 - Integrated circuit device
20070040257 - Chip packages with covers
20070042527 - Microelectronic package optionally having differing cover and device thermal expansivities
20070042562 - Integrated circuit device
20070034777 - Image sensor employing a plurality of photodetector arrays and/or rear-illuminated architecture
January 2007 - Tessera Lerner David Et Al. patents
20070020908 - Multilayer structure having a warpage-compensating layer
20070013044 - Packaged integrated circuits and methods of producing thereof
20070015310 - Polyceramic-coated tool for applying a flowable composition
December 2006 - Tessera Lerner David Et Al. patents
20060286717 - Stacked microelectronic assemblies having basal compliant layers
20060278962 - Microelectronic loop packages
20060278997 - Soldered assemblies and methods of making the same
20060275951 - Microelectronic assemblies having low profile connections
November 2006 - Tessera Lerner David Et Al. patents
20060261476 - Microelectronic assemblies having compliant layers
20060258139 - Manufacturing method for wiring circuit substrate
20060249857 - Microelectronic packages and methods therefor
20060244135 - Microelectronic component and assembly having leads with offset portions
October 2006 - Tessera Lerner David Et Al. patents
20060237836 - Microelectronic assemblies having compliant layers
20060225272 - Method of fabricating semiconductor chip assemblies
20060220234 - Wire bonded wafer level cavity package
20060223227 - Molding method for foldover package
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This listing is an abstract for educational and research purposes is only meant as a recent sample of applications filed, not a comprehensive history. Freshpatents.com is not affiliated or associated with Tessera Lerner David Et Al. in any way and there may be associated servicemarks. This data is also published to the public by the USPTO and available for free on their website. Note that there may be alternative spellings for Tessera Lerner David Et Al. with additional patents listed. Browse our Agent directory for other possible listings.
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