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Terence M. Potter patents

Recent patents with Terence M. Potter listed as an inventor - additional entries may be under other spellings.


Terence M. Potter - Related organizations: Apple Inc. patents

Operand cache control techniques

03/16/17 - 20170075810 - Techniques are disclosed relating to per-pipeline control for an operand cache. In some embodiments, an apparatus includes a register file and multiple execution pipelines. In some embodiments, the apparatus also includes an operand cache that includes multiple entries that each include multiple portions that are each configured to store an
Inventors: Andrew M. Havlir, Terence M. Potter, Liang-kai Wang

Operand cache flush, eviction, and clean techniques

01/26/17 - 20170024323 - An apparatus includes an operand cache for storing operands from a register file for use by execution circuitry. In some embodiments, eviction priority for the operand cache is based on the status of entries (e.g., whether dirty or clean) and the retention priority of entries. In some embodiments, flushes are
Inventors: Andrew M. Havlir, Terence M. Potter

Instruction source specification

12/01/16 - 20160350113 - Techniques are disclosed relating to specification of instruction operands. In some embodiments, this may involve assigning operands to source inputs. In one embodiment, an instruction includes one or more mapping values, each of which corresponds to a source of the instruction and each of which specifies a location value. In
Inventors: James S. Blomgren, Terence M. Potter

Data alignment and formatting for graphics processing unit

03/31/16 - 20160093014 - A data queuing and format apparatus is disclosed. A first selection circuit may be configured to selectively couple a first subset of data to a first plurality of data lines dependent upon control information, and a second selection circuit may be configured to selectively couple a second subset of data
Inventors: Liang Xia, Robert D. Kenney, Benjiman L. Goodman, Terence M. Potter

Gpu task scheduling

02/25/16 - 20160055610 - Techniques are disclosed relating to scheduling tasks for graphics processing. In one embodiment, a graphics unit is configured to render a frame of graphics data using a plurality of pass groups and the frame of graphics data includes a plurality of frame portions. In this embodiment, the graphics unit includes
Inventors: Robert D. Kenney, Benjiman L. Goodman, Terence M. Potter

Clock routing techniques

07/23/15 - 20150205324 - Techniques are disclosed relating to clock routing techniques in processors with both pipelined and non-pipelined circuitry. In some embodiments, an apparatus includes execution units that are non-pipelined and configured to perform instructions without receiving a clock signal. In these embodiments, one or more clock lines routed throughout the apparatus do
Inventors: Andrew M. Havlir, James S. Blomgren, Terence M. Potter

Operand cache design

02/26/15 - 20150058573 - Instructions may require one or more operands to be executed, which may be provided from a register file. In the context of a GPU, however, a register file may be a relatively large structure, and reading from the register file may be energy and/or time intensive An operand cache may
Inventors: James S. Blomgren, Terence M. Potter, Timothy A. Olson, Andrew M. Havlir

Intelligent caching for an operand cache

02/26/15 - 20150058572 - Instructions may require one or more operands to be executed, which may be provided from a register file. In the context of a GPU, however, a register file may be a relatively large structure, and reading from the register file may be energy and/or time intensive An operand cache may
Inventors: Timothy A. Olson, Terence M. Potter, James S. Blomgren, Andrew M. Havlir

Hint values for use with an operand cache

02/26/15 - 20150058571 - Instructions may require one or more operands to be executed, which may be provided from a register file. In the context of a GPU, however, a register file may be a relatively large structure, and reading from the register file may be energy and/or time intensive An operand cache may
Inventors: Terence M. Potter, Timothy A. Olson, James S. Blomgren, Andrew M. Havlir, Michael Geary

Extended multiply

02/26/15 - 20150058389 - Techniques are disclosed relating to performing extended multiplies without a carry flag. In one embodiment, an apparatus includes a multiply unit configured to perform multiplications of operands having a particular width. In this embodiment, the apparatus also includes multiple storage elements configured to store operands for the multiply unit. In
Inventors: James S. Blomgren, Terence M. Potter

Instruction source specification

02/05/15 - 20150039867 - Techniques are disclosed relating to specification of instruction operands. In some embodiments, this may involve assigning operands to source inputs. In one embodiment, an instruction includes one or more mapping values, each of which corresponds to a source of the instruction and each of which specifies a location value. In
Inventors: James S. Blomgren, Terence M. Potter

Type conversion using floating-point unit

02/05/15 - 20150039661 - Techniques are disclosed relating to type conversion using a floating-point unit. In one embodiment, to convert a floating-point value to a normalized integer format, a floating-point unit is configured to perform an operation to generate a result having a significant portion and an exponent portion, where the operation includes multiplying
Inventors: James S. Blomgren, Terence M. Potter

Multi-threaded gpu pipeline

02/05/15 - 20150035841 - Techniques are disclosed relating to a multithreaded execution pipeline. In some embodiments, an apparatus is configured to assign a number of threads to an execution pipeline that is an integer multiple of a minimum number of cycles that an execution unit is configured to use to generate an execution result
Inventors: Andrew M. Havlir, James S. Blomgren, Terence M. Potter

Apparatus implementing instructions that impose pipeline interdependencies

01/08/15 - 20150009223 - Techniques are disclosed relating to implementation of gradient-type graphics instructions. In one embodiment, an apparatus includes first and second execution pipelines and a register file. In this embodiment, the register file is coupled to the first and second execution pipelines and configured to store operands for the first and second
Inventors: Andrew M. Havlir, Terence M. Potter


### Terence M. Potter patent invention listings

The bibliographic references displayed about Terence M. Potter's patents are for a recent sample of Terence M. Potter's publicly published patent applications. The inventor/author may have additional bibliographic citations listed at the USPTO.gov. FreshPatents.com is not associated or affiliated in any way with the author/inventor or the United States Patent/Trademark Office but is providing this non-comprehensive sample listing for educational and research purposes using public bibliographic data published and disseminated from the United States Patent/Trademark Office public datafeed. This information is also available for free on the USPTO.gov website. If Terence M. Potter filed recent patent applications under another name, spelling or location then those applications could be listed on an alternate page. If no bibliographic references are listed here, it is possible there are no recent filings or there is a technical issue with the listing--in that case, we recommend doing a search on the USPTO.gov website.

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