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  Systems and methods of plating via interconnectsUSPTO Application #: 20050178657Title: Systems and methods of plating via interconnects Abstract: Methods for filling high aspect ratio vias with conductive material. At least one high aspect ratio via is formed in the backside of a semiconductor substrate. The at least one via is closed at one end by a conductive element forming a conductive structure of the semiconductor substrate. The backside of the semiconductor substrate is exposed to an electroplating solution containing a conductive material in solution with the active surface semiconductor substrate isolated therefrom. An electric potential is applied across the conductive element through the electroplating solution and a conductive contact pad in direct or indirect electrical communication with the conductive element at the closed end of the at least one via (or forming such conductive element) to cause conductive material to electrochemically deposit from the electroplating solution and fill the at least one via. Semiconductor devices and in-process semiconductor devices are also disclosed. (end of abstract) Agent: Trask Britt - Salt Lake City, UT, US Inventors: Kyle K. Kirby, Warren M. Farnworth USPTO Applicaton #: 20050178657 - Class: 204194000 (USPTO) Related Patent Categories: Chemistry: Electrical And Wave Energy, Apparatus, Electrolytic
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