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  Systems and methods for wafer polishingUSPTO Application #: 20060189257Title: Systems and methods for wafer polishing Abstract: An electromagnetic polish head (100) comprises at least one electromagnet. An embodiment may also include the addition of a slurry component or components that can be affected by an electromagnetic field. During polishing or planarization, a field or fields may be generated by the polish head (100) to affect the polishing of a wafer by attracting or repelling the slurry to a portion or portions of the substrate. (end of abstract)
Agent: Lsi Logic Corporation - Milpitas, CA, US Inventor: Robert Wayne Donis USPTO Applicaton #: 20060189257 - Class: 451005000 (USPTO) Related Patent Categories: Abrading, Precision Device Or Process - Or With Condition Responsive Control, Computer Controlled The Patent Description & Claims data below is from USPTO Patent Application 20060189257. Brief Patent Description - Full Patent Description - Patent Application Claims
CROSS-REFERENCE TO RELATED APPLICATIONS [0001] This patent application is a continuation-in-part of, and claims priority to, co-pending and commonly-assigned U.S. patent application Ser. No. 11/063,384, filed Feb. 22, 2005, entitled "Systems and Methods for Wafer Polishing," which is incorporated in its entirety herein by reference. BACKGROUND [0002] A. Technical Field [0003] The present invention relates generally to the field of semiconductor wafer fabrication, and more particularly, to chemical mechanical planarization or polishing (CMP) of wafers. [0004] B. Background of the Invention [0005] The manufacturing of semiconductor devices, including integrated circuits, microchips, or chips, often involves multiple processes. For example, a semiconductor device may comprise a substrate on which a number of films of various chemical compositions are layered. During manufacturing, a layer's thickness or uniformity may need to be within a set limit for the final device to function properly. Thus, at one or more times during the manufacturing of a semiconductor device, the wafer under development may need to be planarized. One method for planarizing substrates utilized in semiconductor manufacturing is called chemical mechanical polishing or planarization. Chemical mechanical polishing or planarization (CMP) is a polishing process that uses a combination of mechanical removal and chemical etching to planarize a wafer's surface. [0006] A typical CMP apparatus comprises a polish head (also referred to as a carrier head) and a polishing pad. The polish head is a tool fixture that holds a wafer during the CMP process. Typically, the wafer is held in place, in an inverted position, against the polish head through vacuum pressure. A polishing pad faces the wafer when the wafer is positioned on the polish head. During a CMP process, the polish head presses the wafer against the polishing pad. Depending on the particular CMP apparatus configuration, both the polishing pad and the polish head may rotate to create the mechanical polishing. Typically, a chemical etching solution is continuously pumped onto the polishing pad during the CMP process. [0007] The chemical etching solution, also referred to as the "slurry," is normally a mixture of an abrasive or abrasives and other chemicals. For example, a slurry may contain silica or alumina particles dispersed and suspended in an acidic or a basic etching solution, depending on the application. [0008] CMP processes are normally used to planarize silicon wafers at both post-ingot wafer slicing and at various levels of the chip development. For example, once the bare silicon wafer is cut from the silicon ingot, its surface is usually rough and uneven. Generally, there are strict tolerances as to the planarity of the wafer before it can be used to produce yielding chips. To achieve an acceptable level of planarity, CMP is typically employed to planarize the wafer. [0009] Also, during the production of an integrated circuit, it is typically very desirable that the wafer's surface be planar throughout each process. However, due to the nature of certain processes, a non-planar surface may be produced. This non-planar surface may lead to various problems in production, which generally leads to a reduced yield of functional chips. For example, due to uneven topography of the wafer, possibly resulting from prior deposition cycles or other manufacturing processes, reactants may grow uneven layers onto the surface of the wafer. Once again, CMP is often used to reduce the wafer's altitude variations so that subsequent process steps can be performed. [0010] Although the use of CMP processing during the manufacturing of semiconductor manufacturing helps increase yield, the CMP process has limits. Currently, the CMP process may not be able to planarize sufficiently a wafer that possesses too great a disparity in wafer surface altitude. Furthermore, current CMP process may introduce defects into wafers by over-polishing or under-polishing certain areas. These problems may lead-to decreased yields of semiconductor products. SUMMARY OF THE INVENTION [0011] In general, exemplary embodiments of the invention are concerned with an electromagnetic polish head comprising at least one electromagnet. An embodiment may also include employing a slurry component or components that can be affected by an electromagnetic field, such as, for example, a polarized or polarizable slurry component or components. In one embodiment, during polishing or planarization, a field or fields may be generated by the polish head to affect the polishing of a wafer by attracting or repelling the slurry component or components to a portion or portions of the substrate. In an embodiment, the field or fields generated by an electromagnetic polish head may be varied during the polishing process. An embodiment of the present invention may include a contoller, computer system, or processing unit to monitor and/or control the fields generated by the electromagnetic polish head. BRIEF DESCRIPTION OF THE DRAWINGS [0012] Reference will be made to embodiments of the invention, examples of which may be illustrated in the accompanying figures. These figures are intended to be illustrative, not limiting. Although the invention is generally described in the context of these embodiments, it should be understood that it is not intended to limit the scope of the invention to these particular embodiments. [0013] FIG. 1 illustrates a partial profile of a chemical mechanical polishing apparatus, including an embodiment of an electromagnetic polish head and slurry. [0014] FIG. 2 is a top view of the embodiment of the electromagnetic polish head depicted in FIG. 1. [0015] FIG. 3 is a top view of an alternate embodiment of an electromagnetic polish head. [0016] FIG. 4 is a top view of an alternate embodiment of an electromagnetic polish head. [0017] FIG. 5 is a top view of an alternate embodiment of an electromagnetic polish head. [0018] FIG. 6 is a block diagram of an alternate embodiment of an electromagnetic polish head system. [0019] FIG. 7 is a flow chart illustrating an embodiment of a method for utilizing an electromagnetic polish head and slurry to control the polishing or planarization of a substrate. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Continue reading... Full patent description for Systems and methods for wafer polishing Brief Patent Description - Full Patent Description - Patent Application Claims Click on the above for other options relating to this Systems and methods for wafer polishing patent application. ###  How KEYWORD MONITOR works... a FREE service from FreshPatents1. Sign up (takes 30 seconds). 2. Fill in the keywords to be monitored. 3. Each week you receive an email with patent applications related to your keywords. Start now! - Receive info on patent apps like Systems and methods for wafer polishing or other areas of interest. ### Previous Patent Application: Systems and methods for wafer polishing Next Patent Application: Process via worktable of relative coordinates Industry Class: Abrading ### FreshPatents.com Support Thank you for viewing the Systems and methods for wafer polishing patent info. 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