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  Systems and methods for selectively decoupling a parallel extended instruction pipelineUSPTO Application #: 20070074004Title: Systems and methods for selectively decoupling a parallel extended instruction pipeline Abstract: Systems and methods for selectively decoupling a parallel extended processor pipeline. A main processor pipeline and parallel extended pipeline are coupled via an instruction queue. The main pipeline can instruct the parallel pipeline to execute instructions directly or to begin fetching and executing its own instructions autonomously. During autonomous operation of the parallel pipeline, instructions from the main pipeline accumulate in the instruction queue. The parallel pipeline can return to main pipeline controlled execution through a single instruction. A light weight mechanism in the form of a condition code as seen by the main processor is designed to allow intelligent decision maximizing overall performance to be made in run-time if further instructions should be issued to the parallel extended pipeline based on the queue status. (end of abstract) Agent: Hunton & Williams LLP Intellectual Property Department - Washington, DC, US Inventors: Kar-Lik Wong, Carl Norman Graham, Seow Chuan Lim, Simon Jones, Yazid Nemouchi, Aris Aristodemou USPTO Applicaton #: 20070074004 - Class: 712034000 (USPTO) Related Patent Categories: Electrical Computers And Digital Processing Systems: Processing Architectures And Instruction Processing (e.g., Processors), Processing Architecture, Microprocessor Or Multichip Or Multimodule Processor Having Sequential Program Control, Including Coprocessor The Patent Description & Claims data below is from USPTO Patent Application 20070074004. Brief Patent Description - Full Patent Description - Patent Application Claims
CROSS REFERENCE TO RELATED APPLICATIONS [0001] This application claims priority to U.S. Provisional Patent Application No. 60/721,108 titled "SIMD Architecture and Associated Systems and Methods," filed Sep. 28, 2005, the disclosure of which is hereby incorporated by reference in its entirety. FIELD OF THE INVENTION [0002] The invention relates generally to embedded microprocessor architecture and more specifically to systems and methods for selectively decoupling an extended instruction pipeline from a main pipeline in an microprocessor-based system. BACKGROUND OF THE INVENTION [0003] Processor extension logic is utilized to extend a microprocessor's capability. Typically, this logic is in parallel to and accessible by the main processor pipeline. It is often used to perform specific, repetitive, computationally intensive functions thereby freeing up the main processor pipeline. [0004] In conventional microprocessors, there are essentially two types of parallel pipeline architectures: tightly coupled and loosely coupled, or decoupled. In the former, instructions are fetched and executed serially in the main processor pipeline. If the instruction is an instruction to be processed by the extension logic, the instruction is sent to that logic. Because every instruction originates from the main pipeline the two pipelines are said to be tightly coupled. This limits the degree of concurrency exploitable between the pipelines. [0005] In the second architecture, the parallel instruction pipeline containing the extension logic is capable of fetching and executing its own instructions and hence maximizing concurrency. However, control and synchronization between the two pipelines becomes difficult when programming a processor having such a decoupled architecture. Thus, there exists a need for a parallel pipeline architecture that can fully exploit the advantages of parallelism without suffering from the design complexity of loosely or completely decoupled pipelines. SUMMARY OF THE INVENTION [0006] Accordingly, at least one embodiment of the invention provides a microprocessor architecture. The microprocessor architecture according to this embodiment comprises a first processor instruction pipeline, comprising a front end portion and a rear portion, a second processor instruction pipeline, comprising a front end portion and a rear portion, and an instruction queue coupling the first and second instruction pipeline between their respective front end and rear portions. [0007] Another embodiment of the invention provides a method of dynamically decoupling a parallel extended processor pipeline from a main processor pipeline. The method according to this embodiment comprises sending an instruction from the main processor pipeline to the parallel extended processor pipeline instructing the parallel extended processor pipeline to operate autonomously, operating the parallel extended processor pipeline autonomously, storing subsequent instructions from the main processor pipeline to the parallel extended processor pipeline in an instruction queue, executing an instruction with the parallel extended processor pipeline to cease autonomous execution, and thereafter executing instructions supplied by the main processor pipeline in the queue. [0008] Still a further embodiment of the invention provides a method of performing dynamically controlled parallel instruction processing in a microprocessor. The method according to this embodiment comprises fetching and executing instructions with a main processor pipeline, sending instructions from the main processor pipeline to a parallel extended processor pipeline via an instruction queue coupling the two pipelines, and if the instruction is to an instruction to be executed by the parallel extended pipeline, executing that instruction with the parallel extended pipeline, otherwise if the instruction is an instruction instructing that parallel extended pipeline to begin autonomous execution, thereafter fetching and executing instructions autonomously with the parallel extended pipeline independent of the main pipeline's instruction fetches, and storing instructions from main pipeline for the parallel extended pipeline in the instruction queue until autonomous processing has ceased. [0009] These and other embodiments and advantages of the present invention will become apparent from the following detailed description, taken in conjunction with the accompanying drawings, illustrating by way of example the principles of the invention. BRIEF DESCRIPTION OF THE DRAWINGS [0010] In order to facilitate a fuller understanding of the present disclosure, reference is now made to the accompanying drawings, in which like elements are referenced with like numerals. These drawings should not be construed as limiting the present disclosure, but are intended to be exemplary only. [0011] FIG. 1 is a functional block diagram illustrating a microprocessor-based system including a main processor core and a SIMD media accelerator according to at least one embodiment of the invention; [0012] FIG. 2 is a block diagram illustrating a conventional multistage microprocessor pipeline having a pair of parallel data paths; [0013] FIG. 3 is a block diagram illustrating another conventional multiprocessor design having a pair of parallel processor pipelines; [0014] FIG. 4 is a block diagram illustrating a dynamically decoupleable multi-stage microprocessor pipeline according to at least one embodiment of the invention; and [0015] FIG. 5 is a flow chart detailing the steps of a method for sending instructions for operating a main processor pipeline and an extended processor pipeline according to at least one embodiment of the invention; and [0016] FIG. 6 is a flow chart detailing the steps of a method for dynamically decoupling an extended processor pipeline from a main pipeline according to at least one embodiment of the invention. DETAILED DESCRIPTION [0017] The following description is intended to convey a thorough understanding of the embodiments described by providing a number of specific embodiments and details involving microprocessor architecture and systems and methods for selectively decoupling an extended instruction pipeline from a main instruction pipeline. It should be appreciated, however, that the present invention is not limited to these specific embodiments and details, which are exemplary only. It is further understood that one possessing ordinary skill in the art, in light of known systems and methods, would appreciate the use of the invention for its intended purposes and benefits in any number of alternative embodiments, depending upon specific design and other needs. [0018] Referring now to FIG. 1, a functional block diagram illustrating a microprocessor-based system 5 including a main processor core 10 and a SIMD media accelerator 50 according to at least one embodiment of the invention The diagram illustrates a microprocessor 5 comprising a standard single instruction single data (SISD) processor core 10 having a multistage instruction pipeline 12 and a SIMD media engine 50. In various embodiments, the processor core 10 may be a processor core such as the ARC 700 embedded processor core available from ARC, International of Elstree, United Kingdom, and as described in provisional patent application No. 60/572,238 filed May 19, 2004 entitled "Microprocessor Architecture" which, is hereby incorporated by reference in its entirety. Alternatively, in various embodiments, the processor core may be a different processor core. Continue reading... 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