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  Systems and methods for implementing logic in a processorRelated Patent Categories: Electrical Computers: Arithmetic Processing And Calculating, Electrical Digital Calculating Computer, Particular Function PerformedThe Patent Description & Claims data below is from USPTO Patent Application 20060173941. Brief Patent Description - Full Patent Description - Patent Application Claims
FIELD [0001] The present invention is in the field of implementing logic in a processor. More particularly, the invention simplifies the circuitry needed to implement logic functions in an arithmetic/logic unit of a computer processor. BACKGROUND [0002] Many different types of computing systems have attained widespread use around the world. These computing systems include personal computers, servers, mainframes and a wide variety of stand-alone and embedded computing devices. Sprawling client-server systems exist, with applications and information spread across many PC networks, mainframes and minicomputers. In a distributed system connected by networks, a user may access many application programs, databases, network systems, operating systems and mainframe applications. Computers provide individuals and businesses with a host of software applications including word processing, spreadsheet, accounting, e-mail, voice over Internet protocol telecommunications, and facsimile. [0003] Users of digital processors such as computers continue to demand greater and greater performance from such systems for handling increasingly complex and difficult tasks. In addition, processing speed has increased much more quickly than that of main memory accesses. As a result, cache memories, or caches, are often used in many systems to increase performance in a relatively cost-effective manner. Many modem computers also support "multi-tasking" or "multi-threading" in which two or more programs run concurrently with various resources in the processor pipeline allocated to two different threads on any given cycle. [0004] Modern computers include at least a first level cache L1 and typically a second level cache L2, for increasing the speed of memory access by the processor. This dual cache memory system enables storing frequently accessed data and instructions close to the execution units of the processor to minimize the time required to transmit data to and from memory. L1 cache is typically on the same chip as the execution units. L2 cache is external to the processor chip but physically close to it. Ideally, as the time for execution of an instruction nears, instructions and data are moved to the L2 cache from a more distant memory. When the time for executing the instruction is near imminent, the instruction and its data, if any, is advanced to the L1 cache. [0005] A common architecture for high performance, single-chip microprocessors is the reduced instruction set computer (RISC) architecture characterized by a small simplified set of frequently used instructions for rapid execution. Thus, in a RISC architecture, a complex instruction comprises a small set of simple instructions that are executed in steps very rapidly. These steps are performed in execution units adapted to execute specific simple instructions. These execution units typically comprise load/store units, integer Arithmetic/Logic Units, floating point Arithmetic/Logic Units, and Graphical Logic Units. In an architecture with multiple execution units, instructions can be issued to two or more of these units to be executed in parallel. [0006] The Arithmetic/Logic Unit (ALU) performs arithmetic operations and logic operations on operands provided to it. For example, FIG. 1 shows a typical architecture of an arithmetic/logic unit in a digital processor. Two N:1 multiplexers 102 and 104 receive operands from different sources. One such source is the result of instructions that are just finishing execution received from 4:1 multiplexer 118. Each operand, A and B, is latched in latches 106 and 108, respectively. The latch contents are forwarded to the execution macros: an adder 110, a rotator 112, a logical unit 114, and other functions unit 116. [0007] Adder 110 adds the operands, A and B, received from latches 106 and 108. To perform the addition the adder must perform a Generate function 120 and a Propagate function 122. The Generate function is the bitwise logical AND of the two operands. The Propagate function is the bitwise logical OR of the two operands. Rotator 112 receives an operand and rotates it. Logical unit 114 performs various logical functions such as AND, OR, XOR, etc. In a PowerPC architecture there are 8 basic types of logical operations provided by the Instruction Set Architecture (ISA). These are: AND, NAND, OR, NOR, ANDC, ORC, XOR, and EQV. Their values are given in Table 1. TABLE-US-00001 TABLE 1 A A A A A and nand or nor andc A orc A xor A eqv A B B B B B B B B B 0 0 0 1 0 1 0 1 0 1 0 1 0 1 1 0 0 0 1 0 1 0 0 1 1 0 1 1 1 0 1 1 1 0 1 0 0 1 0 1 [0008] FIG. 2 shows an embodiment of a logical unit 114. The operands and their complements are input to certain ones of three-input NAND gates 202, 204, 206, and 208 as shown. The output of these NAND gates is a 4-input NAND gate 210. Selectors C1, C2, C3, and C4 determine the operation performed. By appropriate selection, all eight of the logical operations of Table 1 can be performed. This logic configuration requires a considerable amount of circuitry for its implementation, and thus, more surface area on the processor chip. Further, the logic is slow because the data flows through two stages of multiple input gates. [0009] Thus, there is a need for logic implementation in the arithmetic/logic unit of a digital processor that increases speed and requires less circuitry to implement. SUMMARY [0010] The problems identified above are in large part addressed by systems, methods and media for implementing logic in a digital processor as disclosed herein. In one embodiment, a digital system with an arithmetic/logic unit for executing arithmetic and logical instructions comprises a circuit arrangement that minimizes the circuitry required to perform basic logic operations. Propagate and Generate functions are performed and the results are then sent to execution macros for executing the instruction. [0011] Embodiments comprise a method for implementing logic in an Arithmetic/Logic Unit (ALU). The method comprises receiving two operands and computing a generate function result and a propagation function result. The generate function result is the logical AND or the logical NAND of the two operands. The propagate function result is the logical OR or the logical NOR of the two operands. An execution macro of the ALU computes the complement of the generate function result. An execution macro of the ALU computes the complement of the propagate function result. An execution macro also receives the generate function result and the propagate function result and computes a logical complement and a logical NAND or a logical AND to produce a logical XOR of the two operands and a logical EQV of the two operands. [0012] One embodiment, comprises a generate function preceding an execution macro, that generates a logical AND or a logical NAND of two operands. A propagate function preceding an execution macro, generates a logical OR or a logical NOR of the two operands. Complementation circuitry within an execution macro that receives a generate function result, computes the complement of the generate function. Complementation circuitry within an execution macro that receives a propagate function result, computes the complement of the propagate function. An execution macro comprising an inverter and a NAND or AND gate that receives a generate function result and a propagate function result, computes a logical XOR of the two operands or a logical EQV of the two operands. [0013] In another embodiment, a computer system for processing instructions and data, comprises a memory for storing the instructions and data. A generate function, external to an adder, generates a logical AND or a logical NAND of two operands of the data received from the memory. A propagate function, external to the adder, generates a logical OR or a logical NOR of the two operands. The adder receives a result from the generate function and a result from the propagate function and computes the sum of the two operands. An execution macro, comprising an inverter and a NAND or AND gate, receives a generate function result and a propagate function result and computes operations comprising a logical XOR of the two operands and a logical EQV of the two operands. Complementation circuitry computes the complement of the generate function and the complement of the propagate function; BRIEF DESCRIPTION OF THE DRAWINGS [0014] Other objects and advantages of the invention will become apparent upon reading the following detailed description and upon reference to the accompanying drawings in which, like references may indicate similar elements: [0015] FIG. 1 depicts an arithmetic/logic unit in a digital processor. [0016] FIG. 2 depicts an implementation of logical functions in an arithmetic/logic unit. [0017] FIG. 3 depicts a digital system comprising a processor and cache memory. [0018] FIG. 4 depicts a multi-threading processor with a thread multiplexer for selecting thread instructions to be processed by the multi-threading processor. [0019] FIG. 5 depicts an arithmetic/logic unit with a reduced-circuitry implementation. [0020] FIG. 6 depicts a flow chart for implementing logic operations in an arithmetic/logic unit. Continue reading... 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