| System to detect and identify errors in control information, read data and/or write data -> Monitor Keywords |
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  System to detect and identify errors in control information, read data and/or write dataThe Patent Description & Claims data below is from USPTO Patent Application 20070271495. Brief Patent Description - Full Patent Description - Patent Application Claims
FIELD OF THE INVENTION [0001]The present invention generally relates to integrated circuit devices and/or high speed signaling of such devices. BACKGROUND OF THE RELATED ART [0002]In chip communications, errors may occur in transferring information between integrated circuits. For example, noise, crosstalk and/or inter-symbol interference may alter a signal resulting in erroneously received information. An integrated circuit may have an error detection circuit and/or software for detecting erroneously received and/or transmitted information. For example, an integrated circuit may have a checksum and/or parity-checking scheme to detect when erroneous information is received. Further, an integrated circuit may have an error checking and correcting ("ECC") scheme (ECC is also known as error correction code) that not only detects errors in information, but also corrects the error in the information. [0003]However, when large amounts of information are transferred between integrated circuits, complicated error detection and correction schemes may require too much bandwidth and may introduce latencies that degrade system performance. Further, in certain applications, errors in information on one interconnect (e.g. control or address) may result in other information being erroneously transferred or received and thus it may be difficult to determine what the root cause of the error was. BRIEF DESCRIPTION OF THE DRAWING [0004]Embodiments are illustrated by way of example, and not by way of limitation, in the figures of the accompanying drawings, which like reference numerals refer to similar elements. [0005]FIG. 1 illustrates a system 100 having error detecting circuits according to an embodiment. [0006]FIGS. 2A-B is a flow chart that illustrates a method 200 to detect different types of errors according to an embodiment. [0007]FIG. 3 illustrates an integrated circuit memory device 300 having an error detection circuit according to an embodiment. [0008]FIG. 4 illustrates an integrated circuit buffer device 400 having an error detection circuit according to an embodiment. [0009]FIG. 5 illustrates a memory system 500 that detects errors according to an embodiment. [0010]FIG. 6 illustrates a device 600 including a plurality of integrated circuit memory devices and a buffer device having error detection circuits according to an embodiment. DETAILED DESCRIPTION [0011]An integrated circuit, such as an integrated circuit ("IC") memory or buffer device, method, and/or system, among other embodiments, generates a plurality of error codes, such as cycle redundancy checking ("CRC") codes, corresponding to control information, write data and read data transactions. The plurality of separately generated CRC codes corresponding to control information, write data and read data is logged, or stored in respective storage circuits, such as circular buffers. The stored plurality of CRC codes corresponding to each transaction may be used to determine whether an error occurred during a particular transaction and thus whether a retry of the particular transaction, or multiple retries, is issued. The integrated circuit includes a compare circuit to compare a CRC code generated by the integrated circuit with a CRC code provided by a controller device. A CRC code corresponding to control information is transferred to a controller device using a data mask signal line that is not being used during a read transaction. The CRC code generated by the integrated circuit then may be compared to a CRC code generated by the controller device to determine whether an error occurred in the control information. The controller device generates and stores a plurality of CRC codes, corresponding to control information, write data and read data. The controller device then compares the CRC codes generated by the controller device with CRC codes generated and stored in the integrated circuit to determine whether an error has occurred during a particular transaction. [0012]An integrated circuit includes a first encode circuit to encode a first code representing write data, a second encode circuit to encode a second code representing read data and a third encode circuit to encode a third code representing control information. The control information includes address information and/or a memory command for accessing a storage array. A first, second and third compression circuit compresses the first, second and third codes to provided compressed first, second and third codes. In another embodiment, a single compression circuit compresses the first, second and third codes to provide a single compressed code. The first and second compressed codes are output to a controller device for detecting errors in transferred write and read data. A compare circuit compares the third compressed code that represents control information with a compressed code from a controller device to determine whether an error occurred in transferring the control information. [0013]In a method embodiment of operating an integrated circuit, a first code that represents write data to be stored in a storage array is generated and stored. A second code that represents read data obtained from a storage array is generated and stored. A third code that represents control information used to access the storage array is generated and stored. A fourth code from a controller device is compared with the third code to generate an error signal. A signal indicating retrying a memory transaction is generated in response to the error signal. [0014]In a method embodiment of operating an integrated circuit, the first code is transferred to a controller device that compares the first code to a code generated by the controller device to generate an error signal that represents an occurrence of erroneous write data. The second code is transferred to a controller device that compares the second code to a code generated by the controller device to generate an error signal that represents an occurrence of erroneous read data. The third code is transferred to a controller device that compares the third code to a code generated by the controller device to generate an error signal that represents an occurrence of erroneous control information. A retry of read data, write data and/or control information may then be initiated in response to the corresponding error signals. [0015]In a system embodiment, a controller device includes a first, second and third circuit to store first, second and third codes that represent write data to be stored in a storage array, read data obtained from the storage array and control information used to access the storage array. An integrated circuit includes a fourth, fifth and sixth circuit to store fourth, fifth and sixth codes that represent write data to be stored in a storage array, read data obtained from the storage array and control information used to access the storage array. The controller device includes a compare circuit to compare 1) the third code with the sixth code to determine when to retry a memory command or retransfer control information, 2) the first code with the fourth code to determine when to retransfer the write data from the controller device to the IC memory device, and 3) the second code with the fifth code to determine when to retransfer the read data from the IC memory device to the controller device. [0016]FIG. 1 illustrates a system 100 including an IC 110, such as a controller device or other master device, coupled to an IC 150, such as an IC memory device or buffer device, by an interconnect 160. ICs 110 and 150 include error detection ("ED") circuits 180 and 190, respectively, for detecting hierarchal types of errors when there is a limited amount of available bandwidth for transferring information between the ICs 110 and 150. For example, errors in different types of memory transactions or operations may be detected by using corresponding error codes stored in ICs 110 and 150. A memory transaction may include providing control information, such as address information and/or memory commands, to access a storage array in an IC memory device. Also, a memory transaction may include providing write data to be stored in a storage array of the IC memory device. A memory transaction may also include accessing, by a memory controller, read data from the storage array of the IC memory device. ED circuits 180 and 190 are able to detect whether an error occurred in the control information, write data and/or read data, singly or in combination. [0017]ED circuit 190 includes receivers 140, 141 and 142 coupled to an interconnect 160 that includes signal lines or paths 161-164. Receiver 140 is coupled to a signal line 161 that carries control information and receiver 141 is coupled to a signal line 162 that carries mask information during a write operation, or other signal line that has available bandwidth when providing error information or CRC codes. In an embodiment, signal line 162 is included with other signal lines that transfer write and/or read data, such as signal line 163. Receiver 142 is coupled to signal line 163 that carries data information, such as write data to be stored in a storage array or read data stored in a storage array. Transmitter 143 is coupled to signal line 163 while transmitter 144 is coupled to signal line 164. Signal line 164 may be included in a serial data bus, such as a SMBus bus, that provides CRC codes from ED circuit 190 to IC 110. In an alternate embodiment, signal line 164 is a signal line that has available bandwidth when providing error information. In another embodiment, signal line 164 is a signal line that has available bandwidth used during a typical memory operation, such as transferring read and/or write data. [0018]Control information is provided by receiver 140 to encode circuit 151 that encodes the control information into an error code. Encode circuit 151 then outputs the encoded control information to circular buffer 158 and compression (compress) circuit 152. Compression circuit 152 compresses the encoded control information or CRC code for control information. Compare circuit 153 compares an error code from IC 110 via receiver 141 with a compressed encoded control information from compression circuit 152 in order to determine when an error occurs in the control information. When the received code from IC 110 does not match or is not equal to the code from compression circuit 152, compare circuit 153 generates an error signal indicating that an error occurred in control information. The error signal from compare circuit 153 causes IC 150 to generate a retry signal to IC 110 which then retries or repeats sending the control information on signal line 161. [0019]In another embodiment, an error signal is provided in an IC buffer device that rejects and/or ignores any subsequent read data and/or write data (to and/or from the IC buffer device) until the error is corrected by, for example, resending the control information (to or from) the IC buffer device. Ignoring or rejecting incoming write and/or read data is done in order to avoid any possible data contamination due to receiving erroneous control information. If data is contaminated or erroneous due to receiving erroneous control information, future transactions may be interpreted incorrectly. [0020]Control information from receiver 140 may be provided to IC memory core, such as column decoder circuit 302 and/or row decoder 303, to access storage arrays in IC memory device 300 as illustrated in FIG. 3 and described below. In another embodiment, control information is provided to request an address circuit 440 in IC buffer device 400 as illustrated in FIG. 4 and described below. Continue reading... Full patent description for System to detect and identify errors in control information, read data and/or write data Brief Patent Description - Full Patent Description - Patent Application Claims Click on the above for other options relating to this System to detect and identify errors in control information, read data and/or write data patent application. ###  How KEYWORD MONITOR works... a FREE service from FreshPatents1. Sign up (takes 30 seconds). 2. Fill in the keywords to be monitored. 3. Each week you receive an email with patent applications related to your keywords. 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