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  System, method and storage medium for bus calibration in a memory subsystemRelated Patent Categories: Electrical Computers And Digital Processing Systems: Memory, Storage Accessing And Control, Memory ConfiguringThe Patent Description & Claims data below is from USPTO Patent Application 20080040571. Brief Patent Description - Full Patent Description - Patent Application Claims
CROSS REFERENCE TO RELATED APPLICATIONS [0001] This application is a continuation application of U.S. Ser. No. 10/977,048, filed Oct. 29, 2004, the contents of which are incorporated by reference herein in their entirety. BACKGROUND OF THE INVENTION [0002] The invention relates to a memory subsystem and in particular, to bus calibration in a memory subsystem. [0003] Computer memory subsystems have evolved over the years, but continue to retain many consistent attributes. Computer memory subsystems from the early 1980's, such as the one disclosed in U.S. Pat. No. 4,475,194 to LaVallee et al., of common assignment herewith, included a memory controller, a memory assembly (contemporarily called a basic storage module (BSM) by the inventors) with array devices, buffers, terminators and ancillary timing and control functions, as well as several point-to-point busses to permit each memory assembly to communicate with the memory controller via its own point-to-point address and data bus. FIG. 1 depicts an example of this early 1980 computer memory subsystem with two BSMs, a memory controller, a maintenance console, and point-to-point address and data busses connecting the BSMs and the memory controller. [0004] FIG. 2, from U.S. Pat. No. 5,513,135 to Dell et al., of common assignment herewith, depicts an early synchronous memory module, which includes synchronous dynamic random access memories (DRAMs) 8, buffer devices 12, an optimized pinout, an interconnect and a capacitive decoupling method to facilitate operation. The patent also describes the use of clock re-drive on the module, using such devices as phase lock loops (PLLs). [0005] FIG. 3, from U.S. Pat. No. 6,510,100 to Grundon et al., of common assignment herewith, depicts a simplified diagram and description of a memory system 10 that includes up to four registered dual inline memory modules (DIMMs) 40 on a traditional multi-drop stub bus channel. The subsystem includes a memory controller 20, an external clock buffer 30, registered DIMMs 40, an address bus 50, a control bus 60 and a data bus 70 with terminators 95 on the address bus 50 and data bus 70. [0006] FIG. 4 depicts a 1990's memory subsystem which evolved from the structure in FIG. 1 and includes a memory controller 402, one or more high speed point-to-point channels 404, each connected to a bus-to-bus converter chip 406, and each having a synchronous memory interface 408 that enables connection to one or more registered DIMMs 410. In this implementation, the high speed, point-to-point channel 404 operated at twice the DRAM data rate, allowing the bus-to-bus converter chip 406 to operate one or two registered DIMM memory channels at the full DRAM data rate. Each registered DIMM included a PLL, registers, DRAMs, an electrically erasable programmable read-only memory (EEPROM) and terminators, in addition to other passive components. [0007] As shown in FIG. 5, memory subsystems were often constructed with a memory controller connected either to a single memory module, or to two or more memory modules interconnected on a `stub` bus. FIG. 5 is a simplified example of a multi-drop stub bus memory structure, similar to the one shown in FIG. 3. This structure offers a reasonable tradeoff between cost, performance, reliability and upgrade capability, but has inherent limits on the number of modules that may be attached to the stub bus. The limit on the number of modules that may be attached to the stub bus is directly related to the data rate of the information transferred over the bus. As data rates increase, the number and length of the stubs must be reduced to ensure robust memory operation. Increasing the speed of the bus generally results in a reduction in modules on the bus, with the optimal electrical interface being one in which a single module is directly connected to a single controller, or a point-to-point interface with few, if any, stubs that will result in reflections and impedance discontinuities. As most memory modules are sixty-four or seventy-two bits in data width, this structure also requires a large number of pins to transfer address, command, and data. One hundred and twenty pins are identified in FIG. 5 as being a representative pincount. [0008] FIG. 6, from U.S. Pat. No. 4,723,120 to Petty, of common assignment herewith, is related to the application of a daisy chain structure in a multipoint communication structure that would otherwise require multiple ports, each connected via point-to-point interfaces to separate devices. By adopting a daisy chain structure, the controlling station can be produced with fewer ports (or channels), and each device on the channel can utilize standard upstream and downstream protocols, independent of their location in the daisy chain structure. [0009] FIG. 7 represents a daisy chained memory bus, implemented consistent with the teachings in U.S. Pat. No. 4,723,120. A memory controller 111 is connected to a memory bus 315, which further connects to a module 310a. The information on bus 315 is re-driven by the buffer on module 310a to the next module, 310b, which further re-drives the bus 315 to module positions denoted as 310n. Each module 310a includes a DRAM 311a and a buffer 320a. The bus 315 may be described as having a daisy chain structure, with each bus being point-to-point in nature. [0010] In chip to chip (e.g., controller to module, module to module) communication, it is common place to design receive side circuits and/or logic to aid in the sampling of the incoming data to improve the performance of the interface. Typically the circuitry senses transitions on the incoming data. Based on the position or phase arrival of the data transitions, an algorithm determines the optimum phase of the clock to sample the incoming data. See FIG. 8, where the clock is centered between two consecutive edges of data. The guardbands are used to sense and to equally center the clock within the data transitions. Designers may use a phased loop lock (PLL), a delay locked loop (DLL) or various other closed loop techniques to determine and then to set the optimal phase of the sampling clock. Without transitions on the incoming data, there is no information to sense or to base a relative comparison of the sampling clock to the incoming data. If long periods of time elapse without transitions on data, the sampling clock may drift with changes in temperature or power supply, thus increasing the sampling error and decreasing the performance of the interface. [0011] In order to ensure that there is some minimum transition density within the data, designers often code the data. The 8/10 code is a well known code that encodes an eight bit data stream into ten bits to ensure transitions always exist on data. However, the impact on bandwidth is twenty percent because what would normally take eight bit times to transfer the required information now takes ten bits with the overhead of the coding fniction. An alternative to coding is to periodically interrupt data transfers and to send a known pattern(s). Although the impact on bandwidth may be much smaller than with the coding alternative, this approach also has its drawbacks since the system operation must be halted before the special patterns can be transmitted. BRIEF SUMMARY OF THE INVENTION [0012] Exemplary embodiments of the present invention include a cascaded interconnect system with one or more memory modules, a memory controller and a memory bus. The memory bus utilizes periodic recalibration. The memory modules and the memory controller are directly interconnected by a packetized multi-transfer interface via the memory bus and provide scrambled data for use in the periodic recalibration. [0013] Additional exemplary embodiments include a method for providing periodic recalibration of a memory bus in a cascaded interconnect memory system. The method includes receiving input data at a transmit side, where the transmit side includes a memory controller or a memory module within the memory system. The input data is scrambled at the transmit side, resulting in scrambled data for use in the periodic recalibration of the memory bus. The scrambled data is transmitted to a receive side via the memory bus, where the receive side includes a memory controller or a memory module directly connected to the transmit side by a packetized multi-transfer interface via the memory bus. A sampling clock and a data phase of the scrambled data is periodically synchronized at the receive side for data sampling on the memory bus. The scrambled data is de-scrambled at the receive side, resulting in the original input data. [0014] Further exemplary embodiments include a storage medium with machine readable computer program code for providing periodic bus recalibration of a memory bus in a cascaded interconnect memory subsystem. The storage medium includes instructions for causing a computer to implement a method. The method includes receiving input data at a transmit side, where the transmit side includes a memory controller or a memory module within the memory system. The input data is scrambled at the transmit side, resulting in scrambled data for use in the periodic recalibration of the memory bus. The scrambled data is transmitted to a receive side via the memory bus, where the receive side includes a memory controller or a memory module directly connected to the transmit side by a packetized multi-transfer interface via the memory bus. A sampling clock and a data phase of the scrambled data is periodically synchronized at the receive side for data sampling on the memory bus. The scrambled data is de-scrambled at the receive side, resulting in the original input data. BRIEF DESCRIPTION OF THE DRAWINGS [0015] Referring now to the drawings wherein like elements are numbered alike in the several FIGURES: [0016] FIG. 1 depicts a prior art memory controller connected to two buffered memory assemblies via separate point-to-point links; [0017] FIG. 2 depicts a prior art synchronous memory module with a buffer device; [0018] FIG. 3 depicts a prior art memory subsystem using registered DIMMs; [0019] FIG. 4 depicts a prior art memory subsystem with point-to-point channels, registered DIMMs, and a 2:1 bus speed multiplier; [0020] FIG. 5 depicts a prior art memory structure that utilizes a multidrop memory `stub` bus; Continue reading... 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