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  System for performing data pattern sensitivity compensation using different voltageThe Patent Description & Claims data below is from USPTO Patent Application 20080056001. Brief Patent Description - Full Patent Description - Patent Application Claims
CLAIM OF PRIORITY [0001] This application is a divisional application of U.S. patent application Ser. No. 11/421,884, filed on Jun. 2, 2006, entitled "System For Performing Data Pattern Sensitivity Compensation Using Different Voltage," by Nima Mokhlesi and Yingda Dong, Attorney Docket No. SAND-01103US1, incorporated herein by reference. CROSS-REFERENCE TO RELATED APPLICATIONS [0002] The following applications are cross-referenced and incorporated by reference herein in its entirety: [0003] U.S. Application entitled "System for Performing Data Pattern Sensitivity Compensation Using Different Voltage," by Nima Mokhlesi and Yingda Dong, filed the same day as the present application, Attorney Docket No. SAND-01103US2. [0004] U.S. application Ser. No. 11/421,871, filed on Jun. 2, 2006, entitled "Data Pattern Sensitivity Compensation Using Different Voltage," by Nima Mokhlesi and Yingda Dong, Attorney Docket No. SAND-01103US0. [0005] U.S. Publication No. 20070206426, published on Sep. 6, 2007, U.S. patent application Ser. No. 11/377,972, filed on Mar. 17, 2006, entitled "System for Performing Read Operation On Non-volatile Storage with Compensation for Coupling," by Nima Mokhlesi, Attorney Docket No. SAND-01089US0. [0006] U.S. Publication No. 20070206421, published on Sep. 6, 2007, U.S. patent application Ser. No. 11/384,057, filed on Mar. 17, 2006, entitled "Read Operation for Non-volatile Storage with Compensation for Coupling," by Nima Mokhlesi, Attorney Docket No. SAND-01089US2. [0007] U.S. patent application Ser. No. 11/421,667, filed on Jun. 1, 2006, entitled "Verify Operation For Non-Volatile Storage Using Different Voltages," by Gerrit Jan Hemink, Attorney Docket No. SAND-01084US0. [0008] U.S. patent application Ser. No. 11/421,682, filed on Jun. 1, 2006, entitled "System For Verify Operation For Non-Volatile Storage Using Different Voltages," by Gerrit Jan Hemink, Attorney Docket No. SAND-01084US 1. BACKGROUND OF THE INVENTION [0009] 1. Field of the Invention [0010] The present invention relates to technology for non-volatile memory. [0011] 2. Description of the Related Art [0012] Semiconductor memory has become more popular for use in various electronic devices. For example, non-volatile semiconductor memory is used in cellular telephones, digital cameras, personal digital assistants, mobile computing devices, non-mobile computing devices and other devices. Electrical Erasable Programmable Read Only Memory (EEPROM) and flash memory are among the most popular non-volatile semiconductor memories. [0013] Both EEPROM and flash memory utilize a floating gate that is positioned above and insulated from a channel region in a semiconductor substrate. The floating gate is positioned between the source and drain regions. A control gate is provided over and insulated from the floating gate. The threshold voltage of the transistor is controlled by the amount of charge that is retained on the floating gate. That is, the minimum amount of voltage that must be applied to the control gate before the transistor is turned on to permit conduction between its source and drain is controlled by the level of charge on the floating gate. [0014] One example of a flash memory system uses the NAND structure, which includes arranging multiple transistors in series between two select gates. The transistors in series and the select gates are referred to as a NAND string. [0015] When programming an EEPROM or flash memory device, such as a NAND flash memory device, typically a program voltage is applied to the control gate and the bit line is grounded. Electrons from the channel are injected into the floating gate. When electrons accumulate in the floating gate, the floating gate becomes negatively charged and the threshold voltage of the memory cell is raised so that the memory cell is in a programmed state. More information about programming can be found in U.S. Pat. No. 6,859,397, titled "Source Side Self Boosting Technique for Non-Volatile Memory;" and in U.S. Pat. No. 6,917,542, titled "Detecting Over Programmed Memory;" both patents are incorporated herein by reference in their entirety. [0016] Some EEPROM and flash memory devices have a floating gate that is used to store two ranges of charges and, therefore, the memory cell can be programmed/erased between two states (an erased state and a programmed state). Such a flash memory device is sometimes referred to as a binary flash memory device. [0017] A multi-state flash memory device is implemented by identifying multiple distinct allowed/valid programmed threshold voltage ranges separated by forbidden ranges. Each distinct threshold voltage range corresponds to a predetermined value for the set of data bits encoded in the memory device. [0018] Errors can occur when reading non-volatile storage element due to at least two mechanisms: (1) capacitive coupling between neighboring floating gates and (2) changing conductivity of the channel area after programming (referred to as back pattern effect). Both of these issues are discussed below. [0019] Shifts in the apparent charge stored on a floating gate can occur because of the coupling of an electric field based on the charge stored in adjacent floating gates. This floating gate to floating gate coupling phenomena is described in U.S. Pat. No. 5,867,429, which is incorporated herein by reference in its entirety. An adjacent floating gate to a target floating gate may include neighboring floating gates that are on the same bit line, neighboring floating gates on the same word line, or floating gates that are diagonal from the target floating gate because they are on both a neighboring bit line and neighboring word line. [0020] The floating gate to floating gate coupling phenomena occurs most pronouncedly between sets of adjacent memory cells that have been programmed at different times. For example, a first memory cell is programmed to add a level of charge to its floating gate that corresponds to one set of data. Subsequently, one or more adjacent memory cells are programmed to add a level of charge to their floating gates that correspond to a second set of data. After the one or more of the adjacent memory cells are programmed, the charge level read from the first memory cell appears to be different than programmed because of the effect of the charge on the adjacent memory cells being coupled to the first memory cell. The coupling from adjacent memory cells can shift the apparent charge level being read a sufficient amount to lead to an erroneous reading of the data stored. [0021] The effect of the floating gate to floating gate coupling is of greater concern for multi-state devices because in multi-state devices the allowed threshold voltage ranges and the forbidden ranges are narrower than in binary devices. Therefore, the floating gate to floating gate coupling can result in memory cells being shifted from an allowed threshold voltage range to a forbidden range. Continue reading... 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