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  System and method for stopping functional macro clocks to aid in debuggingUSPTO Application #: 20080010621Title: System and method for stopping functional macro clocks to aid in debugging Abstract: A system and method for debugging an integrated circuit. According to a preferred embodiment of the present invention, the integrated circuit includes a collection of macros. Each macro further includes a collection of latches controlled by a local clock control. A pattern matcher monitors data patterns in at least one macro. In response to detecting a data pattern indicative of a failure signature within the at least one macro, a check stop logic sends an error detection signal to at least one additional macro and to the local clock control. In response to receiving the error detection signal, the local clock control halts operation with the at least one macro such that data values contributing to said data pattern indicative of said failure signature are retained in the collection of latches. (end of abstract) Agent: Dillon & Yudell LLP - Austin, TX, US Inventor: Derek E. Williams USPTO Applicaton #: 20080010621 - Class: 716 4 (USPTO) The Patent Description & Claims data below is from USPTO Patent Application 20080010621. Brief Patent Description - Full Patent Description - Patent Application Claims
BACKGROUND OF THE INVENTION [0001]1. Technical Field [0002]The present invention relates in general to the field of data processing systems. More specifically, the present invention relates to a system and method for stopping functional macro clocks to aid in debugging. [0003]2. Description of the Related Art [0004]Modern computer systems include a large number of integrated circuits. The integrated circuits generally include multiple macros, which each include a collection of integrated circuit elements utilized to perform a discrete function in the integrated circuit. [0005]Frequently, when debugging an integrated circuit, a circuit tester would like to view the latch data values in one or more macros at the time of an error. As well-known by those skilled in the art, often when a particular macro encounters an error, the particular macro sends an error detection signal to a master macro signifying error detection. The master macro, upon receiving the error detection signal from the particular macro, sends a stop signal that halts the functional clock of all macros in the integrated circuit. This allows the values of the latches in the integrated circuit to then be "scanned out" for examination. By the time the particular macro stops operating in response to the stop signal, the data values present in the macro at the time of the error are often lost because the functional clock was halted not at the time the error was detected, but many clock cycles later in response to the master macro's stop signal. Therefore, there is a need for a system and method for addressing the aforementioned limitations of the prior art. SUMMARY OF THE INVENTION [0006]The present invention includes a system and method for debugging an integrated circuit. According to a preferred embodiment of the present invention, the integrated circuit includes a collection of macros. A reliability and serviceability (RAS) macro controls a clock source, scans the contents of the collection of macros via scan chains, and stops operations within the macros by sending out a global clock stop signal in response to receiving an error detection signal sent by any of the macros within the integrated circuit. [0007]Each macro may further include a collection of latches controlled by a local clock control. A pattern matcher monitors data patterns in a current macro. In response to detecting a data pattern indicative of a failure signature within the current macro, a check stop logic sends an error detection signal to the RAS macro and possibly to one or more neighboring macros. The local clock control in the current macro immediately halts operation within the current macro such that the data values that contributed to the data pattern indicated of a failure signature are more likely retained in the collection of latches. In response to receiving the error detection signal from the current macro, the neighboring macro(s) (if enabled) will also immediately stop operations to preserve values in the neighboring macro(s). The RAS macro, upon receiving the error detection signal from the current macro, sends a global clock stop signal to all macros within the integrated circuit. After all macros have been stopped, the latch values within the macro may be scanned out for examination. [0008]The aforementioned features, as well as additional objectives, features, and advantages of the present invention will become apparent in the following detailed description. BRIEF DESCRIPTION OF THE FIGURES [0009]The novel features believed characteristic of the invention are set forth in the appended claims. The invention itself, however, as well as a preferred mode of use, further objects and advantages thereof, will best be understood by reference to the following detailed description of an illustrative embodiment when read in conjunction with the accompanying figures, wherein: [0010]FIG. 1 is a block diagram illustrating an exemplary data processing system in which a preferred embodiment of the present invention may be implemented; [0011]FIG. 2 is a block diagram depicting an exemplary integrated circuit in which a preferred embodiment of the present invention may be implemented; [0012]FIG. 3 is a more detailed block diagram illustrating an exemplary macro as shown in FIG. 2; [0013]FIG. 4 is a more detailed block diagram depicting an exemplary check stop logic as illustrated in FIG. 3; [0014]FIG. 5 is a high-level logical flowchart illustrating an exemplary method for stopping functional macro clocks to aid in debugging in accordance with a preferred embodiment of the present invention. DETAILED DESCRIPTION OF AN ILLUSTRATIVE EMBODIMENT [0015]The present invention includes an integrated circuit that is implemented as a reliability and serviceability (RAS) macro, a collection of macros, and a clock source. Utilizing check stop logic, each macro, including the RAS macro monitors activity within the macros to detect internal data patterns that are indicative of a failure signature (e.g., illegal value). In response to detecting internal data patterns that are indicative of a failure signature within a first macro, the check stop logic sends an error detection signal to a local clock control, any neighboring macros that have elected to receive failure detection signals from the first macro, and to the RAS macro. While the local clock control halts operation of the first macro, any neighboring macros are also halted, if requested, thus more likely preserving the values that generated the illegal value, instead of halting the first macro upon receiving a global clock stop signal from the RAS macro. [0016]With reference now to the figures, and in particular, with reference to FIG. 1, there is depicted an exemplary data processing system 6 in which a preferred embodiment of the present invention may be implemented. The depicted embodiment can be realized, for example, as a workstation, server, or mainframe computer. [0017]As illustrated, data processing system 6 includes one or more processing nodes 8a-8n, which, if more than one processing node 8 is implemented, are interconnected by node interconnect 22. Processing nodes 8a-8n may each include one or more processors 10, a local interconnect 16, and a system memory 18 that is accessed via a memory controller 17. Processors 10a-10m are preferably (but not necessarily) identical and may comprise a processor within the PowerPC.TM. line of processors available from International Business Machines (IBM) Corporation of Armonk, N.Y. In addition to the registers, instruction flow logic and execution units utilized to execute program instructions, which are generally designated as processor core 12, each of processors 10a-10m also includes an on-chip cache hierarchy 14 that is utilized to stage data to the associated processor core 12 from system memories 18. [0018]Each of processing nodes 8a-8n further includes a respective node controller 20 coupled between local interconnect 16 and node interconnect 22. Each node controller 20 serves as a local agent for remote processing nodes 8 by performing at least two functions. First, each node controller 20 snoops the associated local interconnect 16 and facilitates the transmission of local communication transactions to remote processing nodes 8. Second, each node controller 20 snoops communication transactions on node interconnect 22 and masters relevant communication transactions on the associated local interconnect 16. Communication on each local interconnect 16 is controlled by an arbiter 24. Arbiters 24 regulate access to local interconnects 16 based on bus request signals generated by processors 10 and compile coherency responses for snooped communication transactions on local interconnects 16. [0019]Local interconnect 16 is coupled, via mezzanine bus bridge 26, to a mezzanine bus 30. Mezzanine bus bridge 26 provides both a low latency path through which processors 10 may directly access devices among I/O devices 32 and storage devices 34 that are mapped to bus memory and/or I/O address spaces and a high bandwidth path through which I/O devices 32 and storage devices 34 may access system memory 18. I/O devices 32 may include, for example, a display device, a keyboard, a graphical pointer, and serial and parallel ports for connection to external networks or attached devices. Storage devices 34 may include, for example, optical or magnetic disks that provide non-volatile storage for operating system, middleware and application software. [0020]FIG. 2 is a block diagram illustrating an exemplary integrated circuit 200, such as processor 10 within data processing system 6 of FIG. 1. Integrated circuit 200 is preferably implemented as a semiconductor or insulating substrate with integrated circuitry, implemented in various functional blocks referred to herein as reliability and serviceability (RAS) macro 204, macros 205a-205n, and clock source 232. Clock source 232 supplies a clock signal to all the macros 205a-205n and RAS macro 204 and is controlled by RAS macro 204. Continue reading... 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