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  System and method for reducing command scheduling constraints of memory circuitsUSPTO Application #: 20080109595Title: System and method for reducing command scheduling constraints of memory circuits Abstract: A memory circuit system and method are provided. An interface circuit is capable of communication with a plurality of memory circuits and a system. In use, the interface circuit is operable to interface the memory circuits and the system for reducing command scheduling constraints of the memory circuits. (end of abstract) Agent: Zilka-kotab, Pc- Mrm1 - San Jose, CA, US Inventors: Suresh Natarajan Rajan, Keith R. Schakel, Michael John Sebastian Smith, David T. Wang, Frederick Daniel Weber USPTO Applicaton #: 20080109595 - Class: 711105000 (USPTO) Related Patent Categories: Electrical Computers And Digital Processing Systems: Memory, Storage Accessing And Control, Specific Memory Composition, Solid-state Random Access Memory (ram), Dynamic Random Access Memory The Patent Description & Claims data below is from USPTO Patent Application 20080109595. Brief Patent Description - Full Patent Description - Patent Application Claims
RELATED APPLICATION(S) [0001] The application is a continuation of U.S. application Ser. No.: 11/672,921 filed Feb. 08, 2007, which, in turn, is a continuation-in-part of U.S. application Ser. No.: 11/461,437 filed Jul. 31, 2006, U.S. application Ser. No.: 11/702,960 filed Feb. 05, 2007, and U.S. application Ser. No.: 11/702,981 filed Feb. 05, 2007; and further claims priority to U.S. provisional application Ser. No.: 60/772,414 filed Feb. 09, 2006 and U.S. provisional application Ser. No.: 60/865,624 filed Nov. 13, 2006, which are each incorporated herein by reference in their entirety for all purposes. FIELD OF THE INVENTION [0002] The present invention relates to memory, and more particularly to command scheduling constraints of memory circuits. BACKGROUND [0003] Traditionally, memory circuit speeds have remained constant, while the required data transfer speeds and bandwidth of memory systems have steadily increased. Thus, it has been necessary for more commands be scheduled, issued, and pipelined in a memory system in order to increase bandwidth. However, command scheduling constraints have customarily existed in memory systems which limit the command issue rates, and thus limit various attempts to further increase bandwidth, etc. There is thus a need for addressing these and/or other issues associated with the prior art. SUMMARY [0004] A memory circuit system and method are provided. An interface circuit is capable of communication with a plurality of memory circuits and a system. In use, the interface circuit is operable to interface the memory circuits and the system for reducing command scheduling constraints of the memory circuits. BRIEF DESCRIPTION OF THE DRAWINGS [0005] FIG. 1 illustrates a system for interfacing memory circuits, in accordance with one embodiment. [0006] FIG. 2 illustrates a method for reducing command scheduling constraints of memory circuits, in accordance with another embodiment. [0007] FIG. 3 illustrates a method for translating an address associated with a command communicated between a system and memory circuits, in accordance with yet another embodiment. [0008] FIG. 4 illustrates a block diagram including logical components of a computer platform, in accordance with another embodiment. [0009] FIG. 5 illustrates a timing diagram showing an intra-device command sequence, intra-device timing constraints, and resulting idle cycles that prevent full use of bandwidth utilization in a DDR3 SDRAM memory system, in accordance with yet another embodiment. [0010] FIG. 6 illustrates a timing diagram showing an inter-device command sequence, inter-device timing constraints, and resulting idle cycles that prevent full use of bandwidth utilization in a DDR SDRAM, DDR2 SDRAM, or DDR3 SDRAM memory system, in accordance with still yet another embodiment. [0011] FIG. 7 illustrates a block diagram showing an array of DRAM devices connected to a memory controller, in accordance with another embodiment. [0012] FIG. 8 illustrates a block diagram showing an interface circuit disposed between an array of DRAM devices and a memory controller, in accordance with yet another embodiment. [0013] FIG. 9 illustrates a block diagram showing a DDR3 SDRAM interface circuit disposed between an array of DRAM devices and a memory controller, in accordance with another embodiment. [0014] FIG. 10 illustrates a block diagram showing a burst-merging interface circuit connected to multiple DRAM devices with multiple independent data buses, in accordance with still yet another embodiment. [0015] FIG. 11 illustrates a timing diagram showing continuous data transfer over multiple commands in a command sequence, in accordance with another embodiment. [0016] FIG. 12 illustrates a block diagram showing a protocol translation and interface circuit connected to multiple DRAM devices with multiple independent data buses, in accordance with yet another embodiment. [0017] FIG. 13 illustrates a timing diagram showing the effect when a memory controller issues a column-access command late, in accordance with another embodiment. [0018] FIG. 14 illustrates a timing diagram showing the effect when a memory controller issues a column-access command early, in accordance with still yet another embodiment. [0019] FIG. 15 illustrates a representative hardware environment, in accordance with one embodiment. Continue reading... Full patent description for System and method for reducing command scheduling constraints of memory circuits Brief Patent Description - Full Patent Description - Patent Application Claims Click on the above for other options relating to this System and method for reducing command scheduling constraints of memory circuits patent application. ###  How KEYWORD MONITOR works... a FREE service from FreshPatents1. Sign up (takes 30 seconds). 2. Fill in the keywords to be monitored. 3. Each week you receive an email with patent applications related to your keywords. Start now! - Receive info on patent apps like System and method for reducing command scheduling constraints of memory circuits or other areas of interest. ### Previous Patent Application: Non-volatile memory device controlled by a micro-controller Next Patent Application: System having a controller device, a buffer device and a plurality of memory devices Industry Class: Electrical computers and digital processing systems: memory ### FreshPatents.com Support Thank you for viewing the System and method for reducing command scheduling constraints of memory circuits patent info. IP-related news and info Results in 2.38839 seconds Other interesting Feshpatents.com categories: Medical: Surgery , Surgery(2) , Surgery(3) , Drug , Drug(2) , Prosthesis , Dentistry |
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