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System and method for memory element characterization

System and method for memory element characterization description/claims

This application is a Divisional application of allowed U.S. patent application Ser. No. 11/142,709 filed on Jun. 1, 2005, pending.

1. Technical Field

The present invention relates to circuit design and more particularly to a system and method for memory element characterization in latch-type circuits.

2. Description of the Related Art

Latch-type circuits are employed in many electronic applications. The design of a latch circuit is an important aspect of the circuit's performance. The characterization of latch-type circuits is particularly tedious, however.

Latch characterization is typically based on circuit simulation experiments, mainly using transient analysis. In contrast to other characterization targets for library elements, e.g., propagation delay, there are no simulation experiments that can directly determine the set-up or hold-time of a latch.

Instead, a sequence of simulations with varying time delays between clock and data transition events are typically performed, essentially, in a search procedure for the situation when the settling time of the internal latch starts degrading. As a consequence, the characterization of the latch library elements becomes a very costly and disproportionately large portion of the total characterization effort.

A system and method for analyzing a memory element includes modeling the memory element using a simulation method and determining component response characteristics for components of the memory element. Safety regions are computed in a state space of the memory element, which indicate stable states. A transient analysis is performed to determine a path and time needed to reach one of the safety regions. Based on the path and time needed to reach one of the safety regions, a clock waveform or waveforms are determined which place a corresponding state in that safety region.

A latch design system includes a modeling module configured to model a latch using a simulation method. A simulation module is configured to determine component response characteristics for components of the latch and compute safety regions in a state space of the latch. The safety regions indicate stable states for the latch. A transient analysis module is configured to determine transient responses for the latch in an open state to geometrically determine a path and time needed to reach one of the safety regions. The path and the time are employed to determine a clock waveform for placing a corresponding state in the one of the safety regions.

These and other objects, features and advantages will become apparent from the following detailed description of illustrative embodiments thereof, which is to be read in connection with the accompanying drawings.

The disclosure will provide details in the following description of preferred embodiments with reference to the following figures wherein:

FIG. 1 is a block/flow diagram showing an illustrative system/method for avoiding metastable states by determining characteristics including set-up and hold times for a latch or memory circuit in accordance with one exemplary embodiment;

FIG. 2 is a schematic diagram of a latch circuit and response plots for given components on which an analysis is performed in accordance with an embodiment of the present invention;

FIG. 3 is a timing diagram of the latch circuit of FIG. 2 showing data and clock signals for an open state for latching data in the latch in accordance with an embodiment of the present invention;

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