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  System and method for hiding memory latencyUSPTO Application #: 20060080661Title: System and method for hiding memory latency Abstract: A System and method for hiding memory latency in a multi-thread environment is presented. Branch Indirect and Set Link (BISL) and/or Branch Indirect and Set Link if External Data (BISLED) instructions are placed in thread code during compilation at instances that correspond to a prolonged instruction. A prolonged instruction is an instruction that instigates latency in a computer system, such as a DMA instruction. When a first thread encounters a BISL or a BISLED instruction, the first thread passes control to a second thread while the first thread's prolonged instruction executes. In turn, the computer system masks the latency of the first thread's prolonged instruction. The system can be optimized based on the memory latency by creating more threads and further dividing a register pool amongst the threads to further hide memory latency in operations that are highly memory bound. (end of abstract)
Agent: Ibm Corporation- Austin (jvl) C/o Van Leeuwen & Van Leeuwen - Austin, TX, US Inventors: Daniel Alan Brokenshire, Harm Peter Hofstee, Barry L. Minor, Mark Richard Nutter USPTO Applicaton #: 20060080661 - Class: 718100000 (USPTO) Related Patent Categories: Electrical Computers And Digital Processing Systems: Virtual Machine Task Or Process Management Or Task Management/control, Task Management Or Control The Patent Description & Claims data below is from USPTO Patent Application 20060080661. Brief Patent Description - Full Patent Description - Patent Application Claims
BACKGROUND OF THE INVENTION [0001] 1. Technical Field [0002] The present invention relates in general to a system and method for hiding memory latency. More particularly, the present invention relates to a system and method for, in a multi-thread environment, passing control from a first thread to a second thread when the first thread encounters a prolonged instruction. [0003] 2. Description of the Related Art [0004] Developers attempt to increase a computer system's performance by improving both the hardware aspects and the software aspects of the computer system. From a hardware perspective, a hardware developer may focus on improving areas such as a microprocessor's speed, bus interface speed, and memory size. From a software perspective, a developer may design an application to invoke multiple threads in order to increase the application's performance. For example, a gaming application may invoke a thread to render terrain data for the left half of a computer screen, and invoke a second thread to render terrain data for the right half of the computer screen. Each thread is given "control" at particular times and it is during these control times that a thread executes instructions. [0005] In addition, a software developer may increase software performance by minimizing code latency. Code latency occurs when one line of code is waiting on another line of code to finish executing. There are instructions, however, that take a prolonged amount of time to execute. These "prolonged instructions" typically include operations that retrieve data from a memory area, such as a Direct Memory Access (DMA) operation. A challenge found with prolonged instructions is removing the latency that results when an application waits for the prolonged instruction to finish. [0006] A further challenge is found when an application invokes multiple threads and one of the threads encounters a prolonged instruction. Because the thread that encountered the prolonged instruction has control, the other threads sit idle. [0007] What is needed, therefore, is a system and method to hide a prolonged instruction's code latency in a multi-thread environment. SUMMARY [0008] It has been discovered that the aforementioned challenges are resolved by passing control to a second thread while a first thread processes a prolonged instruction using branch instructions. At compile time, Branch Indirect and Set Link (BISL) and/or Branch Indirect and Set Link if External Data (BISLED) instructions are placed in thread code at instances that correspond to a thread's prolonged instruction. A prolonged instruction is an instruction that may instigate latency in a computer system, such as a DMA instruction. When a first thread encounters a BISL or a BISLED instruction, the first thread passes control to a second thread while the first thread's prolonged instruction executes, thereby masking the latency of the first thread's prolonged instruction. [0009] A computer application includes a first thread and a second thread. The first thread begins execution and encounters a prolonged instruction, such as a DMA instruction. The first thread's next instruction is either a BISL or a BISLED instruction. A BISLED instruction modifies a link register of a second thread such that when control is passed back to the first thread, the first thread checks as to whether the prolonged instruction is complete. If the prolonged instruction is not complete, the first thread continues to pass control away to the second thread until the prolonged instruction is complete. A BISL instruction modifies a link register of a second thread such that when control is passed back to the first thread, the first thread maintains control and waits for the prolonged instruction to complete. [0010] When the first thread encounters a BISL or a BISLED instruction, the first thread determines that its prolonged instruction is still being processed, and initiates steps to branch to a second thread. The first thread stores its return address in a first register, whereby the first thread's return address corresponds to an address at which to return when control is passed back to the first thread. If the branch instruction is a BISL instruction, the first thread's return address corresponds to the instruction after the BISL instruction. If the return address is a BISLED instruction, the first thread's return address corresponds to the BISLED instruction such that when control is passed back to the first thread, the prolonged instruction condition is checked once again. The first thread retrieves the second thread's return address from a second register and passes control to the second thread. [0011] The second thread receives control, and begins to execute its instructions. The second thread encounters a prolonged instruction and begins to execute the prolonged instruction. The second thread identifies that its next instruction is either a BISL or a BISLED instruction. As such, the second thread stores the second thread's return address in the second register, and retrieves the first thread's return address from the first register. The second thread passes control to the first thread at the first thread's return address, whereby the first thread executes its instructions. This cyclical loop continues between the first thread and the second thread in order to hide memory latency that both threads encounter when they perform a prolonged instruction. [0012] BISL and BISLED instructions may be inserted into a software program either manually or automatically. For example, when a developer is writing a program in machine code, the developer may manually insert BISL and BISLED instructions after prolonged instructions. In another example, when a developer is writing a program in a high-level programming language, a compiler may automatically insert BISL and BISLED instructions for particular co-routines. [0013] The foregoing is a summary and thus contains, by necessity, simplifications, generalizations, and omissions of detail; consequently, those skilled in the art will appreciate that the summary is illustrative only and is not intended to be in any way limiting. Other aspects, inventive features, and advantages of the present invention, as defined solely by the claims, will become apparent in the non-limiting detailed description set forth below. BRIEF DESCRIPTION OF THE DRAWINGS [0014] The present invention may be better understood, and its numerous objects, features, and advantages made apparent to those skilled in the art by referencing the accompanying drawings. The use of the same reference symbols in different drawings indicates similar or identical items. [0015] FIG. 1 is a diagram showing two threads branching to each other when the threads encounter a prolonged instruction; [0016] FIG. 2A is a diagram showing two threads that include a branch indirect and set link instruction (BISL); [0017] FIG. 2B is a diagram showing two threads that include a branch indirect and set link if external data instruction (BISLED); [0018] FIG. 3 is flowchart showing steps taken in compiling threads and assigning registers to the threads that include branch instructions; [0019] FIG. 4 is a flowchart showing steps taken in two threads branching to each other when the threads encounter a prolonged instruction; [0020] FIG. 5 is a diagram showing a processor element architecture that includes a plurality of heterogeneous processors; [0021] FIG. 6A illustrates a first information handling system which is a simplified example of a computer system capable of performing the computing operations described herein; Continue reading... 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