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  System and method for executing instructions utilizing a preferred slot alignment mechanismUSPTO Application #: 20070186077Title: System and method for executing instructions utilizing a preferred slot alignment mechanism Abstract: A system and method for executing instructions utilizing a preferred slot alignment mechanism is presented. A processor architecture uses a vector register file, a shared data path, and instruction execution logic to process both single instruction multiple data (SIMD) instruction and scalar instructions. The processor architecture divides a vector into four “slots,” each including four bytes, and locates scalar data in “preferred slots” to ensure proper positioning. Instructions using the preferred slot mechanism include 1) shift and rotate instructions operating across an entire quad-word that specify a shift amount, 2) memory load and store instructions that require an address, and 3) branch instructions that use the preferred slot for branch conditions (conditional branches) and branch addresses (register-indirect branches). As a result, the processor architecture eliminates the requirement for separate issue slots, separate pipelines, and the control complexity for separate scalar units. (end of abstract) Agent: Ibm Corporation- Austin (jvl) C/o Van Leeuwen & Van Leeuwen - Austin, TX, US Inventors: Michael Karl Gschwind, Harm Peter Hofstee, Martin E. Hopkins, James Allan Kahle USPTO Applicaton #: 20070186077 - Class: 712003000 (USPTO) Related Patent Categories: Electrical Computers And Digital Processing Systems: Processing Architectures And Instruction Processing (e.g., Processors), Processing Architecture, Vector Processor, Scalar/vector Processor Interface The Patent Description & Claims data below is from USPTO Patent Application 20070186077. Brief Patent Description - Full Patent Description - Patent Application Claims
RELATED APPLICATIONS [0001] This application is a Continuation in Part (CIP) of U.S. Patent Application US 2002/0138637 A1, Ser. No. 09/816,004, filed on Mar. 22, 2001 titled "Computer Architecture and Software Cells for Broadband Networks," and has at least one of the same inventors as the above referenced U.S. Patent Application. BACKGROUND OF THE INVENTION [0002] 1. Technical Field [0003] The present invention relates to a system and method for executing instructions utilizing a preferred slot alignment mechanism. More particularly, the present invention relates to a processor architecture that includes a vector register file, a shared data path, and instruction execution logic to process source operands that correspond to both Single Instruction Multiple Data (SIMD) computations and scalar computations. [0004] 2. Description of the Related Art [0005] A continuing importance of gaming applications and other numerically intensive workloads has generated an upsurge in novel computer architectures tailored for such functionality. Gaming applications feature highly parallel code for functions such as game physics, which have high computation and memory requirements. Gaming applications also include scalar code for functions such as game artificial intelligence that require fast response times and a full-featured programming environment. [0006] A challenge found with these computer architectures is that they have overly complex designs, which results in area and power inefficiencies. For example, the computer architectures implement both Single Instruction Multiple Data (SIMD) execution units as well as scalar execution units. As a result, they include duplication logic for instruction decoding, instruction issue, register dependence tracking and resolution, register files, execution resources, and instruction commit. [0007] What is needed, therefore, is a system and method that provides a power-efficient, area-efficient, low-complexity, and high performance computer architecture. SUMMARY [0008] It has been discovered that the aforementioned challenges are resolved using a processor architecture that uses a vector register file, a shared data path, and instruction execution logic to process source operands that correspond to both Single Instruction Multiple Data (SIMD) computations and scalar computations. The processor architecture divides a vector into four "slots," each including four bytes, and locates scalar data items in "preferred slots" to ensure proper positioning. As a result, the processor architecture eliminates a requirement for separate issue slots, separate pipelines, and the control complexity for separate scalar units. [0009] A local storage area includes instructions that are fed into a buffer in 128-byte increments, which supplies the instructions to a fetch unit in 64 byte increments (representing a first and second half of a memory line). In turn, the instructions proceed through a shared datapath that includes instruction line buffers, issue/branch units, and a vector register file. The vector register file provides operands in data widths of 16 bytes, regardless of whether the instruction corresponds to a scalar computation or SIMD computation, to an appropriate execution unit for further processing, such as a vector floating point unit, a vector fixed point unit, a data formatting and permute unit, and a load/store unit. [0010] In order to process the scalar instructions correctly, scalar data items are aligned using a "preferred slot" mechanism with respect to a vector word. Instructions using the preferred slot mechanism include 1) shift and rotate instructions operating across an entire quad-word that specify a shift amount, 2) memory load and store instructions that require an address, and 3) branch instructions that use the preferred slot for branch conditions (conditional branches) and branch addresses (register-indirect branches). Branch and link instructions also use the preferred slot mechanism to deposit a function return address in a return address register. [0011] In one embodiment, the preferred slot is four bytes in length and starts at the leftmost word element slot that includes byte locations 0 through 3. As such, when a scalar data item is only one byte in length the byte resides in byte location 3. When a scalar data item is a half-word in length, the half-word resides in byte locations 2-3. When a vector includes a 32-bit address, the address resides in byte locations 0-3. When a scalar data item is one word in length, the word resides in byte locations 0-3. When a scalar data item is two words in length, the double word resides in byte locations 0-7. And, when a scalar data item is four words in length, the quad word resides in byte locations 0-15. [0012] The foregoing is a summary and thus contains, by necessity, simplifications, generalizations, and omissions of detail; consequently, those skilled in the art will appreciate that the summary is illustrative only and is not intended to be in any way limiting. BRIEF DESCRIPTION OF THE DRAWINGS [0013] The present invention may be better understood, and its numerous objects, features, and advantages made apparent to those skilled in the art by referencing the accompanying drawings. [0014] FIG. 1 illustrates the overall architecture of a computer network; [0015] FIG. 2 is a diagram illustrating the structure of a processor element (PE); [0016] FIG. 3 is a diagram illustrating the structure of a broadband engine (BE); [0017] FIG. 4 is a diagram illustrating the structure of an attached processing unit (APU); [0018] FIG. 5 is a diagram illustrating the structure of a processor element, visualizer (VS) and an optical interface; [0019] FIG. 6 is a diagram illustrating one combination of processor elements; [0020] FIG. 7 illustrates another combination of processor elements; Continue reading... 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