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System and method for determining probing locations on icRelated Patent Categories: Data Processing: Measuring, Calibrating, Or Testing, Testing System, Of CircuitSystem and method for determining probing locations on ic description/claimsThe Patent Description & Claims data below is from USPTO Patent Application 20070179731, System and method for determining probing locations on ic. Brief Patent Description - Full Patent Description - Patent Application Claims
CROSS-REFERENCE TO RELATED APPLICATIONS [0001] This application claims priority from, and is a continuation in part of U.S. application Ser. No. 11/345,004, filed Jan. 31, 2006 and commonly assigned to the current assignee, and which is incorporated herein by reference in its entirety. This case also claims priority from U.S. application Ser. No. 60/774,991, filed Feb. 17, 2006, which is incorporated herein by reference in its entirety. BACKGROUND [0002] 1. Field of the Invention [0003] The present invention relates to an apparatus and method for finding exact locations for probing integrated circuits, and conversely tracing the circuit element and location of a suspected spot on a DUT (device under test) probed by a probing tool. [0004] 2. Description of the Related Art [0005] Probing systems have been used in the art for testing and debugging integrated circuit (IC) designs and layouts. Various laser-based systems for probing IC's are known in the prior art. In these prior art systems, the DUT is driven by an electrical test signal, while a laser beam is used to illuminate the DUT. The laser beam then reflects from the DUT, and the reflection is perturbed according to the DUT's response to the electrical test signals. The reflected beam is then converted to an electrical signal having a waveform corresponding to the reflected beam. This waveform is displayed for the user's analysis. [0006] Some of the test and debug technique used in the prior art include LIVA (Light Induced Voltage Alteration), TIVA (Thermally Induced Voltage Alteration), CIVA (Charge Induced Voltage Alteration), XIVA (Externally Induced Voltage Alteration), OBIC (Optical Beam Induced Current), OBHIC (Optical Beam Heat Induced Current), and OBIRCH (Optical Beam Induced Resistance Change). These techniques probe the DUT to detect a change in the characteristics of certain devices or structures therein to thereby detect a failure or an area that is prone to fail or adversely affect the DUT's performance. According to these techniques, the DUT is driven by an electrical signal, while a laser beam is used to illuminate the DUT to thereby cause either heating, carrier generation, or both. As a result, the electrical output from the DUT is perturbed, and this perturbation is detected and analyzed. That is, under these techniques the laser beam is used only as a perturbing agent, but the detection is done by analyzing the electrical output from the DUT. [0007] Other probing techniques are based on the observation that active devices, such as transistors, emit light upon switching of state. In these systems, the DUT is also energized by test vectors, but no light is used to illuminate the DUT. Rather, an optical system is used to collect the faint light that is emitted upon the switching of the transistor being probed. This techniques is generally referred to in the industry as time-resolved emission (TRE) or time-resolved photon emission (TRPE). A system for performing TRPE probing is commercially available under the trade name EmiScope.TM. from Credence Systems Corporation of Milpitas, California. [0008] As is known in the art, in order to probe the DUT and obtain meaningful analysis, the location of the probed devices must be specified as accurately as possible. This is especially true for TRPE, as the location from which emission emanates is very small, so that accurate placement of the collection optics is imperative for proper emission collection and proper identification of the device that emits the photons. [0009] FIG. 1A is a schematic of prior art method of identifying probing locations on a DUT. In order to test a DUT, first test patterns (also referred to as test vectors) are generated by an automatic test pattern generator, ATPG 105. The test patterns are then fed to the automated testing equipment (also referred to as automated testing and evaluation) ATE 110. The ATE feeds the test vectors to the DUT, 145, and tests the electrical response of the DUT to the test patterns. The ATE then generates a log of fail results, 115, identifying scan chains and test patterns having failures. The log, 115, is then input to an analysis tool, 120, which performs fault simulation using the log so as to determine potential cells or pins that may be faulty. As is shown by the broken-line double arrow, some commercially available ATPG's contain mechanism to also perform the analysis, so while two separate tools are shown, the generation of test vectors and the analysis of the fail log can be done by the same tool. The analysis tool performs fault simulation to determine potential causes for the fault and then outputs a callout log, 125, which lists all of the cell names and related pins that are likely to result in detection of failures. [0010] The cells and pins identified in the callout list may not be the actual cause of the failures. Therefore, it is a practice in the art to use a debug tester, such as a TRPE tool to investigate the actual cause for the fault. For that purpose, the callout log is used to determine which locations to probe with the TRPE tool. That is, using the callout list a debug engineer needs to perform various manual procedures, 150, to determine where to place the prober. The manual procedure involve reviewing various design databases, 130, reviewing the layout vs. schematic, LVS 135, and reviewing layout designs, 140, so as to provide the results, 160, normally in terms of the coordinates of the corner of the cell to be probed. [0011] As can be understood, the methods used in the prior art to arrive at probing locations are tedious and time consuming. Additionally, in most instances only the coordinates of the corner of the cell to be investigated is obtained, and the prober needs to be scanned over the cell to find the actual proper location for probing. Therefore, there is a need in the art for an automated system that provides more detailed information regarding the locations to be probed. [0012] Conversely, in cases where a fault location is detected by the prober, it is currently difficult to determine the corresponding circuit element that is probed. That is, the prober provides only the coordinates of the probing location with respect to the DUT. However, the prober provides no information with respect to layout or circuit design of the DUT, so that the circuit element that emits the light is not readily identifiable. FIG. 1B depicts a general process of the prior art for determining the circuit element that may be responsible for the emission spot. As shown, the location, 100, in terms of X,Y CAD coordinates on the DUT is obtained from the prober. The engineers go manually through various databases, such as design databases 130, layout vs. schematics database 135, and layout tools 140, to determine the candidate elements, 160, that may be the cause. Therefore, there is a need in the industry to provide a system and method to trace back a coordinate location of a probing location to a circuit element in the DUT layout and design. SUMMARY [0013] Various embodiments of the present invention provide apparatus and method for determining the proper locations for probing of a DUT. Other embodiments of the present invention provide apparatus and method for determining the proper locations for probing of a DUT and automatically controlling a stage so that the testing equipment is aligned to the proper location. Yet other embodiments of the present invention provide apparatus and method for tracing back a probing location to identify the circuit element being probed. [0014] According to an aspect of the invention, a method for identifying an area of the chip to be probed proceeds as follows. A callout list of failures is obtained from a tester, the callout list including cell name and pin for each failure. A Def file is interrogated to locate a Def entry matching the cell name, and a cell type, cell location, and cell orientation data is obtained for the cell name from the Def file. A Lef file is then interrogated to locate a Lef entry matching the cell type, and the coordinates of the pin are obtaining from the Lef file. A GDS file is then interrogated to locate a GDS entry matching the cell type, and the coordinates of polygons listed in the GDS entry are obtained. The coordinates of the pin are then crossed with the coordinates of the polygons to identify overlapping area. The overlapping area is defined as the location to be probed. [0015] According to another aspect of the invention, a method for identifying an area of the chip to be probed proceeds as follows. A callout list of failures is obtained from a tester, the callout list including cell name and pin for each failure. A Def file is interrogated to locate a Def entry matching the cell name, and a cell type, cell location, and cell orientation data is obtained for the cell name from the Def file. A Lef file is then interrogated to locate a Lef entry matching the cell type, and the coordinates of the pin are obtaining from the Lef file. A GDS file is then interrogated to locate a GDS entry matching the cell type, and the coordinates of diffusion and poly layer polygons listed in the GDS entry are obtained. The diffusion polygons are crossed with the poly layer polygons to obtain crossed GDS coordinates. The coordinates of the pin are then crossed with the crossed coordinates of the GDS to identify overlapping area. The overlapping area is defined as the location to be probed. [0016] According to another aspect of the invention, a computerized system for determining locations on an integrated circuit microchip to be probed is provided. The system comprising a computer having an input, an output, and a processor. The processor is pre-programmed to perform the steps: a. receive via the input a callout list of failures, the callout list including cell name and pin for each failure; b. interrogate a Def file to locate a Def entry matching the cell name and obtain from the Def entry cell type, cell location, and cell orientation data; c. interrogate a Lef file to locate a Lef entry matching the cell type and obtain from the Lef entry coordinates of the pin; d. interrogate a GDS file to locate a GDS entry matching the cell type and obtain coordinates of polygons listed in the GDS entry; e. perform a Boolean operation on the coordinates of the pin with the coordinates of the polygons to identify overlapping area; and f. output the overlapping area as the location to be probed. [0017] According to yet another aspect of the invention, the computer is pre-programmed to perform the steps: d1. obtain coordinates of diffusion layer polygons and coordinates of poly layer polygons from the GDS entry; and, d2. cross the coordinates of the diffusion layer polygons and the coordinates of the poly layer polygons to thereby obtained coordinates of crossed GDS polygon; and step e comprises perform a Boolean operation on the coordinates of the pin with the coordinates of the crossed GDS polygon to identify overlapping area. [0018] According to still another aspect of the invention, a computerized system for determining locations on an integrated circuit microchip to be probed and controlling a stage to place a prober at the proper location is provided. The system comprising a computer having an input, an output, and a processor. The processor is pre-programmed to perform the steps: a. receive via the input a callout list of failures, the callout list including cell name and pin for each failure; b. interrogate a Def file to locate a Def entry matching the cell name and obtain from the Def entry cell type, cell location, and cell orientation data; c. interrogate a Lef file to locate a Lef entry matching the cell type and obtain from the Lef entry coordinates of the pin; d. interrogate a GDS file to locate a GDS entry matching the cell type and obtain coordinates of polygons listed in the GDS entry; and e. determine from the interrogated files the proper location on the microchip to be probed. The system then provides an output to control the motion of a stage so as to align the prober with the location on the microchip. [0019] According to yet another aspect of the invention, a system and method to trace back a coordinate location of a probing location to a circuit element in the DUT layout and design proceeds as follows. The coordinate of an irregularity on the DUT are determined. The coordinates are used to interrogate the Def/Lef files to obtain cell data. The cell data is used to determine potential commonalities that may cause the irregularity. According another aspect a method for identifying elements on a device under test (DUT) that are suspect of causing irregularities manifested as photoemission locations on the DUT is disclosed. The method comprises receiving spatial coordinates of the photoemissions on the DUT; interrogating a Def file to locate Def entries matching the spatial coordinates and obtaining from the Def entries cell instance name and cell type, of corresponding cells; and interrogating schematic viewer to locate schematic entries matching the cell instance name for each of the cell names. In a further aspect the method further comprises analyzing the schematics entries to determine suspect elements. The analysis may comprise investigating whether all of the corresponding cells are being driven by a common net; investigating whether all of the corresponding cells are being driven by a common net or a plurality of nets; and, if the corresponding cells are driven by a plurality of nets, determining whether the plurality of nets are traceable back to a single parent net; investigating whether all of the corresponding cells are being driven by a common net or a plurality of nets; and, if the corresponding cells are driven by a plurality of nets, determining whether the plurality of nets are traceable back to a single cell instance; investigating whether all of the corresponding cells comprise same type of via structure; investigating whether all of the corresponding cells comprise same routing rules; or investigating whether all of the corresponding cells comprise same cell type. [0020] The method may further comprise interrogating a Lef file to locate Lef entries matching the cell types and obtaining from the Lef entries cell width, cell height, and cell pin data. [0021] According to another aspect, a method for identifying elements on a device under test (DUT) that are suspect of causing irregularities manifested as photoemission locations on the DUT is disclosed, comprising: a. receiving spatial coordinates of the photoemissions on the DUT; b. interrogating a Def file to locate Def entries matching the spatial coordinates and obtaining from the Def entries cell instance name and cell type, of corresponding cells; and, c. interrogate Lef file to obtain entries corresponding to the cell types to obtain cell width, cell height and cell pin data. The method may also comprise using coordinates of each cell pin obtained in step (c) to interrogate the Def file to thereby obtain net name for a net connected to each pin. The method may also comprise obtaining from said Def file for each net name at least one of: net connectivity, pin connectivity, metal level data, and vias data. The method may further comprise using said net connectivity to trace all relating cells connected to said net. Continue reading about System and method for determining probing locations on ic... Full patent description for System and method for determining probing locations on ic Brief Patent Description - Full Patent Description - Patent Application Claims Click on the above for other options relating to this System and method for determining probing locations on ic patent application. ###  How KEYWORD MONITOR works... a FREE service from FreshPatents1. Sign up (takes 30 seconds). 2. Fill in the keywords to be monitored. 3. Each week you receive an email with patent applications related to your keywords. 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