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  System and method for analyzing software performance without requiring hardwareUSPTO Application #: 20070089102Title: System and method for analyzing software performance without requiring hardware Abstract: A system and method for analyzing software performance without requiring hardware is presented. A timing description generator logs instruction performance characteristics for each of the assembly code's instructions. The performance characteristics identify whether an instruction issued or stalled during particular instruction cycles. Once the timing description generator cycles through the instructions and logs performance characteristics for each instruction, the timing description generator generates a performance graph. For each page line, the performance graph includes 1) dual-issue information if applicable, 2) instruction cycle counter values/stalled instruction identifier's that are positioned at corresponding line location values, and 3) the instruction. A developer may analyze the performance graph and identify code locations that require optimization in order to increase performance. (end of abstract) Agent: Ibm Corporation- Austin (jvl) C/o Van Leeuwen & Van Leeuwen - Austin, TX, US Inventor: David John Erb USPTO Applicaton #: 20070089102 - Class: 717140000 (USPTO) Related Patent Categories: Data Processing: Software Development, Installation, And Management, Software Program Development Tool (e.g., Integrated Case Tool Or Stand-alone Development Tool), Translation Of Code, Compiling Code The Patent Description & Claims data below is from USPTO Patent Application 20070089102. Brief Patent Description - Full Patent Description - Patent Application Claims
BACKGROUND OF THE INVENTION [0001] 1. Technical Field [0002] The present invention relates to a system and method for analyzing software performance without requiring hardware. More particularly, the present invention relates to a system and method for using assembly code to generate a performance graph that represents an instruction's execution progress as it relates to a program's actual instruction sequence. [0003] 2. Description of the Related Art [0004] Software designers are typically faced with the problem of accurately analyzing software performance and efficiency, whether hardware (e.g. a processor) is available or not. When the hardware is available, a typical software measurement technique is to run the software program on the hardware, and sampling the program counter's location at periodic intervals. After the program finishes, the samples may be drawn on a chart to assess software performance. However, this sampling technique only obtains one data point per interval. Thus, if the sampling interval is too large, much of the program run-time is effectively ignored. Conversely, if the sampling interval is too small, the act of tracing the program will itself affect the program's performance. In addition, both of these techniques only provide a fairly broad overview of the program's performance. [0005] When the hardware is in development and, therefore, not available, the above performance measurement technique is not possible. One option is to use a simulator, but a challenge found is that simulators are too slow and inaccurate to measure a program's performance based upon actual hardware, which thus makes it difficult to accurately assess a program's actual efficiency. This is an especially critical problem for hardware compiler developers because they have no simple way of determining compiler-generated assembly code quality. [0006] Furthermore, a challenge found is that processors themselves are becoming increasingly complicated. In modern processors, each hardware instruction has its own characteristics that affect performance, including multiple pipes, multiple-instruction issue, dependencies, instruction-pairing, latency, instruction location, and setup. Thus, measuring a program's performance before hardware becomes available is virtually impossible, and when hardware is available, only a broad overview is obtained. [0007] What is needed, therefore, is a system and method to accurately assess instruction-level software performance regardless of hardware availability. SUMMARY [0008] It has been discovered that the aforementioned challenges are resolved using a system and method for using assembly code to generate a performance graph that represents an instruction's execution progress as it relates to a program's actual instruction sequence. A timing description generator logs instruction performance characteristics for each of the assembly code's instructions, and generates a performance graph that includes the performance characteristics. As such, the performance graph provides an extremely accurate representation of an instruction when it executes on a processor. [0009] A compiler generates assembly code and passes the assembly code to the timing description generator. For example, a developer may add an optional pass to the compiler that loads the assembly code into the timing description generator. In one embodiment, the timing description generator resides within the compiler. In another embodiment, a software developer generates the assembly code instead of the compiler. [0010] The timing description generator receives the assembly code, and generates performance characteristics that provide a graphical representation of an instruction's performance. In one embodiment, the timing description generator displays each instruction on a separate page line, and displays the instruction's execution progress (performance characteristics) in the same page line on a "line location" basis. [0011] In order to track instruction cycles and line locations, the timing description generator includes a instruction cycle counter and a line location tracker, which may be counters that count up to a particular value and then reset. The instruction cycle counter increments on each instruction cycle, and tracks the last digit of an instruction cycle number, which produces an instruction cycle counter value between 0-9. The line location tracker increments on each instruction cycle and produces a line location value that signifies a particular location on a page line. For example, a line location value of "42" represents the 42.sup.nd space of a page line. Continuing with this example, an instruction cycle counter value of "4" and a line location value of "42" generates, on a performance graph, the number "4" at the 42.sup.nd space on a page line. [0012] When an instruction stalls (e.g. dependency conditions), the timing description generator logs a "stalled instruction identifier" and the line location value, which, when displayed on the performance graph, identifies that the instruction is stalled. The stalled instruction identifier may be an alphanumeric character or symbol, such as ".about.." Using the example described above, if the instruction stalls at the same instruction cycle, the performance graph displays a ".about." at the 42.sup.nd space on the page line instead of "4." [0013] In an embodiment that includes multiple-issue capability, the timing description generator logs, for applicable instructions, a "pipeline identifier" and a "dual-issued prevented identifier" or a "dual-issue allowed identifier." The pipeline identifier corresponds to the pipeline that is slotted to execute the instruction, such as "0" for pipeline 0 or "1" for pipeline 1. [0014] The dual-issue prevented identifier signifies that an instruction is eligible for dual-issue, but is prevented from issuing because of other instructions, such as an instruction start delay or another instruction using a required register. The dual-issue prevented identifier may be an alphanumeric character or symbol, such as "d." The dual-issue allowed identifier signifies that an instruction is eligible for dual-issue, and does in fact issue. The dual-issue allowed identifier may also be an alphanumeric character or symbol, such as "D." [0015] Once the timing description generator cycles through the instructions and logs performance characteristics for each instruction, the timing description generator generates the performance graph. For each page line, the performance graph includes 1) dual-issue information if applicable, 2) instruction cycle counter values/stalled instruction identifier's that are positioned at corresponding line location values, and 3) the instruction. A developer may analyze the performance graph and identify code locations that require optimization in order to increase software performance. [0016] The foregoing is a summary and thus contains, by necessity, simplifications, generalizations, and omissions of detail; consequently, those skilled in the art will appreciate that the summary is illustrative only and is not intended to be in any way limiting. Other aspects, inventive features, and advantages of the present invention, as defined solely by the claims, will become apparent in the non-limiting detailed description set forth below. BRIEF DESCRIPTION OF THE DRAWINGS [0017] The present invention may be better understood, and its numerous objects, features, and advantages made apparent to those skilled in the art by referencing the accompanying drawings. [0018] FIG. 1 is a diagram showing a timing description generator using assembly code to generate a performance graph; [0019] FIG. 2 is a diagram showing a performance graph of inefficient assembly code; [0020] FIG. 3 is a diagram showing a performance graph of efficient assembly code; [0021] FIG. 4 is a high-level flowchart showing steps taken in generating an assembly code performance graph; Continue reading... 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