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  System and method for adaptive frequency scalingUSPTO Application #: 20080028249Title: System and method for adaptive frequency scaling Abstract: A system and method provide adaptive frequency scaling for predicting the load on a processing unit and dynamically changing its clock frequency while keeping the synchronization with other processing units. The amount of data in an input memory waiting to be processed is a good indicator of the current load and thus embodiments of the present invention utilize the same concept for predicting the load on the processing unit. The frequency of operation is thus changed on the basis of the percentage of memory being occupied by its input data. Algorithms according to embodiments of the present invention allow the processing unit to use the maximum possible clock frequency only when it is required and to run at some lower frequencies in low processing power requirements. Operating the circuit at low frequency helps in reducing power consumption. (end of abstract)
Agent: Graybeal, Jackson, Haley LLP - Bellevue, WA, US Inventor: Parag Vijay Agrawal USPTO Applicaton #: 20080028249 - Class: 713501000 (USPTO) Related Patent Categories: Electrical Computers And Digital Processing Systems: Support, Clock, Pulse, Or Timing Signal Generation Or Analysis, Multiple Or Variable Intervals Or Frequencies The Patent Description & Claims data below is from USPTO Patent Application 20080028249. Brief Patent Description - Full Patent Description - Patent Application Claims
PRIORITY CLAIM [0001] This application claims priority from Indian patent application No. 931/Del/2006, filed Mar. 31, 2006, which is incorporated herein by reference. TECHNICAL FIELD [0002] The present invention relates to dynamic frequency scaling in electronic devices and more particularly to adaptive frequency scaling based on workload prediction for reducing power consumption in an electronic device. BACKGROUND [0003] Current trends in the chip industry point to the development of heterogeneous systems that will be able to support several complementary standards on a single chip in order to satisfy the user's demands in diverse application scenarios. These systems will lead to the integration of existing technologies and standards and will be based on reconfigurable architecture consisting of hardware units shared between different technologies and standards. [0004] Supporting different types of task or service requests in a heterogeneous system based on reconfigurable architectures and side-by-side satisfying the need for low power consumption is a challenge. [0005] An interactive mobile terminal, for example can spend 90% of system energy and time waiting for a user response. Such idle periods provide opportunities for dynamic power management and voltage scaling techniques to reduce the system power usage. Dynamic voltage frequency scaling (DVFS) is a technique to reduce active power consumption by scaling processor frequency and voltage to meet the required performance. This technique enables a chip to operate at different voltages and clock frequencies. In a system based on dynamic frequency clocking, the current operating frequency of a processing unit is set on the basis of different factors. These factors may be application, environment, or circuit specific. The conventional systems based on dynamic frequency clocking try to reduce the power consumption by changing the frequency on the basis of technology or standard or interface being used at that time. [0006] The most effective way to reduce dynamic power consumption on an implementation level is scaling of the supply voltage due to the quadratic dependence. The limiting parameter is the propagation delay through a digital circuit that increases with low supply voltages. [0007] The propagation delay through a CMOS circuit increases drastically as the supply voltage approaches the threshold voltage of the circuit. On the other hand, there is only little impact on performance with high supply voltages. Therefore, any voltage reduction must be balanced against performance reduction. To compensate and maintain the same data throughput extra hardware may be added. [0008] The working principle of dynamic frequency clocking has been explained with the help of a block diagram shown in FIG. 1. A Clock Divider Block (also known as Frequency Divider Block) (101) is used to generate multiple clock frequencies based on a master clock frequency which is the maximum frequency at which the synthesized system can work. The multiple clocks have been shown as 102A, 102B, 102C and 102D. A frequency selector (103) selects one of these frequencies based on some control signals generated by a control block (104). The delay that is needed by the dynamic frequency scaling circuit to change the clock frequency and remaining stabilized is taken into account at the time of implementation. [0009] One system and method for dynamic clock generation includes a clock controller for an Application Specific Integrated Circuit (ASIC) for a portable electronic device that dynamically and automatically varies the frequency of on-chip clocks in response to bandwidth requirements of the driven logic. The ASIC includes one or more oscillators used by phase locked loops (PLLs) to generate one or more master clocks. These master clocks are received by a system clock controller which derives various clocks of different frequencies from the master clocks. These derived clocks are used to drive the various controllers and peripherals connected to the ASIC. For example, the system clock controller preferably generates a memory clock for clocking the memory controller and the external memory devices, a bus clock for clocking the system bus, a CPU clock for clocking the CPU, and one or more peripheral clocks for clocking the various peripheral controllers and peripherals coupled to the ASIC. The various devices in the ASIC that can be accessed by other devices in the ASIC are known as "resources". The speed at which a resource is clocked affects the rate at which the resource can process data (i.e. the bandwidth of the resource). Every device in the ASIC that can access a resource, also known as a controller, has a request line coupled to the system clock controller to indicate when the controller is accessing a resource. In addition, the system clock controller has a programmable bandwidth register associated with each controller for holding a value representing the bandwidth utilized by the controller. The system clock controller also preferably includes an adder, a frequency table, and a multiplexer (MUX) for each clocked resource. When a controller accesses a resource, the controller signals the system clock controller via the request line. The system clock controller in turn, uses the adder to sum the values held in the bandwidth registers of all of the controllers that are currently accessing the resource. The resulting sum is then used as an index to an entry in the frequency table. The contents of the entry are applied to the selection lines of the MUX and dynamically select the appropriate clock frequency for the resource. Thus, the clock frequency for the resource is automatically determined by the total bandwidth utilization of the controllers requesting access to the resource. Accordingly, the clock frequency is preferably chosen so that the bandwidth of the resource closely matches the needed bandwidth. As a result, little power is wasted due to operating the resource at a higher clock frequency than is necessary. [0010] The above mentioned technique and other such techniques based on conventional dynamic frequency clocking reduce power consumption in an ASIC by changing the frequency of operation on the basis of the interface or standard being used at that time. These conventional techniques cannot work in the scenarios when there is only one technology or standard or interface controller is being used. In case of single standard, the processing requirement may change depending on the real time incoming data scenarios. For example, the real time data scenario may vary from time to time in terms of the number of packets arriving in a burst, size of each packet, inter-packet delay. Data sometimes can come as a burst of large number of packets whereas other times, the burst can just comprise only two or three packets. These variations have not been taken into account by any of the existing techniques of frequency scaling. [0011] Therefore, there arises a need for a system and method for dynamic frequency scaling which dynamically modifies the frequency of operation not on the basis of interface and standard being used but on the basis of load on the processing unit at a particular time, which is the right criterion for the processing requirement. SUMMARY [0012] Embodiments of the present invention provide an improved technique of dynamic frequency scaling which modifies the frequency of operation not on the basis of an interface and standard being used but on the basis of the load on the processing unit at a particular instant of time. [0013] An improved algorithm predicts the load on the processing unit and dynamically changes its clock frequency while keeping the synchronization with other processing units. The amount of data in the input memory waiting to be processed is a good indicator of the current load. Embodiments of the present invention utilize the same concept for predicting the load on the processing unit. The frequency of operation is thus changed on the basis of the percentage of memory being occupied by its input data. Algorithms according to embodiments of the present invention allow the processing unit to use the maximum possible clock frequency only when it is required and run at some lower frequencies in low processing power requirements. Operating the circuit at low frequency helps in reducing power consumption. The present invention also provides a method of implementing the proposed algorithm in the form of a simple digital circuit. [0014] To overcome the drawbacks of the prior art and to achieve the aforementioned objectives, according to one embodiment of the present invention, a system for adaptive frequency scaling in an electronic device includes an input interface block for receiving real time data, at least one processing unit for processing real time data received by the input interface block, at least one memory unit for storing the real time data before the data is processed by the processing unit, a frequency divider block for generating multiple clock frequencies from received clock frequency; and a control unit for selecting the appropriate frequency of operation from the multiple clock frequencies wherein the selection is based on the level of utilization of the memory unit. [0015] According to one embodiment of the present invention a method for adaptive frequency scaling in an electronic device includes initializing the processing unit of said electronic device at a first frequency, keeping track of data present in memory for processing, signaling the change in occupancy level of memory; and changing the frequency of operation of said processing unit in response to change in occupancy level of memory BRIEF DESCRIPTION OF THE DRAWINGS [0016] Embodiments of the invention will now be described with reference to the accompanying drawings. [0017] FIG. 1 shows the basic principle of dynamic frequency clocking in the form of a block diagram. [0018] FIG. 2 shows a block diagram of the basic structure of a standard chip. [0019] FIG. 3 shows a block diagram of an asynchronous FIFO according to an embodiment of the present invention. Continue reading... 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