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08/02/07 - USPTO Class 710 |  106 views | #20070180182 | Prev - Next | About this Page  710 rss/xml feed  monitor keywords

System and method for a distributed crossbar network using a plurality of crossbars

USPTO Application #: 20070180182
Title: System and method for a distributed crossbar network using a plurality of crossbars
Abstract: A system and method for single hop, processor-to-processor communication in a multiprocessing system over a plurality of crossbars are disclosed. Briefly described, one embodiment is a multiprocessing system comprising a plurality of processors having a plurality of high-bandwidth point-to-point links; a plurality of processor clusters, each processor cluster having a predefined number of the processors residing therein; and a plurality of crossbars, one of the crossbars coupling each of the processors of one of the plurality of processor clusters to each of the processors of another of the plurality of processor clusters, such that all processors are coupled to each of the other processors, and such that the number of crossbars is equal to [X*(X−1)/2], wherein X equals the number of processor clusters. (end of abstract)



Agent: Hewlett Packard Company - Fort Collins, CO, US
USPTO Applicaton #: 20070180182 - Class: 710317000 (USPTO)

Related Patent Categories: Electrical Computers And Digital Data Processing Systems: Input/output, Intrasystem Connection (e.g., Bus And Bus Transaction Processing), Bus Interface Architecture, Path Selecting Switch, Crossbar

System and method for a distributed crossbar network using a plurality of crossbars description/claims


The Patent Description & Claims data below is from USPTO Patent Application 20070180182, System and method for a distributed crossbar network using a plurality of crossbars.

Brief Patent Description - Full Patent Description - Patent Application Claims
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TECHNICAL FIELD

[0001] Embodiments are generally related to parallel processing computer systems and, more particularly, are related to a system and method for single hop, processor-to-processor communication in a multiprocessing system over a plurality of crossbars.

BACKGROUND

[0002] Multiprocessing systems employ many parallel-operating central processing units (CPUs) which independently perform tasks under the direction of a single operating system. One type of multiprocessing system is based upon a plurality of CPUs employing high-bandwidth point-to-point links (rather than a conventional shared-bus architecture) to provide direct connectivity between the CPUs and to router devices, input/output (I/O) devices, memory units and/or other CPUs.

[0003] Another type of multiprocessing system is based upon a plurality of computing nodes, each node employing high-bandwidth point-to-point links to communicate with other nodes. Each node may contain a plurality of components such as CPUs, memory units, I/O devices, etc. Individual nodes may have a different number of components. Both of these types of multiprocessing systems share the common problem of building a communication fabric to interconnect the endpoints. These endpoints will be referred to here as "processors," but could be any type of computing block including CPUs, memory devices, I/O devices, cells, nodes, etc.

[0004] Multiprocessing system designs often allow processors to be grouped into "clusters" of processors. The clusters are communicatively coupled together via router devices, such as crossbars, to facilitate communications among the various processors of the clusters. A plurality of processor clusters and crossbars may be assembled onto modular boards or in a chassis to create a large multiprocessing system having many processors.

[0005] As the size of conventional multiprocessing systems increase, the number of ports, and hence the size of the crossbars, also increases. Larger crossbars may be more difficult and expensive to fabricate because of the associated large area of silicon required for fabrication, because of the inherent failure rates associated with large integrated circuits on a single die, and because of the larger number of ports.

[0006] When vendor-provided crossbars are used in the fabrication of multiprocessing systems, the multiprocessing system designers must use crossbars having a predefined number of ports available on a vendor-provided crossbar. Thus, design limitations may be encountered if a desired number of ports are not available on a vendor-provided crossbar to couple the desired number of CPUs (and/or other devices) together.

[0007] Conventional solutions to these problems use multiple levels of crossbars to interconnect the processors. This requires signals to propagate through two or more crossbars, increasing the latencies through the system and decreasing system performance.

SUMMARY

[0008] One embodiment is a multiprocessing system comprising a plurality of processors having a plurality of high-bandwidth point-to-point links, a plurality of processor clusters, each processor cluster having a predefined number of the processors residing therein, and a plurality of crossbars, one of the crossbars coupling each of the processors of one of the plurality of processor clusters to each of the processors of another of the plurality of processor clusters, such that all processors are coupled to each of the other processors, and such that the number of crossbars is equal to (X*(X-1))/2, wherein X equals the number of processor clusters.

[0009] Another embodiment is a method for processor-to-processor communication between any pair of processors in a multiprocessing system using a single hop across one crossbar, the method comprising communicating from a selected one of the processors of a first cluster to another one of the processors in a second one of a plurality of clusters via a first crossbar such that the communicating uses a single hop across the first crossbar, and wherein the processors of the first cluster are coupled to the processors of the second cluster via the first crossbar, communicating from the selected processor of the first cluster to another processor in a third one of the plurality of clusters via a second crossbar such that the communicating uses a single hop across the second crossbar, and wherein the processors of the first cluster are coupled to the processors of the third cluster via the second crossbar, and communicating from the selected processor of the first cluster to another processor in an i.sup.th one of a plurality of clusters via an (i-1).sup.th crossbar such that the communicating uses a single hop across the (i-1).sup.th crossbar, and wherein the processors of the first cluster are coupled to the processors of the i.sup.th cluster via the (i-1).sup.th crossbar.

BRIEF DESCRIPTION OF THE DRAWINGS

[0010] The components in the drawings are not necessarily to scale relative to each other. Like reference numerals designate corresponding parts throughout the several views.

[0011] FIG. 1 is a block diagram illustrating an embodiment of a multiprocessing system.

[0012] FIG. 2 is a block diagram of the multiprocessing system of FIG. 1 illustrating link paths between processor clusters via the crossbar network.

[0013] FIG. 3 is a block diagram of a portion of the multiprocessing system of FIG. 1 illustrating link paths from a first processor cluster, through a plurality of crossbars, to the other processor clusters.

[0014] FIG. 4 is a block diagram illustrating in greater detail the coupling of processors in processor cluster 1 and processor cluster 2, via the link paths and the crossbar, of the multiprocessing system embodiment illustrated in FIG. 3.

[0015] FIG. 5 is a block diagram of an embodiment of a multiprocessing system having four processor clusters, each with four processors, illustrating the determined number of crossbars and the links through the crossbars.

[0016] FIG. 6 is a block diagram of an embodiment of a multiprocessing system illustrating processors having additional links for coupling to input/output (I/O) devices and/or to other processors of a processor cluster.

[0017] FIG. 7 is a block diagram of an embodiment of a multiprocessing system illustrating an 8+n port crossbar that has additional links for coupling to input/output (I/O) devices and/or to other crossbars.

[0018] FIG. 8 is a flowchart illustrating an embodiment of a process for single-hop connectivity for processor-to-processor communications over a single crossbar.

DETAILED DESCRIPTION

[0019] FIG. 1 is a block diagram illustrating an embodiment of a multiprocessing system 100. Multiprocessing systems 100 employ many parallel-operating processing units which independently perform tasks under the direction of a single operating system. One embodiment of multiprocessing system 100 is based upon a plurality of processing units employing high-bandwidth point-to-point links 102 (rather than a conventional shared-bus architecture) to provide direct connectivity between the processing units and to input/output (I/O) devices, memory units and/or other processors.

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