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Synopsys, Inc. C/o Park, Vaughan & Fleming LLP patentsThe following is a sampling of recent Synopsys, Inc. C/o Park, Vaughan & Fleming LLP patent applications (USPTO Patent Application #, Patent Title) sorted by month.
September 2007 - Synopsys, Inc. C/o Park, Vaughan & Fleming LLP patents
20070206354 - Slack-based transition-fault testing
August 2007 - Synopsys, Inc. C/o Park, Vaughan & Fleming LLP patents
20070198958 - Method and apparatus for using a database to quickly identify and correct a manufacturing problem area in a layout
20070192751 - Method and apparatus to reduce random yield loss
20070180414 - Facilitating structural coverage of a design during design verification
July 2007 - Synopsys, Inc. C/o Park, Vaughan & Fleming LLP patents
20070174797 - Predicting ic manufacturing yield by considering both systematic and random intra-die process variations
20070174808 - Method and apparatus for determining a process model that uses feature detection
20070162888 - Method and apparatus to determine if a pattern is robustly manufacturable
20070156367 - Method and apparatus for determining the performance of an integrated circuit
June 2007 - Synopsys, Inc. C/o Park, Vaughan & Fleming LLP patents
20070143717 - Formally proving the functional equivalence of pipelined designs containing memories
May 2007 - Synopsys, Inc. C/o Park, Vaughan & Fleming LLP patents
20070121759 - Method and apparatus for integrated distribution function capture
20070124707 - Method and apparatus for facilitating variation-aware parasitic extraction
20070118339 - Method and apparatus for distinguishing combinational designs
April 2007 - Synopsys, Inc. C/o Park, Vaughan & Fleming LLP patents
20070082281 - Compensating for effects of topography variation by using a variable intensity-threshold
February 2007 - Synopsys, Inc. C/o Park, Vaughan & Fleming LLP patents
20070044045 - Method and apparatus for optimizing a logic network in a digital circuit
20070038973 - Method and apparatus for quickly determining the effect of placing an assist feature at a location in a layout
20070033561 - Speeding up timing analysis by reusing delays computed for isomorphic subcircuits
December 2006 - Synopsys, Inc. C/o Park, Vaughan & Fleming LLP patents
20060294485 - Method and apparatus for routing an integrated circuit
20060288318 - Method and apparatus for associating an error in a layout with a cell
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This listing is an abstract for educational and research purposes is only meant as a recent sample of applications filed, not a comprehensive history. Freshpatents.com is not affiliated or associated with Synopsys, Inc. C/o Park, Vaughan & Fleming LLP in any way and there may be associated servicemarks. This data is also published to the public by the USPTO and available for free on their website. Note that there may be alternative spellings for Synopsys, Inc. C/o Park, Vaughan & Fleming LLP with additional patents listed. Browse our Agent directory for other possible listings.
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