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  Symmetrical mimcap capacitor designRelated Patent Categories: Active Solid-state Devices (e.g., Transistors, Solid-state Diodes), Housing Or Package, With Semiconductor Element Forming Part (e.g., Base, Of Housing)The Patent Description & Claims data below is from USPTO Patent Application 20070267733. Brief Patent Description - Full Patent Description - Patent Application Claims
TECHNICAL FIELD [0001] This invention relates generally to capacitors and, more particularly, to the methods and systems for capacitor structures with symmetrical polarity characteristics. BACKGROUND ART [0002] On-chip capacitors are critical components of integrated circuits that are fabricated on silicon semiconductors. These capacitors are used for a variety of purposes: illustrative examples include bypass and capacitive matching as well as coupling and decoupling. The design and implementation of capacitor structures on silicon semiconductor chips may be dependent upon one or more symmetrical structural, target circuit quality and low parasitic resistance performance characteristics. [0003] More particularly, capacitor structures may be categorized as being formed in one of two regions: the Front End Of (production) Line (FEOL), or the Back End Of the Line (BEOL). In integrated-circuit fabrication lines, FEOL conventionally refers to earlier process stages that directly modify the semiconductor substrate or the immediate contacts to it; for example, dopant diffusion and implantation, sputtering of gate films, oxidations, and the patterning steps associated with these. In contradistinction, the BEOL is metalization (PVD) for interconnects and vias (vertical interconnects between planar interconnects) and associated non-conducting depositions and growths (for example, polymers, glasses, oxides, nitrides, and oxinitrides) for electrical isolation, dielectrics (for capacitance), diffusion barriers, and mechanical passivation (in particular, to prevent failure of interconnects by electromigration and stress migration). FEOL and BEOL are used in transferred sense to refer to the levels of an IC fabricated in the corresponding stages. BEOL is the metalization layers (say between four and ten) and associated insulating layers, and FEOL everything below that--mostly transistors. [0004] It is known to use a metal oxide silicon (MOS) capacitor, or MOSCAP, for semiconductor chip capacitor elements formed on the chip substrate in the FEOL. However, MOSCAP capacitors generally require large chip area footprints in integrated circuits (IC). Accordingly, design requirements typically result in requiring large semiconductor chip footprint areas or real estate for MOSCAP capacitor structures relative to their circuit capacitance properties, resulting in high production costs and reduced semiconductor chip area availability for other circuit structures. Moreover, current leakage during a semiconductor circuit's idle mode is known to result in increased power consumption. Silicon semiconductor chip capacitor structures thus usually require large MOSCAP capacitor structures in order to avoid current leakage problems. [0005] As the production cost of an IC is generally proportional to the real estate required, it is desired to reduce IC chip costs by reducing the footprint required for a MOSCAP structure. Accordingly, one possible technique for reducing FEOL MOSCAP footprints is to form additional capacitor structures in the BEOL in circuit communication with the FEOL MOSCAP, preferably increasing the capacitance of the total FEOL/BEOL capacitor structure while resulting in a relatively smaller FEOL MOSCAP footprint. [0006] Two types of capacitors commonly utilized in the BEOL are a Metal-Insulator-Metal Capacitor (MIMCAP) 100 schematically illustrated in FIG. 1 with respect to a chip substrate 114, and a Vertical Native Capacitor (VNCAP) 200 schematically illustrated in FIG. 2. (FEOL structures are omitted for simplicity of illustration.) The MIMCAP 100 comprises a first plate 110 and a second plate 112, each having a connector or port 116, 118, respectively, with a dielectric material 120 placed between the plates 110, 112 to complete the capacitive structure. The VNCAP 200 also comprises a first plate 210 and a second plate 212, each having a connector or port 216, 218, respectively, with a dielectric material 220 placed between the plates 210, 212 to complete the capacitive structure. What is significant is that the lateral arrangement of the MIMCAP 100 plates 110, 112 above the substrate footprint 130 results in asymmetrical parasitic capacitances of the respective plates 110, 112, whereas the vertical arrangement of the generally parallel VNCAP 200 plates 210, 212, projecting parallel plate footprints 230, 232, respectively, results in symmetrical parasitic plate 210, 212 capacitance properties. [0007] The MIMCAP 100 and VNCAP 200 each offer distinctive circuit behaviors and, in some BEOL applications, combinations of one or more MIMCAP's 100 with one or more VNCAP's 200 may be preferred. However, the asymmetrical parasitic capacitances of the MIMCAP 100 plates 110, 112 produce a polarity for the port terminals 116, 118. In one respect, a circuit using port 116 as an input port and port 118 as an output port results in different equivalent circuit behavior. In another respect, the polarity difference may render the MIMCAP 100 a unidirectional device. And incorrect polarity usage may cause circuit performance degradation. Accounting for such polarity issues results in circuit design inefficiencies as additional design time must be expended to distinguish between input and output polarities. [0008] In many instances, multiple MIMCAPS capacitors are required on a single chip substrate, with each having the same intrinsic capacitance value. In configurations wherein the capacitors are close to the substrate, the variable extrinsic capacitances between the bottom plates closest to the substrate cannot be adequately controlled for in circuit design, as the value of the extrinsic capacitances may not be precisely predicted. Therefore, in conventional prior art practices wherein all of the plates closest to the substrate are connected together, and all of the plates farthest from the substrate are connected together, divergent capacitance values are effectively created in the otherwise individually equivalent capacitors. [0009] Additional problems arise for high-density on-chip BEOL capacitor structures incorporating both MIMCAP's 100 and VNCAP's 200, since parallel connections between the VNCAP 200 and MIMCAP 100 components must be provided to accommodate the divergent polarities of the port terminals 116, 118, and forming such parallel connections presents structural limitations on the resultant composite MIMCAP 100/VNCAP 200 BEOL structure that diminishes possible chip real estate efficiencies. It also presents other difficulties in providing a symmetrical BEOL capacitor structure created from multiple VNCAP's and MIMCAP's. [0010] What is needed is a system and method for enabling the efficient incorporation of lateral MIMCAP capacitors in BEOL applications. Accordingly, it is necessary to develop a technique to provide each of a plurality of MIMCAP capacitors on a substrate with symmetry with respect to the substrate. SUMMARY OF THE INVENTION [0011] In one aspect, a capacitance circuit assembly mounted on a semiconductor chip, and methods for making the same, are provided comprising at least two capacitors mounted close to a substrate, wherein each capacitor has a lateral lower conductive plate mounted near enough to the substrate to have extrinsic capacitance greater than an upper plate extrinsic capacitance. One half of lower plates and one half of upper plates are connected to a first port, and a remaining one half of upper plates and lower plates are connected to a second port, the first and second port having about equal extrinsic capacitance from the lower plates. [0012] In another aspect, the at least two capacitors are Metal-Insulator-Metal Capacitors, and the capacitance circuit assembly is located in a back-end-of-line semiconductor capacitor circuit. [0013] In another aspect, the substrate further comprises a front-end-of-line capacitor defining a substrate footprint, and the at least two capacitors are electrically connected to the front-end-of-line capacitor and disposed above the substrate within the front-end-of-line capacitor footprint. [0014] In another aspect, the at least two capacitors are at least four capacitors. In a further aspect, the at least four capacitors are arrayed in a rectangular array generally parallel to the substrate. [0015] In another aspect, a Vertical Native Capacitor is electrically connected to at least two capacitors and disposed above the substrate within the front-end-of-line capacitor footprint. [0016] In another aspect, the first and second plates are formed of the same material. In a further aspect, the plates are a metal or polysilicon, and/or the dielectric material has a permeability value greater than about 4 (er >4). BRIEF DESCRIPTION OF THE DRAWINGS [0017] FIGS. 1 and 2 are schematic perspective depictions of two techniques for mounting capacitors on a substrate; [0018] FIG. 3 depicts a schematic perspective of a MIM capacitor in relation to a substrate; [0019] FIG. 4 depicts a schematic perspective of a conventional prior art connection of two MIM capacitors relative to a substrate; [0020] FIG. 5 depicts a schematic perspective of a connection of two MIM capacitors relative to a substrate according to this invention; Continue reading... Full patent description for Symmetrical mimcap capacitor design Brief Patent Description - Full Patent Description - Patent Application Claims Click on the above for other options relating to this Symmetrical mimcap capacitor design patent application. ###  How KEYWORD MONITOR works... a FREE service from FreshPatents1. Sign up (takes 30 seconds). 2. Fill in the keywords to be monitored. 3. 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