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Symmetric capacitor structure

This application is a continuation application claiming priority to Ser. No. 11/421,774, filed Jun. 2, 2006.

1. Technical Field

The present invention relates to a semiconductor device comprising a symmetric capacitor structure.

2. Related Art

A device within an electrical structure typically does not comprise terminals extending from the device that comprise equivalent electrical properties. Terminals that do not comprise equivalent electrical properties may cause other devices within the electrical structure to operate inefficiently. Thus, there is a need for a structure and associated method for forming an electrical structure with terminals comprising equivalent electrical properties.

The present invention provides a structure, comprising: a first doped region formed within a substrate, wherein said first doped region comprises a first dopant having a first polarity; a second doped region formed within said substrate and over said first doped region, wherein said second doped region forms a first electrode of a symmetric capacitor; a third doped region formed within said substrate and over first doped region, wherein said third doped region forms a second electrode of said symmetric capacitor, wherein each of said second doped region and said third doped region comprises a same second dopant having a second polarity, wherein each of said second doped region and said third doped region is formed simultaneously, and wherein said first doped region, said second doped region, and said third doped region in combination form a PN junction; and a first shallow trench isolation structure formed between said second doped region and said third doped region, wherein said first shallow trench isolation structure electrically isolates said second doped region from said third doped region, wherein said symmetric capacitor comprises a main capacitance, wherein said structure comprises a first parasitic capacitance and a second parasitic capacitance, wherein said main capacitance comprises a capacitance between said second doped region and said third doped region, wherein said first parasitic capacitance represents a parasitic connection between said second doped region and said first doped region, wherein said second parasitic capacitance represents a parasitic connection between said third doped region and said first doped region, wherein a first distance between said second doped region and said first doped region is about equal to a second distance between said third doped region and said first doped region, and wherein said first parasitic capacitance is about equal to said second parasitic capacitance.

The present invention provides a method for forming a structure, comprising:

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Previous Patent Application:
Method and system for utilizing dram components in a system-on-chip
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Method of fabricating a trench capacitor having increased capacitance
Industry Class:
Active solid-state devices (e.g., transistors, solid-state diodes)

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