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Switch control apparatus, semiconductor device test apparatus and sequence pattern generating programSwitch control apparatus, semiconductor device test apparatus and sequence pattern generating program description/claimsThe Patent Description & Claims data below is from USPTO Patent Application 20060208767, Switch control apparatus, semiconductor device test apparatus and sequence pattern generating program. Brief Patent Description - Full Patent Description - Patent Application Claims
[0001] This patent application claims priority from a Japanese patent application No. 2004-089022 filed on Mar. 25, 2004, the contents of which are incorporated herein by reference. BACKGROUND OF THE INVENTION [0002] 1. Field of the Invention [0003] The present invention relates to a switch control apparatus, a semiconductor testing apparatus, and a machine readable medium storing thereon a generating program. More particularly, the present invention relates to a switch control apparatus, a semiconductor testing apparatus, and a machine readable medium storing thereon a generating program for controlling timing of opening and closing a switch. [0004] 2. Description of the Related Art [0005] A number of semiconductor switches are provided in a circuit used for a semiconductor testing apparatus. Order and timing of opening and closing the switches are predetermined and if opening and closing are conducted against the order and timing, sometimes the semiconductor testing apparatus or a semiconductor under test is broken down. For example, if a number of switches are open all at once, sometimes the semiconductor under test is damaged by spike voltage. [0006] Therefore, conventionally, for each semiconductor switch, a technique to provide a sequence circuit which is a logic circuit for controlling timing of opening and closing of the semiconductor switch is used. [0007] However, in case of frequently repeat of opening and closing of the switch being required, a logic circuit constituting the sequence circuit becomes complicated. Further, for every testing apparatus for performing a different testing, an exclusive sequence circuit should be prepared. Further, when it is required to maintain the position of the switch to be opened or closed for a while after a testing is started, even if it is a case where the switch same is to be controlled about the same examination, a different kind of control is sometimes required according to an open/close state predetermined before the testing is started. Thus, sometimes the sequence circuit becomes more complicated. [0008] Accordingly, it is an object to make a program for writing sequence of instructing open or close of a switch on a sequence memory and make the contents of a testing easily changed by rewriting the sequence memory, without composing a sequence circuit by a logic circuit. SUMMARY OF THE INVENTION [0009] Therefore, it is an object of the present invention to provide a switch control apparatus, a semiconductor testing apparatus, and a machine readable medium storing thereon a generating program, which are capable of overcoming the above drawbacks accompanying the conventional art. The above and other objects can be achieved by combinations described in the independent claims. The dependent claims define further advantageous and exemplary combinations of the present invention. [0010] According to the first aspect of the present invention, a switch control apparatus for controlling a switch, includes a sequence memory for recording a sequence pattern includes open/close instruction data which instruct to open/close the switch thereon; an address control module for sequentially retrieving each of the open/close instruction data of the sequence pattern from the sequence memory; and an open/close state storage module for storing an open/close state instructed by changed open/close instruction data when the open/close instruction data retrieved by the address control module is changed, wherein the switch opens or closes in response to the open/close state stored by the open/close state storage module. [0011] Further, the open/close state storage module may hold the open/close state stored before a first open/close instruction data is retrieved, while the same data as the first open/close instruction data is consecutively retrieved from the time when the first open/close instruction data of the sequence pattern is retrieved. [0012] Further, the sequence memory may store a plurality of sequence patterns, the address control module may retrieve each of the open/close instruction data of the plurality of sequence patterns, and the open/close state storage module may hold the open/close state instructed by the last open/close instruction data of another one of the sequence patterns retrieved before one of the sequence patterns is retrieved, while the same data as the first open/close instruction data is consecutively retrieved from the time when the first open/close instruction data of the one of the sequence patterns is retrieved. [0013] Further, the open/close state storage module may include: a first flip-flop for storing the open/close instruction data retrieved by the address control module; a second flip-flop for storing the open/close instruction data retrieved by the address control module before the open/close instruction data stored by the first flip-flop; a third flip-flop for storing the open/close state instructed by the open/close instruction data retrieved by the address control module in case the open/close instruction data stored by the first and second flip-flops are different, and the switch may open or close in response to the open/close state stored by the third flip-flop. [0014] Further, the address control module may store the first open/close instruction data of the sequence pattern in both of the first and second flip-flops. [0015] Further, the address control module may retrieve the first open/close instruction data of the sequence pattern within a shorter time than that for the second or later open/close instruction data and stores them in both of the first and second flip-flops. [0016] According to the second aspect of the present invention, a semiconductor test apparatus for testing a device under test by providing an electric power to each part of the device under test sequentially, includes: a plurality of switches for controlling an electric power input to or output from the device under test; a first sequence memory for storing a sequence pattern includes open/close instruction data which instructs to open/close the switch for each switch; a first address control module for sequentially retrieving each of the open/close instruction data of each of the plurality of sequence patterns from the first sequence memory; and a first open/close state storage module provided for each switch for storing an open/close state instructed by changed open/close instruction data when the open/close instruction data, which instructs to open/close the switch, retrieved by the first address control module is changed, wherein each of the plurality of switches opens or closes in response to the open/close state stored by the first open/close state storage module provided for each switch. [0017] Further, the first sequence memory may store the sequence pattern for each test mode for testing the device under test, and in case the test mode is changed, the first open/close state storage module may hold the open/close instruction instructed by a last open/close instruction data of the sequence pattern before the test mode is changed, while the same data as the first open/close instruction data is consecutively retrieved from the time when the first open/close instruction data of the sequence pattern is retrieved after the test mode is changed. [0018] Further, the semiconductor test apparatus may further include: a second sequence memory for storing a sequence pattern includes open/close instruction data, which instructs to open/close other switch than the plurality of switches; a second address control module for sequentially retrieving each of the open/close instruction data of the sequence pattern from the second sequence memory in case an open/close state stored on the first open/close state storage module is changed; and a second open/close state storage module for storing an open/close state instructed by changed open/close instruction data in case the open/close instruction data, which instructs to open/close the other switch, retrieved by the second address control module is changed, wherein the other switch may open or close in response to the open/close state stored by the second open/close state storage module provided for each of the other switch. [0019] According to the third aspect of the present invention, a machine readable medium storing thereon a computer program for generating a sequence pattern includes open/close instruction data, which instructs to open/close a switch, output from a switch control apparatus to the switch, is provided, the computer program generating a sequence pattern includes an open/close instruction data, which is different from an open/close instruction data output when the open/close state storage module starts opening or closing the switch, as an open/close instruction data output until the open/close state storage module starts opening or closing the switch from the time when the address control module starts retrieving the open/close instruction data of the sequence data, wherein the switch control apparatus includes: a sequence memory for recording a sequence pattern includes open/close instruction data which instructs to open/close the switch thereon; an address control module for sequentially retrieving each of the open/close instruction data of the sequence pattern from the sequence memory; and an open/close state storage module for storing an open/close state instructed by changed open/close instruction data when the open/close instruction data retrieved by the address control module is changed. [0020] The summary of the invention does not necessarily describe all necessary features of the present invention. The present invention may also be a sub-combination of the features described above. The above and other features and advantages of the present invention will become more apparent from the following description of the embodiments taken in conjunction with the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS [0021] FIG. 1 is a block diagram of a semiconductor testing apparatus. Continue reading about Switch control apparatus, semiconductor device test apparatus and sequence pattern generating program... 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