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Sudarshan Kadambi patents

Recent bibliographic sampling of Sudarshan Kadambi patents listed/published in the public domain by the USPTO (USPTO Patent Application #,Title):



02/14/13 - 20130042074 - Prefetch unit
In one embodiment, a processor comprises a prefetch unit coupled to a data cache. The prefetch unit is configured to concurrently maintain a plurality of separate, active prefetch streams. Each prefetch stream is either software initiated via execution by the processor of a dedicated prefetch instruction or hardware initiated via...
Inventors: Sudarshan Kadambi, Puneet Kumar, Po-yung Chang (Apple Inc.)

11/01/12 - 20120278685 - Store handling in a processor
In one embodiment, a processor may be configured to write ECC granular stores into the data cache, while non-ECC granular stores may be merged with cache data in a memory request buffer. In one embodiment, a processor may be configured to detect that a victim block writeback hits one or...
Inventors: Ramesh Gunna, Po-yung Chang, Sudarshan Kadambi

05/24/12 - 20120131281 - Converting victim writeback to a fill
In one embodiment, a processor may be configured to write ECC granular stores into the data cache, while non-ECC granular stores may be merged with cache data in a memory request buffer. In one embodiment, a processor may be configured to detect that a victim block writeback hits one or...
Inventors: Ramesh Gunna, Sudarshan Kadambi

10/27/11 - 20110264864 - Prefetch unit
In one embodiment, a processor comprises a prefetch unit coupled to a data cache. The prefetch unit is configured to concurrently maintain a plurality of separate, active prefetch streams. Each prefetch stream is either software initiated via execution by the processor of a dedicated prefetch instruction or hardware initiated via...
Inventors: Sudarshan Kadambi, Puneet Kumar, Po-yung Chang

02/24/11 - 20110047336 - Converting victim writeback to a fill
In one embodiment, a processor may be configured to write ECC granular stores into the data cache, while non-ECC granular stores may be merged with cache data in a memory request buffer. In one embodiment, a processor may be configured to detect that a victim block writeback hits one or...
Inventors: Ramesh Gunna, Sudarshan Kadambi

10/21/10 - 20100268894 - Prefetch unit
In one embodiment, a processor comprises a prefetch unit coupled to a data cache. The prefetch unit is configured to concurrently maintain a plurality of separate, active prefetch streams. Each prefetch stream is either software initiated via execution by the processor of a dedicated prefetch instruction or hardware initiated via...
Inventors: Sudarshan Kadambi, Puneet Kumar, Po-yung Chang

04/29/10 - 20100106916 - Data cache block zero implementation
In one embodiment, a processor comprises a core configured to execute a data cache block write instruction and an interface unit coupled to the core and to an interconnect on which the processor is configured to communicate. The core is configured to transmit a request to the interface unit in...
Inventors: Ramesh Gunna, Sudarshan Kadambi, Peter J. Bannon

10/08/09 - 20090254734 - Partial load/store forward prediction
In one embodiment, a processor comprises a prediction circuit and another circuit coupled to the prediction circuit. The prediction circuit is configured to predict whether or not a first load instruction will experience a partial store to load forward (PSTLF) event during execution. A PSTLF event occurs if a plurality...
Inventors: Sudarshan Kadambi, Po-yung Chang, Eric Hao

05/07/09 - 20090119488 - Prefetch unit
In one embodiment, a processor comprises a prefetch unit coupled to a data cache. The prefetch unit is configured to concurrently maintain a plurality of separate, active prefetch streams. Each prefetch stream is either software initiated via execution by the processor of a dedicated prefetch instruction or hardware initiated via...
Inventors: Sudarshan Kadambi, Puneet Kumar, Po-yung Chang

Apple Inc.

Archived*
(*May have duplicates - we are upgrading our archive.)

20090254734 - Partial load/store forward prediction
20090254734 - Partial load/store forward prediction
20090119488 - Prefetch unit
20080307167 - Converting victim writeback to a fill
20080307166 - Store handling in a processor
20080177988 - Partial load/store forward prediction
20070294482 - Prefetch unit
20070113020 - Data cache block zero implementation
20070038846 - Partial load/store forward prediction


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The bibliographic references displayed about Sudarshan Kadambi's patents are for a recent sample of Sudarshan Kadambi's publicly published patent applications. The inventor/author may have additional bibliographic citations listed at the USPTO.gov. FreshPatents.com is not associated or affiliated in any way with the author/inventor or the United States Patent/Trademark Office but is providing this non-comprehensive sample listing for educational and research purposes using public bibliographic data published and disseminated from the United States Patent/Trademark Office public datafeed. This information is also available for free on the USPTO.gov website. If Sudarshan Kadambi filed recent patent applications under another name, spelling or location then those applications could be listed on an alternate page. If no bibliographic references are listed here, it is possible there are no recent filings or there is a technical issue with the listing--in that case, we recommend doing a search on the USPTO.gov website.

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