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07/27/06 - USPTO Class 716 |  114 views | #20060168552 | Prev - Next | About this Page  716 rss/xml feed  monitor keywords

Substrate mapping

USPTO Application #: 20060168552
Title: Substrate mapping
Abstract: A method for fabricating semiconductor die packages and semiconductor die packages including a mounting substrate and dice attached thereto. The mounting substrate includes multiple die attach sites and a designator having substrate identification information. The die attach sites are evaluated and categorized as either good or defective die attach sites, wherein the evaluated information is saved in an electronic file as mapped information. A die is attached to the die attach sites in accord with the information, wherein known good dice are attached to the good die attach sites and known defective dice are attached to the defective die attach sites. The assembly is then encapsulated in a transfer molding operation. (end of abstract)



Agent: Trask Britt - Salt Lake City, UT, US
Inventors: Warren M. Farnworth, Derek J. Gochnour
USPTO Applicaton #: 20060168552 - Class: 716012000 (USPTO)

Related Patent Categories: Data Processing: Design And Analysis Of Circuit Or Semiconductor Mask, Circuit Design, Routing (e.g., Routing Map, Netlisting)

Substrate mapping description/claims


The Patent Description & Claims data below is from USPTO Patent Application 20060168552, Substrate mapping.

Brief Patent Description - Full Patent Description - Patent Application Claims
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Data processing: design and analysis of circuit or semiconductor mask

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