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  Structure for uniform triggering of multifinger semiconductor devices with tunable trigger voltageUSPTO Application #: 20080050880Title: Structure for uniform triggering of multifinger semiconductor devices with tunable trigger voltage Abstract: The present invention provides a method in which a low-resistance connection between the MOS channel and silicided source/drain regions is provided that has an independence from the extension ion implant process as well as device overlap capacitance. The method of the present invention broadly includes selectively removing outer spacers of an MOS structure and then selectively plating a metallic or intermetallic material on exposed portions of a semiconductor substrate that were previously protected by the outer spacers. The present invention also provides a semiconductor structure that is formed utilizing the method. The semiconductor structure includes a low-resistance connection between the silicided source/drain regions and the channel regions which includes a selectively plated metallic or intermetallic material. (end of abstract) Agent: Scully, Scott, Murphy & Presser, P.C. - Garden City, NY, US Inventors: Michel J. Abou-Khalil, Robert Gauthier, Hongmei Li, Junjun Li, Souvick Mitra, Christopher S. Putnam USPTO Applicaton #: 20080050880 - Class: 438299000 (USPTO) Related Patent Categories: Semiconductor Device Manufacturing: Process, Making Field Effect Device Having Pair Of Active Regions Separated By Gate Structure By Formation Or Alteration Of Semiconductive Active Regions, Having Insulated Gate (e.g., Igfet, Misfet, Mosfet, Etc.), Self-aligned The Patent Description & Claims data below is from USPTO Patent Application 20080050880. Brief Patent Description - Full Patent Description - Patent Application Claims
RELATED APPLICATIONS [0001] This application is a divisional of U.S. patent application Ser. No. 11/164,378, filed Nov. 21, 2005. FIELD OF THE INVENTION [0002] The present invention relates to a semiconductor structure and a method of fabricating the same. More particularly, the present invention relates to a semiconductor structure that has a low-resistance extension connection (on the order of less than 50 ohms/square, preferably from about 2 to about 30 ohms/square; prior art values are typically from about 50 to about 500 ohms/square) between the channel of a metal oxide semiconductor field effect transistor (MOSFET) and silicided source/drain regions with an independence from extension implants and device overlap (i.e., Miller) capacitance. The present invention also provides a method of fabricating such a semiconductor structure in which portions of the source/drain extension regions located between the silicided source/drain regions and the channel are selectively plated with a metallic or intermetallic material. BACKGROUND OF THE INVENTION [0003] Field effect transistors (FETs) are the basic building block of today's integrated circuit. Such transistors can be formed in conventional bulk substrates (such as silicon) or in semiconductor-on-insulator (SOI) substrates [0004] State of the art metal oxide semiconductor (MOS) transistors are fabricated by depositing a gate stack material over a gate dielectric and a substrate. Generally, the MOS transistor fabrication process implements lithography and etching processes to define the conductive, e.g., poly-Si, Si, gate structures. The gate structure and substrate are thermally oxidized, and, after this, source/drain extensions are formed by implantation. Sometimes the implant is performed using a spacer to create a specific distance between the gate and the implanted junction. In some instances, such as in the manufacture of an n-FET device, the source/drain extensions for the n-FET device are implanted with no spacer. For a p-FET device, the source/drain extensions are typically implanted with a spacer present. A thicker spacer is typically formed after the source/drain extensions have been implanted. The deep source/drain implants are then performed with the thick spacer present. High temperature anneals are performed to activate the junctions after which the source/drain and top portion of the gate are generally silicided. Silicide formation typically requires that a refractory metal be deposited on a Si-containing substrate followed by a high temperature thermal anneal process to produce the silicide material. The silicide process forms low resistivity contacts to the deep source/drain regions and the gate conductor. [0005] In order to be able to make integrated circuits (ICs), such as memory, logic, and other devices, of higher integration density than currently feasible, one has to find a way to further downscale the dimensions of field effect transistors (FETs), such as metal oxide semiconductors. The downscaling of transistor dimensions allows for improved performance as well as compactness, but such downscaling has some device degrading effects. Generational improvements for high performance MOS devices are obtained by decreasing the transistor line width, reducing the gate oxide thickness, and decreasing the source/drain extension resistance. Smaller transistor line width results in less distance between the source and the drain. This results in faster switching speeds for complementary metal oxide semiconductor (CMOS) circuits. However, as the transistor line width gets smaller, the overall area available for silicidation is reduced. This means that as transistor line width shrinks, line resistance (i.e., series resistance) is increased. Increased line resistance causes degradation in device performance. [0006] Source/drain extension resistance is another important performance factor. Drive currents may be increased by reducing source/drain extension resistance. Increasing the source/drain extension dose leads to lower resistance but has an undesirable side effect of increasing the junction depth. [0007] As such, there is a need for providing a semiconductor structure having a low-resistance extension connection between the channel and the silicided source/drain regions with an independence from extension implants and device overlap (i.e., Miller) capacitance. Miller capacitance, which can also be referred to as the gate-drain or gate-source capacitance, increases the capacitance by a factor related to the voltage gain of a transistor. SUMMARY OF THE INVENTION [0008] The present invention provides a method in which a low-resistance connection between the device channel and silicided source/drain regions is provided that has an independence from the extension ion implant process as well as device overlap capacitance. The method of the present invention broadly includes selectively removing outer spacers of an MOS structure and then selectively plating a metallic or intermetallic material on exposed portions of a semiconductor substrate that were previously protected by the outer spacers. The exposed portions are located between the silicided source/drain regions and the channel region (or the edge of the gate conductor). [0009] In general terms, the method of the present invention comprises: [0010] providing a MOS structure that at includes at least one gate region located on a surface of a semiconductor substrate, said at least one gate region comprising source/drain regions and source/drain extension regions in said semiconductor substrate that are separated by a channel region, a gate dielectric and a gate conductor located above said channel region, an offset spacer located on sidewalls of at least said gate conductor and an outer spacer adjacent to said offset spacer and silicide contacts located atop the source/drain regions adjacent said outer spacer; [0011] removing said outer spacer to expose a surface portion of the semiconductor substrate including said source/drain extension regions; and [0012] selectively plating a metallic or intermetallic material on said exposed surface portion of said semiconductor substrate including said source/drain extension regions. [0013] In addition to the method, the present invention also relates to a semiconductor structure that is formed utilizing the method described above. In broad terms, the semiconductor structure includes a low-resistance connection between the silicided source/drain regions and the channel region which includes a selectively plated metallic or intermetallic material. By "low-resistance" it is meant a connection that has a resistivity on the order of less than 50 ohms/square, with about 2 to about 30 ohms/square being more typical. In the prior art, the resistance is typically about 50 to about 500 ohms/square, thus the present invention represents an improvement over prior art structures. [0014] In general terms, the semiconductor structure comprises: [0015] a semiconductor substrate including source/drain extension regions and a channel region located between said source/drain extension regions; [0016] a gate dielectric and a gate conductor located above the channel region and positioned on a surface of said semiconductor substrate, said gate dielectric and said gate conductor having vertical edges that are covered by an offset spacer; and [0017] silicide source/drain contacts, wherein said silicide source/drain contacts are spaced apart from said channel region by a metallic or intermetallic material that is located on the surface of said semiconductor substrate including said source/drain extension regions. [0018] The term "silicided source/drain contacts" is used herein to denote the portions of the source/drain regions that have been silicided by a conventional salicidation process. BRIEF DESCRIPTION OF THE DRAWINGS [0019] FIG. 1 is a pictorial representation (through a cross sectional view) depicting an initial MOS structure that is used in the present invention. Continue reading... Full patent description for Structure for uniform triggering of multifinger semiconductor devices with tunable trigger voltage Brief Patent Description - Full Patent Description - Patent Application Claims Click on the above for other options relating to this Structure for uniform triggering of multifinger semiconductor devices with tunable trigger voltage patent application. ###  How KEYWORD MONITOR works... a FREE service from FreshPatents1. Sign up (takes 30 seconds). 2. Fill in the keywords to be monitored. 3. Each week you receive an email with patent applications related to your keywords. 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