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  Structure and self-locating method of making capped chipsUSPTO Application #: 20070096312Title: Structure and self-locating method of making capped chips Abstract: A capped chip is provided in which a cap member has a bottom surface facing a front surface of the chip and a top surface opposite the front surface. A plurality of through holes is desirably provided in the cap member which extend from the bottom surface to the top surface. A plurality of metallic interconnects electrically connected to the chip are provided which project upwardly from the front surface of the chip at least partially through the through holes. Desirably, the metallic interconnects include stud bumps. (end of abstract) Agent: Tessera Lerner David Et Al. - Westfield, NJ, US Inventors: Giles Humpston, Belgacem Haba USPTO Applicaton #: 20070096312 - Class: 257734000 (USPTO) Related Patent Categories: Active Solid-state Devices (e.g., Transistors, Solid-state Diodes), Combined With Electrical Contact Or Lead The Patent Description & Claims data below is from USPTO Patent Application 20070096312. Brief Patent Description - Full Patent Description - Patent Application Claims
[0001] This application is a division of U.S. application Ser. No. 10/949,575 filed Sep. 24, 2004. Said application Ser. No. 10/949,575 claims the benefit of the filing dates of U.S. Provisional Patent Application Nos. 60/506,500 filed Sep. 26, 2003, Ser. No. 60/515,615 filed Oct. 29, 2003, Ser. No. 60/532,341 filed Dec. 23, 2003, Ser. No. 60/568,041 filed May 4, 2004, Ser. No. 60/574,523 filed May 26, 2004, and is a continuation-in-part of U.S. patent application Ser. No. 10/928,839, filed Aug. 27, 2004, the disclosures of all such applications being hereby incorporated herein by reference. BACKGROUND OF THE INVENTION [0002] The present invention relates to microelectronic packaging. Microelectronic chips typically are thin, flat bodies with oppositely facing, generally planar front and rear surfaces and with edges extending between these surfaces. Chips generally have contacts on the front surface, which are electrically connected to the circuits within the chip. Certain chips require a protective element, referred to herein as a cap or lid, over all or part of the front surface. For example, chips referred to as surface acoustic wave or "SAW" chips incorporate acoustically-active regions on their front surfaces, which must be protected from physical and chemical damage by a cap. Microelectromechanical or "MEMS" chips include microscopic electromechanical devices, e.g., acoustic transducers such as microphones, which must be covered by a cap. The caps used for MEMS and SAW chips must be spaced from the front surface of the chip to-an open gas-filled or vacuum void beneath the cap in the active area, so that the cap does not touch the acoustical or mechanical elements. Certain electro-optical chips such as optical sensing chips and light-emitting chips have photosensitive elements which also must be protected by a lid. Voltage controlled oscillators (VCOs) sometimes also require a cap to be placed over the active area. [0003] Miniature SAW devices can be made in the form of a wafer formed from or incorporating an acoustically active material such as lithium niobate or lithium tantalate material. The wafer is treated to form a large number of SAW devices, and typically also is provided with electrically conductive contacts used to make electrical connections between the SAW device and other circuit elements. After such treatment, the wafer is severed to provide individual devices. SAW devices fabricated in wafer form can be provided with caps while still in wafer form, prior to severing. For example, as disclosed in U.S. Pat. No. 6,429,511 a cover wafer formed from a material such as silicon can be treated to form a large number of hollow projections and then bonded to the top surface of the active material wafer, with the hollow projections facing toward the active wafer. After bonding, the cover wafer is polished to remove the material of the cover wafer down to the projections. This leaves the projections in place as caps on the active material wafer, and thus forms a composite wafer with the active region of each SAW device covered by a cap. [0004] Such a composite wafer can be severed to form individual units. The units obtained by severing such a wafer can be mounted on a substrate such as a chip carrier or circuit panel and electrically connected to conductors on the substrate by wire-bonding to the contacts on the active wafer after mounting, but this requires that the caps have holes of a size sufficient to accommodate the wire bonding process. This increases the area of the active wafer required to form each unit, requires additional operations and results in an assembly considerably larger than the unit itself. [0005] In another alternative disclosed by the '511 patent, terminals can be formed on the top surfaces of the caps and electrically connected to the contacts on the active wafer prior to severance as, for example, by metallic vias formed in the cover wafer prior to assembly. However, formation of terminals on the caps and vias for connecting the terminals to the contacts on the active wafer requires a relatively complex series of steps. Similar problems occur in providing terminals for MEMS devices. For these and other reasons, further improvements in processes and structures for packaging SAW, MEMS, electro-optical and other capped devices would be desirable. SUMMARY OF THE INVENTION [0006] As used herein in relation to a cap and cap wafer and a lid and lid wafer, the term "top surface" refers to an outer surface of the cap, and the term "bottom surface" refers to an inner surface of the cap, the inner and outer surfaces of the cap relating to the form in which the cap is joined to the chip. Stated another way, the outer surface of the cap faces away from the front, i.e., the contact-bearing surface of the chip, while the inner surface of the cap faces towards the front or contact-bearing surface of the chip. The outer surface of the cap is referred to as the top surface, and the inner surface of the cap is referred to as the bottom surface, even if the capped chip structure including both chip and cap is turned over and mounted, such that the top surface faces downwardly and is joined to another article, such as a printed circuit panel. [0007] According to an aspect of the invention, a capped chip is provided which includes a chip having an upwardly facing front surface and a plurality of bond pads exposed in a bond pad region at the front surface. A cap member having a top surface, a bottom surface opposite the top surface, and a plurality of through holes extending between the top and bottom surfaces, is mounted to the chip such that the bottom surface faces the front surface of the chip and is spaced therefrom to define a void. A plurality of solid electrically conductive interconnects extend from the bond pads at least partially through the through holes to form seals extending across the through holes. [0008] An assembly including a capped chip according to a preferred aspect of the invention further includes a circuit panel having a plurality of terminals, wherein the interconnects are joined to the terminals of the circuit panel. [0009] According to a particular preferred aspect of the invention, the interconnects may include a fusible conductive material joined to the bond pads. Wettable regions are desirably provided on sidewalls of the through holes, the fusible material contacting the wettable regions. The fusible conductive material may include at least one of a solder, tin, or eutectic composition, and the through holes have a substantially frusto-conical shape. [0010] According to a particular preferred aspect of the invention, a seal disposed between the bottom surface of the cap member and a portion of the front surface of the chip, the seal at least substantially enclosing the bond pad region and the void. The chip preferably includes an active area and the through holes are disposed between the seal and the active area such that the seal and the interconnects seal the active area within the void. In one embodiment, the interconnects include a fusible material and an attach temperature of a sealing material of the seal coincides with a reflowing temperature for the fusible material. [0011] In an embodiment, the bottom surface of the cap member includes a stop, the stop being engaged with the front surface of the active chip to control a spacing between the cap member and the chip. A sealing material of the seal is preferably disposed in contact with the stop and with the front surface of the chip such that the cap member is sealed to the chip at the stop. Illustratively, the stop includes a knife-edge and the seal includes a material such as a thermoplastic, adhesive, low melting point glass, solder or eutectic composition. In one embodiment, the seal is diffusion bonded to at least one of the chip and the cap member. [0012] In a particular embodiment, the seal includes spacing elements, such that the front surface of the chip and the bottom surface of the cap member are spaced by no less than a width of the spacing elements. The cap member preferably includes at least one material selected from the group consisting of ceramics, metals, glasses, and semiconductor materials. In a highly preferred embodiment, the cap member consists essentially of a material having a coefficient of thermal expansion (CTE) closely matched to a CTE of the chip. Such chip may include a surface acoustic wave (SAW) device exposed at the front surface and the cap member includes a material having a CTE, which is closely matched to a CTE of the SAW device. In a specific embodiment, the SAW device includes a component consisting essentially of lithium tantalate, and the cap member includes a layer of aluminum and a layer of aluminum oxide overlying the layer of aluminum. In such embodiment, the cap member may include a metal layer and an oxide layer overlying the metal layer, the oxide layer including an oxide of a metal of the metal layer, wherein the oxide layer lines the through holes. The material of the cap member may further include one or more nickel alloys. [0013] Preferably, through holes of the cap are metallized with two or more layers of metal disposed on sidewalls thereof. The layers of metal desirably include a layer consisting essentially of titanium contacting the sidewall of the through hole, a layer consisting essentially of platinum contacting the titanium layer, and an exposed layer consisting essentially of gold contacting the platinum layer. Such metallization is a preferred example of a broader class of metallization schemes colloquially referred to as "under bump metallizations" ("UBMs"), a UBM typically being applied to form a bondable surface on a larger surface, prior to applying a molten fusible conductive material thereto, such as a solder mass. [0014] According to another preferred aspect of the invention, the chip includes a rear surface opposite the front surface and peripheral edges extending between the front and rear surfaces, and the cap member includes peripheral edges disposed between the bottom surface and the top surface, wherein the chip further comprises an additional seal sealing at least the peripheral edges of the cap member to the peripheral edges of the chip. [0015] According to yet another preferred aspect, the cap member includes a dielectric layer having an inner surface and an outer surface, a ground layer disposed on at least the inner outer surface and at least one trace extending along the outer surface from the interconnect. [0016] In a particular embodiment, the interconnects of the capped chip include stud bumps in conductive communication with the bond pads, and the stud bumps extend at least partially through the through holes. Contacts at the top surface of the cap member are disposed in conductive communication with the stud bumps. [0017] In one embodiment, some of the stud bumps have shoulders abutting the bottom surface of the cap member, whereby the spacing between the bottom surface and the cap member is determined by the shoulders. [0018] In another particular embodiment of the invention, the through holes are tapered, becoming smaller in a direction from the top surface towards the bottom surface. [0019] In a preferred embodiment, the interconnects include at least one conductive trace extending horizontally along the top surface of the cap member. The interconnects may further include one or more contacts in conductive communication with the at least one conductive trace. [0020] According to another aspect of the invention, a capped chip is provided which includes a chip having a front surface, and a plurality of bond pads exposed at the front surface. The cap member has a top surface, a bottom surface opposite the top surface, and a plurality of through holes which extend between the top and bottom surfaces. The cap member is mounted to the chip such that the bottom surface faces the chip and is spaced therefrom to define a void. In such capped chip, a plurality of electrically conductive interconnects extend from the bond pads at least partially through the through holes. The interconnects including a flowable conductive material that extends at least partially through the through holes. [0021] Preferably, the flowable conductive material extends from the bond pads through the holes. As in the above aspect of the invention, a seal preferably extends between the chip and the cap member, the seal surrounding at least some or all of the interconnects, and the flowable conductive material sealing the through holes. In one embodiment, the seal includes a flowable conductive material of the same composition as the interconnects. [0022] According to a preferred aspect of the invention, the flowable conductive material wets portions of the cap member surrounding the through holes. In a particular embodiment, the cap member defines walls extending from the top surface to the bottom surface, the walls surrounding each of the through holes and the flowable conductive material wets the walls. When the cap member includes a structural material not wettable by the flowable conductive material, the cap may include liners formed from a material wettable by the flowable conductive material covering the walls. In a preferred embodiment, the flowable conductive material is a solder. Continue reading... Full patent description for Structure and self-locating method of making capped chips Brief Patent Description - Full Patent Description - Patent Application Claims Click on the above for other options relating to this Structure and self-locating method of making capped chips patent application. ###  How KEYWORD MONITOR works... a FREE service from FreshPatents1. Sign up (takes 30 seconds). 2. Fill in the keywords to be monitored. 3. Each week you receive an email with patent applications related to your keywords. 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