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Structure and method to optimize strain in cmosfetsRelated Patent Categories: Semiconductor Device Manufacturing: Process, Making Field Effect Device Having Pair Of Active Regions Separated By Gate Structure By Formation Or Alteration Of Semiconductive Active Regions, Having Insulated Gate (e.g., Igfet, Misfet, Mosfet, Etc.), Complementary Insulated Gate Field Effect Transistors (i.e., Cmos)Structure and method to optimize strain in cmosfets description/claimsThe Patent Description & Claims data below is from USPTO Patent Application 20080070357, Structure and method to optimize strain in cmosfets. Brief Patent Description - Full Patent Description - Patent Application Claims
RELATED APPLICATIONS [0001] This application is a divisional of U.S. Ser. No. 10/905,745, filed Jan. 19, 2005. BACKGROUND OF THE INVENTION Field of the Invention [0002] The present invention relates generally to a semiconductor structure of strained complementary metal oxide semiconductor field effect transistors (CMOSFETs), and a method for fabricating strained MOSFETs that optimizes strain in the MOSFETs, and more particularly pertains to a structure and method that maximizes the strain in one type/kind (N or P) of MOSFET and minimizes and relaxes the strain in another type/kind (P or N) of MOSFET. [0003] Process induced strain has attracted a great deal of attention recently because the strain can enhance the carrier mobility in the channel of a MOSFET. Contact barrier (CA) nitride stress engineering is especially effective in transferring strain into the channel of a MOSFET. Moreover, the process is compatible with and can be easily implemented in the current manufacturing process. The strain in the channel of a MOSFET is proportional to the thickness of the contact barrier (CA) nitride, with a thicker CA nitride causing higher stress in the channel of the MOSFET. Either compressive CA nitride or tensile CA nitride can improve the performance of one kind of MOSFET and degrade the performance of another kind of MOSFET. More specifically, compressive CA nitride improves the performance of PMOSFETs while it degrades the performance of NMOSFETs, and tensile CA nitride improves the performance of NMOSFETs while it degrades the performance of PMOSFETs. The compressive nitride film or tensile nitride film can be selectively deposited by changing the power of the plasma deposition, as is known in the art. [0004] Masked (blocked PFET or blocked NFET) Ge or As implants have been implemented to relax the stress in one kind (N or P) of MOSFET to reduce the degradation while maintaining the strain in another kind (P or N) of MOSFET. A thick CA nitride can cause higher stress in the channel of one kind (N or P) of MOSFET. However, a thick CA nitride makes it harder to relax the stress with Ge or As implants to improve the performance of the other kind (P or N) MOSFET. SUMMARY OF THE INVENTION [0005] The present invention provides a structure and method to optimize strain in semiconductor devices such as CMOSFETs and has broad applicability to semiconductor devices in general. The subject invention provides a strained semiconductor structure comprising both PMOSFETs and NMOSFETS, and a method for fabricating strained MOSFETs that maximizes the strain in one type/kind (P or N) of MOSFET and minimizes and relaxes the strain in another type/kind (N or P) of MOSFET. [0006] A strain inducing CA nitride coating having an original full thickness is formed over one of the PMOSFET and the NMOSFET, wherein the strain inducing coating produces an optimized full strain in the one semiconductor device. A strain inducing CA nitride coating having an etched reduced thickness, less than the full thickness, is formed over the other of the PMOSFET and the NMOSFET, wherein the reduced thickness of the strain inducing coating relaxes and produces less strain in the other MOSFET. BRIEF DESCRIPTION OF THE DRAWINGS [0007] The foregoing objects and advantages of the present invention for structure and method to optimize strain in MOSFETs may be more readily understood by one skilled in the art with reference being had to the following detailed description of several embodiments thereof, taken in conjunction with the accompanying drawings wherein like elements are designated by identical reference numerals throughout the several views, and in which: [0008] FIG. 1 illustrates a MOSFET structure having a greater thickness of CA compressive nitride on a PMOSFET that maximizes the strain in the PMOSFET and a lesser thickness of CA compressive nitride on an NMOSFET that minimizes and relaxes the strain in the NMOSFET. [0009] FIG. 2 illustrates a MOSFET structure having a greater thickness of CA tensile nitride on an NMOSFET that maximizes the strain in the NMOSFET and a lesser thickness of CA tensile nitride on a PMOSFET that minimizes and relaxes the strain in the PMOSFET. DETAILED DESCRIPTION OF THE INVENTION [0010] The present invention provides a MOSFET structure with different thicknesses of contact barrier (CA) nitride on NMOSFETs and PMOSFETs that maximizes the strain in one type/kind (P or N) of MOSFET and minimizes and relaxes the strain in another type/kind (Nor P) of MOSFET. [0011] FIG. 1 illustrates first and second exemplary embodiments of the present invention on a semiconductor wafer having both PMOSFETs 30 and NMOSFETs 32 separated by isolation regions 34. In the first and second exemplary embodiments of the present invention, compressive CA nitride is used to maximize the strain in the PMOSFETs 30 and minimize and relax the strain in the NMOSFETs 32. [0012] In summary, after deposition of a thick (700-1000 A) compressive CA nitride 36 on both the PMOSFETs 30 and the NMOSFETs 32, the wafer is patterned with photoresist such that the PMOSFETs 30 are covered by photoresist and the NMOSFETs 32 are exposed and not covered by photoresist. The CA nitride at the NMOSFETs 32 is etched thinner at 38 to (300-500 A), while the photoresist protects the PMOSFETs 30 from the etch. Therefore, the thinner CA nitride 38 at the NMOSFETs 32 results in less compressive strain at the NMOSFETs 32 than at the PMOSFETs 30, and the NMOSFETs 32 degradation is reduced. FIG. 1 also illustrates that a Ge or As implant 40 can be applied to further relax the strain and improve the NMOSFETs 32 performance. [0013] In a first step, a thick (700-1000 A) layer of compressive CA nitride 36 is deposited on both the PMOSFETs 30 and the NMOSFETs 32 on a wafer. [0014] A blanket layer of photoresist is then deposited over the wafer, and the photoresist is then patterned by using a mask such that the PMOSFETs 30 are covered by photoresist while the NMOSFETs 32 remain exposed and are not covered by the photoresist. [0015] The CA nitride at the NMOSFETs 32 is then etched thinner to (300-500 A) at 38, while the photoresist protects the CA nitride at the PMOSFETs 30 from the etch such that the CA nitride 36 on top of the PMOSFETs 30 remains at the full deposited thickness. Therefore, the thinner CA nitride at 38 on top of the NMOSFETs 32 results in less compressive strain at the NMOSFETs 32 than at the PMOSFETs 30, and the degradation of the NMOSFETs 32 caused by the compressive CA nitride is reduced. [0016] The first embodiment of the present invention is completed with the completion of the above steps. FIG. 1 also illustrates a second embodiment wherein, after completion of the above steps, the NMOSFETs 32 degradation is further reduced by implanting at 40 Ge or As into the NMOSFETs 32. The implant 40 is performed while the PMOSFETs 30 are blocked with a mask, (indicated in the drawing by +B (block) P (PFETs) Ge/As implant 40), which can be the same mask used to pattern the photoresist, to further relax the strain and improve the performance of the NMOSFETs 32. [0017] FIG. 2 illustrates third and fourth exemplary embodiments of the present invention which show that the same structure and method of FIG. 1 can be applied to tensile CA nitride. In summary, after deposition of a thick (700-1000 A) tensile CA nitride 42 on both the NMOSFETs 32 and the PMOSFETs 30, the wafer is patterned with photoresist such that the NMOSFETs 32 are covered by photoresist while the PMOSFETs 30 are exposed and not covered by photoresist. The CA nitride at the PMOSFETs 30 is etched thinner at 44 to (300-500 A), while the photoresist protects the NMOSFETs 32 from the etch. Therefore, the thinner CA nitride 44 at the PMOSFETs 30 results in less compressive strain at the PMOSFETs 30 than at the NMOSFETs 32, and the PMOSFETs 30 degradation is reduced. FIG. 2 also illustrates at 46 that a Ge or As implant can be applied to further relax the strain and improve the PMOSFETs 30 performance. [0018] In a first step a thick (700-1000 A) layer of tensile CA nitride 42 is deposited on both the PMOSFETs 30 and the NMOSFETs 32 on the wafer. Continue reading about Structure and method to optimize strain in cmosfets... Full patent description for Structure and method to optimize strain in cmosfets Brief Patent Description - Full Patent Description - Patent Application Claims Click on the above for other options relating to this Structure and method to optimize strain in cmosfets patent application. ###  How KEYWORD MONITOR works... a FREE service from FreshPatents1. Sign up (takes 30 seconds). 2. Fill in the keywords to be monitored. 3. Each week you receive an email with patent applications related to your keywords. Start now! - Receive info on patent apps like Structure and method to optimize strain in cmosfets or other areas of interest. ### Previous Patent Application: Trench replacement gate process for transistors having elevated source and drain regions Next Patent Application: Semiconductor device Industry Class: Semiconductor device manufacturing: process ### FreshPatents.com Support Thank you for viewing the Structure and method to optimize strain in cmosfets patent info. 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