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Structure and method to induce strain in a semiconductor device channel with stressed film under the gateRelated Patent Categories: Active Solid-state Devices (e.g., Transistors, Solid-state Diodes), Field Effect Device, Having Insulated Electrode (e.g., Mosfet, Mos Diode), Insulated Gate Field Effect Transistor In Integrated Circuit, Complementary Insulated Gate Field Effect TransistorsStructure and method to induce strain in a semiconductor device channel with stressed film under the gate description/claimsThe Patent Description & Claims data below is from USPTO Patent Application 20070187773, Structure and method to induce strain in a semiconductor device channel with stressed film under the gate. Brief Patent Description - Full Patent Description - Patent Application Claims
CROSS REFERENCE TO RELATED APPLICATIONS [0001] This application is a divisional application of copending U.S. patent application Ser. No. 10/906,054 filed on Feb. 1, 2005, the contents of which are incorporated by reference in their entirety. BACKGROUND OF THE INVENTION Field of the Invention [0002] The invention relates to CMOS devices and method of manufacture and more particularly to CMOS devices with stressed channels and method of manufacture. [0003] Metal-oxide semiconductor transistors generally include a substrate made of a semiconductor material, such as silicon. The transistors also typically include a source region, a channel region and a drain region within the substrate. The channel region is located between the source and the drain regions. A gate stack, which usually includes a conductive material gate or gate conductor on top of a gate oxide layer and sidewall spacers, is generally provided above the channel region. More particularly, the gate oxide layer is typically provided on the substrate over the channel region, while the gate conductor is provided above the gate oxide layer. The sidewall spacers help define locations of source and drain ion implantation and form self-aligned silicide. [0004] It is known that the amount of current flowing through a channel of a semiconductor device which has a given electric field across it is proportional to the mobility of the carriers in the channel. Thus, by increasing the mobility of the carriers in the channel, the operation speed of the transistor can be increased. [0005] It is further known that mechanical stresses within a semiconductor device substrate can modulate device performance by, for example, increasing the mobility of the carriers in the semiconductor device. The mechanical stress can be induced by STI, gate spacer, an etch stopping layer or by silicide. So, certain types of stresses within a semiconductor device are known to enhance semiconductor device characteristics. Thus, to improve the characteristics of a semiconductor device, tensile and/or compressive stresses may be created in the channel of the n-type devices (e.g., nFETs) and/or p-type devices (e.g., pFETs). It should be noted that the same stress component, for example tensile stress or compressive stress, improves the device characteristics of one type of device (i.e., n-type device or p-type device) while negatively affecting the characteristics of the other type device. [0006] For example, tensile stress along the channel direction increases electron mobility in an nFET device while decreasing hole mobility in a pFET. On the other hand, tensile stress perpendicular to the gate oxide surface degrades nFET performance, but improves pFET performance. [0007] One method of creating stress in the channel of a CMOS device includes forming a film of stressed material over the CMOS device. Thus, some of the stress in the stressed film is coupled to the substrate of the CMOS device thereby generating stress in the channel of the CMOS device. Because the enhanced carrier mobility due to mechanical stress is proportional to the amount of stress, it is desirable to create as much stress in the channel as possible. Additionally, stresses in the stressed film are generated due to appropriately adjusting characteristics in the stressed film deposition process, or introducing stress-producing dopants into the stressed film. It should be noted that such methods of producing a stressed film are limited to producing a stress film with an internal stress on the order of a couple of GigaPascal (GPa). [0008] Consequently, with the maximum stress of a stressed film being limited to a couple of GPa, it is desirable to develop improved methods and structures for coupling the stress in a stressed film into the channel region of a CMOS device to increase the amount of stress in the channel. SUMMARY OF THE INVENTION [0009] In first aspect of the invention, a method of making a CMOS device with a stressed channel includes forming a silicon island comprising a top surface and a sidewall, and arranging an oxide gate on the top surface and above a sidewall of the silicon island. The method also includes arranging a stress film below the gate oxide and adjacent a sidewall of the silicon island. [0010] In another aspect of the invention, a method of making a CMOS device with a stressed channel includes forming a silicon island comprising a top surface and multiple sidewalls, and arranging a gate oxide and gate stack on the top surface and above a sidewall of the silicon island. The method also includes surrounding a portion of the silicon island around the multiple sidewalls with a stress film. [0011] In another aspect of the invention, a CMOS device with a stressed channel includes a silicon island comprising a top surface and a sidewall, and a gate oxide and gate stack arranged on the top surface and above a sidewall of the silicon island. The CMOS device also includes a stress film arranged below the gate oxide and adjacent a sidewall of the silicon island. BRIEF DESCRIPTION OF THE DRAWINGS [0012] FIGS. 1-2 illustrate steps in fabricating a semiconductor device in accordance with the invention; [0013] FIG. 3 illustrates a top view of a semiconductor device in accordance with the invention; [0014] FIGS. 4-10 illustrate steps in fabricating a semiconductor device in accordance with the invention; and [0015] FIG. 11 is a graph of stress versus distance in a semiconductor device in accordance with the invention. DETAILED DESCRIPTION OF EMBODIMENTS OF THE INVENTION [0016] The invention reduces the electrical resistance of a channel in a semiconductor device which causes an increase in device operation speed. The invention also enhances stress in a channel of a semiconductor device by applying stress to the channel. Consequently, the invention applies stress to a channel with a stress film deposited either partially or completely under the gate. Accordingly, some embodiments of the invention completely surround the semiconductor device channel continuously on all sides thereby enhancing the amount of stress applied to the channel. The invention additionally allows for reducing the resistance of a channel in a semiconductor device by increasing the mobility of carriers or holes. Accordingly, the invention allows for producing semiconductor channels having higher stress levels and a correspondingly higher frequency or current response. [0017] In one embodiment, the invention creates a unique structure so that high stressed silicon nitride film is introduced to the bottom part of the gate in the STI oxide region. Oxide is recessed so that, for example, Si.sub.3N.sub.4, can be deposited partially or completely under the gate. Additionally, the invention can induce strain in the adjacent channel region, which is especially effective for narrow width transistors. [0018] Referring to FIG. 1, a silicon substrate 10 has a trench 12 formed therein. The trench 12 may be formed by any of the processes well known in the art for forming a trench in a silicon substrate such as, for example, a dry etch process. Continue reading about Structure and method to induce strain in a semiconductor device channel with stressed film under the gate... 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