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  Structure and method of three dimensional hybrid orientation technologyUSPTO Application #: 20070224754Title: Structure and method of three dimensional hybrid orientation technology Abstract: A method and device for increasing pFET performance without degradation of nFET performance. The method includes forming a first structure on a substrate using a first plane and direction and forming a second structure on the substrate using a second plane and direction. In use, the device includes a nFET stack on a substrate using a first plane and direction, e.g., (100)<110> and a pFET stack on the substrate using a second plane and direction, e.g., (111)/<112>. An isolation region within the substrate is provided between the nFET stack and the pFET stack. (end of abstract) Agent: Greenblum & Bernstein, P.L.C - Reston, VA, US Inventor: Oh-jung KWON USPTO Applicaton #: 20070224754 - Class: 438224000 (USPTO) Related Patent Categories: Semiconductor Device Manufacturing: Process, Making Field Effect Device Having Pair Of Active Regions Separated By Gate Structure By Formation Or Alteration Of Semiconductive Active Regions, Having Insulated Gate (e.g., Igfet, Misfet, Mosfet, Etc.), Complementary Insulated Gate Field Effect Transistors (i.e., Cmos), Including Isolation Structure, Dielectric Isolation Formed By Grooving And Refilling With Dielectric Material, Having Well Structure Of Opposite Conductivity Type, The Patent Description & Claims data below is from USPTO Patent Application 20070224754. Brief Patent Description - Full Patent Description - Patent Application Claims
CROSS REFERENCE TO RELATED APPLICATIONS [0001] This application is a divisional of U.S. patent application Ser. No. 10/907,622, filed Apr. 8, 2005, the disclosure of which is expressly incorporated by reference herein in its entirety. BACKGROUND OF THE INVENTION [0002] 1. Field of the Invention [0003] The invention relates to semiconductor devices, and more particularly to semiconductor devices having increased pFET performance without degradation of the nFET performance and a method of manufacture. [0004] 2. Background Description [0005] Field effect transistors (FET's) are a fundamental building block in the field of integrated circuits. FET's can be classified into two basic structural types: horizontal and vertical. Horizontal, or lateral, FET's exhibit carrier flow from source to drain in a direction parallel (e.g., horizontal) to the plane of the substrate and vertical FET's exhibit carrier flow from source to drain in a direction transverse to the plane of the substrate (e.g., vertical) on which they are formed. FET structures may include a single gate (e.g., for forming a single channel) or a pair of gates (e.g., for forming a pair of channels), with double-gate versions providing an advantage of an increased current carrying capacity (e.g. typically greater than twofold over the single-gate versions). [0006] A FET typically consists of source and drain electrodes interconnected by semiconductor material. Conduction between the drain and source electrodes occurs basically within the semiconductor, and the length between the source and drain is the conduction channel. In particular, the output current is inversely proportional to the channel length, while the operating frequency is inversely proportional to the square of the channel length. [0007] The basic metal-oxide-semiconductor field-effect transistor (MOSFET) structure has a so-called "flat design". A nFET structure is a four-terminal device and consists of a p-type semiconductor substrate, into which two n-regions, a source electrode and drain electrode are formed (e.g., by ion implantation). The metal contact on the insulator is a gate. Heavily doped polysilicon or a combination of silicide and polysilicon can also be used as the gate electrode. [0008] The basic device parameters are the channel length L, which is the distance between the two metallurgical n-p junctions, the channel width W, the gate oxide thickness t, the junction depth, and the substrate doping. When voltage is applied to the gate, the source-to-drain electrodes correspond to two p-n junctions connected back to back. The only current that can flow from source to drain is the reverse leakage current. When a sufficiently positive bias is applied to the gate so that a surface inversion layer (or channel) is formed between the two n-regions, the source and the drain are connected by the conducting surface of the n-channel through which a current can flow. [0009] It is known, though, that the nFETs are optimized in the horizontal plane of the substrate. That is, the electron mobility across the channel is optimized when the nFET is fabricated on the 100 plane and the 110 direction. This is a typical flat structure fabrication. The pFET device, on the other hand, has significantly decreased performance characteristics when it is fabricated on the 100 plane and the 110 direction; namely, the hole mobility is significantly decreased, thereby degrading the performance of the entire device. However, it is typical in semiconductor fabrication to build both the nFET and pFET structures in the 100 plane and the 110 direction, using well-known processes. SUMMARY OF THE INVENTION [0010] In a first aspect of the invention, a method of fabricating a semiconductor structure comprising forming a first structure on a substrate using a first plane and direction and forming a second structure on the substrate using a second plane and direction. [0011] In another aspect of the invention, a method of manufacturing a semiconductor device comprising building a nFET stack on a substrate using a first plane and direction and building a pFET stack on the substrate using a second plane and direction, different from the first plane and first direction. The method further includes providing an isolation region within the substrate between the nFET stack and the pFET stack. [0012] In another aspect of the invention, a semiconductor structure includes a nFET stack on a substrate using a first plane and direction and a pFET stack on the substrate using a second plane and direction, different from the first plane and first direction. An isolation region within the substrate is provided between the nFET stack and the pFET BRIEF DESCRIPTION OF THE DRAWINGS [0013] FIGS. 1-15 illustrates steps in manufacturing a device in accordance with the invention; and [0014] FIG. 16 illustrates a final structure and manufacturing in accordance with the invention. DETAILED DESCRIPTION OF EMBODIMENTS OF THE INVENTION [0015] The invention is directed to semiconductor structures and more particularly to semiconductor structures and methods of manufacture using three dimensional hybrid orientation technologies. In one aspect of the invention, the performance of a pFET is improved or optimized by increasing carrier mobility for the pFET without any degradation in the performance of the nFET. To accomplish the invention, the nFET is formed in a first plane/direction and the pFET is formed in a second plane/direction using similar processing steps. For example, in one non-limiting aspect of the invention, the nFET will be formed in the (100)/<110> plane/direction and the pFET will be formed in the (111)/<112> plane/direction. In this manner, the channel length of the pFET may be longer than the channel length of nFET using the same processes. The invention is compatible with CMOS technologies such as, for example, SOI, strained Si, dual spacer and the like. [0016] FIG. 1 shows a beginning structure in accordance with the invention. In this structure, a shallow trench isolation structure (STI) 12 is formed in a substrate 10 having a (100) plane. In one exemplary illustration, the depth of the STI 12 is between 2000 .ANG.-5000 .ANG., depending on the required device performance. The depth of the STI 12 may be shallower in SOI process technologies. In the embodiment described herein, a nFET will be formed on one side of the STI 12 and a pFET will be formed on an opposing side of the STI 12. [0017] By an exemplary illustration, the STI 12 may be formed by depositing a pad oxide and pad nitride over the substrate 10. A photo mask or a hard mask is formed over the pad nitride and an etching process etches to the substrate through the formed layers. An additional etching process etches into the substrate to form the trench. An oxide, for example, is deposited in the trench to fill the trench. The surface is planarized using a chemical mechanical polishing (CMP) process. The pad nitride may then be removed, resulting in the structure of FIG. 1. [0018] FIG. 2 represents a well implantation process. In one implementation, the p-well is doped using boron, which later forms part of the nFET. The n-well may be doped with phosphorous, which later forms part of the pFET. The doping is performed using well-known processes in the industry. [0019] In FIG. 3, an oxide material 14 is formed over the substrate 10 using well-known processes such as, for example, thermal oxidation or chemical vapor deposition. In one aspect of the invention, the oxide layer 14 is approximately 10 .ANG. to 100 .ANG. in thickness; although other thickness or dimensions are contemplated by the invention. A block material 16 such as nitride is deposited over the oxide layer 14 using a CVD process, for example. The block material 16 may be in the range of 200 .ANG. to 2000 .ANG., although other thickness and dimensions are also contemplated for use with the invention. A photoresist 18 is deposited over the block material 16. After patterning, only pFET region is opened for subsequent anisotropic etching. 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