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Structure and method of making a semiconductor integrated circuit tolerant of mis-alignment of a metal contact patternRelated Patent Categories: Active Solid-state Devices (e.g., Transistors, Solid-state Diodes), Field Effect DeviceStructure and method of making a semiconductor integrated circuit tolerant of mis-alignment of a metal contact pattern description/claimsThe Patent Description & Claims data below is from USPTO Patent Application 20060118829, Structure and method of making a semiconductor integrated circuit tolerant of mis-alignment of a metal contact pattern. Brief Patent Description - Full Patent Description - Patent Application Claims
BACKGROUND OF THE INVENTION [0001] The present invention relates to the fabrication of semiconductor integrated circuits, and more specifically to a structure and method of making a semiconductor integrated circuit which is tolerant of mis-alignment of the metal contact pattern to the gate pattern. [0002] In a semiconductor integrated circuit, a metal contact such as tungsten is used to connect the transistor gate, source/drain, and body to backend wiring. A conventional method for forming a metal contact will be briefly explained. [0003] FIGS. 10 and 11 illustrate stages in conventional fabrication of a semiconductor integrated circuit. [0004] Referring to FIG. 10, a conventional method of forming a metal contact in a semiconductor integrated circuit includes a step of forming a gate stack 950 of a PFET 901 and a gate stack 960 of an NFET 903, on a substrate 900 which includes a silicon substrate 902, a buried oxide (BOX) layer 904 and a semiconductor layer 906. Then oxide spacers 972, 982 are formed on side walls of the gate stacks 950, 960 followed by formation of source drain (S/D) extensions 920, 922, 924, 926 in a semiconductor layer 906. Next, nitride spacers 974, 984 are formed on the oxide spacers 972, 982 respectively. Subsequently, S/D regions 912, 914, 916, 918 are formed. Further, using the nitride side walls 974, 984 as masks, metal silicide regions 932, 934, 936, 938 are formed on the S/D regions 912, 914, 916, 918, respectively. Next, a contact liner 988, commonly Si.sub.3N.sub.4, is deposited over the substrate 900, followed by deposition of an interlayer dielectric layer (IDL) 990 and planerization. Thereafter, photolithographic and etching techniques are used to pattern the IDL 990, forming contact openings 992, 994, 996, 998 that expose the silicide on the S/D regions as illustrated in FIG. 11. The process typically proceeds by a first anisotropic etch process to form openings in the interlayer dielectric 990 stopping on the contact liner 988, followed by a second anisotropic etch through the contact liner 988, using the silicide 932, 934, 936, 938 as an etching stop. [0005] In the photolithography, the pattern for the contact openings is inevitably slightly mis-aligned to the gate pattern. Thus, at least a portion of a contact opening may be mis-aligned over the side walls 974, 984. However, the etch process designed to etch away the contact liner 988, typically nitride, has no selectivity to the spacer 974, 984, which is also typically nitride. Therefore, at least a part of the spacers 974, 978 may be etched through, exposing the underlying semiconductor layer 906. Since the silicide 932, 934, 936, 938 on the S/D regions 912, 914, 916, 918 are formed by using the side walls 974, 984, as masks, no silicide is deposited beneath the spacers 974, 984 in the semiconductor layer 906. Accordingly, the exposed portion of the substrate may be etched, causing problems such as a short 993, 997 between a metal contact and the substrate, and causing unexpected parasitic capacitance. [0006] Further occasionally the semiconductor layer 906 is exposed between the bottom of the spacers 974, 984 and the edges 931, 933, 935, 937 of the silicide 932, 934, 936, 938 even though the spacers 974, 984 are used as masks in forming silicide 932, 934, 936, 938, increasing the possibility of causing a short between a metal contact and the substrate. [0007] Accordingly, there is a need for a structure and method of forming a metal contact that is tolerant of mis-alignment of the contact pattern to the gate pattern and avoids shorts between the contact and substrate. SUMMARY OF THE INVENTION [0008] According to an aspect of the invention, a method of fabricating a field effect transistor is provided. The method includes steps of forming a gate stack on a top surface of a semiconductor substrate and a first spacer formed on a sidewall of the gate stack; forming, in or on the semiconductor substrate, a silicide adjacent to the first spacer; forming a second spacer covering the surface of the first spacer; forming a contact liner over at least the gate stack, the second spacer and the silicide; forming an interlayer dielectric over the contact liner; forming an opening to expose the contact liner over the silicide; and extending the opening through the contact liner to expose the silicide without exposing the substrate. [0009] In another aspect of the invention, the second spacer further covers at least a portion of the silicide so that the semiconductor layer is not exposed even if a gap between the second spacer and the silicide exists. [0010] These, and other aspects of the present invention will be better appreciated and understood when considered in conjunction with the following description and the accompanying drawings, which are not necessarily drawn to scale. BRIEF DESCRIPTION OF THE DRAWINGS [0011] FIGS. 1 through 7 illustrate stages in fabrication of a PFET and an NFET according to an embodiment of the invention. [0012] FIG. 8 illustrates a stage in fabrication of a PFET and an NFET according to another embodiment of the invention. [0013] FIG. 9 shows a flow of method for fabricating a semiconductor circuit according to an embodiment of the invention. [0014] FIGS. 10 and 11 illustrate conventional stages in fabrication of a PFET and an NFET. DETAILED DESCRIPTION [0015] FIGS. 1 through 7 illustrate stages in processing to form a PFET 101 and an NFET 103 according to an embodiment of the invention. [0016] Firstly, as shown in FIG. 1, a PFET 101 and an NFET 103 are formed on a substrate 100. The substrate 100 preferably includes a silicon substrate 102, buried oxide (BOX) layer 104, a semiconductor layer 106 and a trench isolation region 140. Alternatively, the substrate 100 may be a bulk semiconductor substrate such as silicon. However, the invention is not limited to silicon substrates but other types of semiconductors such as III-V compound semiconductor materials, e.g. gallium arsenide (GaAs), may be used. [0017] The PFET 101 and NFET 103 include gate stacks 150, 160, channel regions 108, 110, source drain extensions 120, 122, 124, 126, S/D regions 112, 114, 116, 118, silicide S/D regions (hereinafter "silicide") 132, 134, 136, 138 in the S/D regions respectively. The silicide may include, for example, titanium (Ti), cobalt (Co), Nickel (Ni), tungsten (W) or platinum (Pt). The gate stacks 150, 160 may further include gate dielectric layers 152, 162 on the channel regions 108, 110, and gate conductor portions 154, 164, such as polysilicon. Metal lower resistance portions 156, 166 may also be included in some embodiment. [0018] Adjacent the side walls of the gate stacks 150, 160, multiple spacers 172, 174, 182, 184 are preferably formed. Alternatively, a single spacer may be deposited on the side walls of each gate stack 150, 160. The spacers 174, 178 preferably include silicon nitride (Si.sub.3N.sub.4). The spacers 174, 178 are used as masks in the formation of the silicide 132, 134, 136, 138 in the S/D regions 112, 114, 116, 118. [0019] The S/D regions 112, 114, 116, 118 may be raised S/D regions, which may be formed by selective epitaxial growth. [0020] The silicide 132, 134, 136, 138 may be formed by a method such as chemical vapor deposition (CVD) of silicide, or metal sputtering followed by an anneal. Continue reading about Structure and method of making a semiconductor integrated circuit tolerant of mis-alignment of a metal contact pattern... Full patent description for Structure and method of making a semiconductor integrated circuit tolerant of mis-alignment of a metal contact pattern Brief Patent Description - Full Patent Description - Patent Application Claims Click on the above for other options relating to this Structure and method of making a semiconductor integrated circuit tolerant of mis-alignment of a metal contact pattern patent application. ###  How KEYWORD MONITOR works... a FREE service from FreshPatents1. Sign up (takes 30 seconds). 2. Fill in the keywords to be monitored. 3. Each week you receive an email with patent applications related to your keywords. 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