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  Structure and method for reliability evaluation of fcpbga substrates for high power semiconductor packaging applicationsUSPTO Application #: 20070202616Title: Structure and method for reliability evaluation of fcpbga substrates for high power semiconductor packaging applications Abstract: There is provided a method for measuring thermal properties of a semiconductor packaging material. The method includes incorporating at least one conducting feature into a substrate that includes the semiconductor packaging material, applying an electric current to the feature, and measuring a change in temperature of a region of the substrate around the feature as a result of the electric current. There is also provided a test vehicle for measuring thermal properties of a semiconductor packaging material. (end of abstract) Agent: Ohlandt, Greeley, Ruggiero & Perle, LLP - Stamford, CT, US Inventors: David J Russell, Ronald S Malfatt, Stefano S Oggioni, Jamil A Wakil USPTO Applicaton #: 20070202616 - Class: 438015000 (USPTO) Related Patent Categories: Semiconductor Device Manufacturing: Process, With Measuring Or Testing, Packaging (e.g., With Mounting, Encapsulating, Etc.) Or Treatment Of Packaged Semiconductor The Patent Description & Claims data below is from USPTO Patent Application 20070202616. Brief Patent Description - Full Patent Description - Patent Application Claims
BACKGROUND OF THE INVENTION [0001] 1. Field of the Invention [0002] The present invention relates to methods and devices for testing substrate materials, and more particularly, to methods and devices for testing semiconductor packaging materials. [0003] 2. Description of the Related Art [0004] The use of build-up organic substrates for semiconductor packaging, such as flip chip plastic ball grid array (FCPBGA), is increasing. One area in which FCPBGA is being applied is the area of high power processors. Typical applications for FCPBGA involve processor chips with a power requirement of 45 watts or less. Recent applications requiring chips up to 100 W, and applications under development requiring power in excess of 200 W, have raised concerns about the reliability of the organic build-up laminate substrates used for chip packaging. [0005] Typically thermal evaluations of high power chips are accomplished by fabricating high resistance heaters in the chip, so that a low amount of current can be used to power the heaters and thereby control the amount of heat generated by the chip. Such an approach does not satisfy the concerns raised for high power applications because the low amount of current needed to heat the chip is not representative of the currents that may pass through laminates of chips and interconnects in actual high power applications. [0006] Because of this use of chips in high power applications, there is a significant effort to cool chips and interconnects to a specified temperature, typically 85.degree. C. or lower. However, passing high current through fine conductive copper features in the laminate can potentially add more heat to the packaging laminate under the chip due to resistive heating. [0007] Therefore, there is a need to provide a device and method to determine effects on characteristics of substrates used in packaging high power chips. Such characteristics include additional heating occurring inside the organic packaging substrate as a result of resistive heating of the conductive features when high currents are passed through the conductive features. Other characteristics include the long term reliability of the organic laminate making up the packaging, as it is subjected to these high currents for extended periods of time, and the long term reliability effects of having the organic laminate subjected to repeated heating and cooling experienced during on-off power cycles. The present invention addresses these needs. SUMMARY OF THE INVENTION [0008] It is an object of the present invention to provide a device and method for evaluating high power semiconductor packaging. [0009] It is another object of the present invention to provide such a structure and method for measuring heating of a packaging substrate as a result of current applied to features in the substrate. [0010] It is a further object of the present invention to provide such a structure and method for measuring the long term reliability implications of heating of a packaging laminate over a period of time. [0011] It is still a further object of the present invention to provide such a structure and method for measuring the long term reliability implications of heating of a packaging laminate subject to repeated on-off power cycles. [0012] These and other objects of the present invention are achieved by a method for measuring thermal properties of a semiconductor packaging material. The method includes incorporating at least one conducting feature into a substrate that includes the semiconductor packaging material, applying an electric current to the feature, and measuring a change in temperature of a region of the substrate around the feature as a result of the electric current. The present invention also provides a test vehicle for measuring thermal properties of a semiconductor packaging material. BRIEF DESCRIPTION OF THE DRAWINGS [0013] FIG. 1 is a top and bottom view of an embodiment of a test vehicle 100. [0014] FIG. 2 is a cross section view of part of a flip chip ball grid array packaging assembly. [0015] FIG. 3A is a perspective view of an embodiment of the features and test measurement line of test vehicle 100. [0016] FIG. 3B is a close-up of a region 301 of the embodiment of test vehicle 100 shown in FIG. 3A. [0017] FIG. 3C is a close-up of a region 302 of the embodiment of test vehicle 100 shown in FIG. 3A. [0018] FIG. 3D is a schematic showing the temperature sensing lines as part of a four point probe testing system for power feeding the features and measuring temperature changes using a four probe microresistance measuring technique. [0019] Temperature sensing line 325, in one embodiment, is a component of a four-point probe used to measure changes in resistivity due to temperature changes in substrate 105 as a result of electric current applied to micro-vias 305. [0020] FIG. 4A is a perspective view of an embodiment of the features and test measurement line of test vehicle 100. [0021] FIG. 4B is a close-up of the embodiment of test vehicle 100 shown in FIG. 4A. Continue reading... Full patent description for Structure and method for reliability evaluation of fcpbga substrates for high power semiconductor packaging applications Brief Patent Description - Full Patent Description - Patent Application Claims Click on the above for other options relating to this Structure and method for reliability evaluation of fcpbga substrates for high power semiconductor packaging applications patent application. ###  How KEYWORD MONITOR works... a FREE service from FreshPatents1. Sign up (takes 30 seconds). 2. Fill in the keywords to be monitored. 3. Each week you receive an email with patent applications related to your keywords. Start now! - Receive info on patent apps like Structure and method for reliability evaluation of fcpbga substrates for high power semiconductor packaging applications or other areas of interest. ### Previous Patent Application: Plasma processing apparatus Next Patent Application: Method for fabricating stacked semiconductor components with through wire interconnects Industry Class: Semiconductor device manufacturing: process ### FreshPatents.com Support Thank you for viewing the Structure and method for reliability evaluation of fcpbga substrates for high power semiconductor packaging applications patent info. IP-related news and info Results in 2.18459 seconds Other interesting Feshpatents.com categories: Daimler Chrysler , DirecTV , Exxonmobil Chemical Company , Goodyear , Intel , Kyocera Wireless , |
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