| Structure and method for manufacturing planar strained si/sige substrate with multiple orientations and different stress levels -> Monitor Keywords |
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Structure and method for manufacturing planar strained si/sige substrate with multiple orientations and different stress levelsRelated Patent Categories: Active Solid-state Devices (e.g., Transistors, Solid-state Diodes), Field Effect Device, Having Insulated Electrode (e.g., Mosfet, Mos Diode), Single Crystal Semiconductor Layer On Insulating Substrate (soi)Structure and method for manufacturing planar strained si/sige substrate with multiple orientations and different stress levels description/claimsThe Patent Description & Claims data below is from USPTO Patent Application 20070170507, Structure and method for manufacturing planar strained si/sige substrate with multiple orientations and different stress levels. Brief Patent Description - Full Patent Description - Patent Application Claims
CROSS REFERENCE TO RELATED APPLICATIONS [0001] This application is a divisional application of U.S. Ser. No. 10/905,978, filed Jan. 28, 2005, which is related to co-assigned U.S. patent application Ser. No. 10/250,241 entitled HIGH PERFORMANCE SOI DEVICES ON HYBRID CRYSTAL-ORIENTATED SUBSTRATES, filed Jun. 17, 2003, now U.S. Patent Application Publication No. 2004-0256700, and co-assigned U.S. patent application Ser. No. 10/710,277 entitled STRUCTURE AND METHOD FOR MANUFACTURING PLANAR SOI SUBSTRATE WITH MULTIPLE ORIENTATIONS, filed Jun. 30, 2004, now U.S. Pat. No. 7,094,634, the entire content and subject matter of which are incorporated herein by reference. FIELD OF THE INVENTION [0002] The present invention relates to semiconductor materials having enhanced electron and hole mobilities, and more particularly, to semiconductor materials that include a silicon (Si)-containing layer having enhanced electron and hole mobilities. The present invention also provides methods for forming such semiconductor materials. BACKGROUND OF THE INVENTION [0003] For more than three decades, the continued miniaturization of silicon metal oxide semiconductor field effect transistors (MOSFETs) has driven the worldwide semiconductor industry. Various showstoppers to continued scaling have been predicated for decades, but a history of innovation has sustained Moore's Law in spite of many challenges. However, there are growing signs today that metal oxide semiconductor transistors are beginning to reach their traditional scaling limits. A concise summary of near-term and long-term challenges to continued CMOS scaling can be found in the "Grand Challenges" section of the 2002 Update of the International Technology Roadmap for Semiconductors (ITRS). A very thorough review of the device, material, circuit, and systems can be found in Proc. IEEE, Vol. 89, No. 3, March 2001, a special issue dedicated to the limits of semiconductor technology. [0004] Since it has become increasingly difficult to improve MOSFETs and therefore complementary metal oxide semiconductor (CMOS) performance through continued scaling, methods for improving performance without scaling have become critical. One approach for doing this is to increase carrier (electron and/or hole) mobilities. This can be done by either: (1) introducing the appropriate strain into the Si lattice; (2) by building MOSFETs on Si surfaces that are orientated in directions different than the conventional <100> Si; or (3) a combination of (1) and (2). [0005] As far as approach (1) is concerned, the application of stresses or strains changes the lattice dimensions of the Si-containing layer. By changing the lattice dimensions, the energy band gap of the material is changed as well. The change may only be slight in intrinsic semiconductors resulting in only a small change in resistance, but when the semiconducting material is doped, i.e., n-type, and partially ionized, a very small change in the energy bands can cause a large percentage change in the energy difference between the impurity levels and the band edge. Thus, the change in resistance of the material with stress is large. [0006] Prior attempts to provide strain-based improvements of semiconductor substrates have utilized etch stop liners or embedded SiGe structures. N-type channel field effect transistors (nFETs) need tension on the channel for strain-based device improvements, while p-type channel field effect transistors (pFETs) need a compressive stress on the channel for strain-based device improvements. [0007] In terms of approach (2), electrons are known to have a high mobility for a (100) Si surface orientation, but holes are known to have high mobility for a (110) surface orientation. That is, hole mobility values on (100) Si are roughly 2.times.-4.times. lower than the corresponding electron mobility for this crystallographic orientation. To compensate for this discrepancy, pFETs are typically designed with larger widths in order to balance pull-up currents against the nFET pull-down currents and achieve uniform circuit switching. NFETs having larger widths are undesirable since they take up a significant amount of chip area. [0008] On the other hand, hole mobilities on the (110) crystal plane of Si are approximately 2.times. higher than on the (100) crystal plane of Si; therefore, pFETs formed on a surface having a (100) crystal plane will exhibit significantly higher drive currents than pFETs formed on a surface having a (100) crystal plane. Unfortunately, electron Nobilities on the (110) crystal plane of Si are significantly degraded compared to the (100) crystal plane of Si. [0009] There is interest in integrating strained substrates having multiple crystallographic orientations with silicon-on-insulator (SOI) technology. SOI substrates reduce parasitic capacitance within the integrated circuit, reduce individual circuit loads and reduce the incidence of latch-up, thereby improving circuit and chip performance. [0010] In view of the state of the art mentioned above, there is a continued need for providing a strained Si/SiGe on insulator substrate with multiple crystallographic orientations and different stress levels. SUMMARY OF THE INVENTION [0011] One object of the present invention is to provide a multiple crystallographic orientation strained Si/SiGe-on-insulator (SGOI) substrate. [0012] Another object of the present invention is to provide a SGOI substrate that integrates strained silicon nFETs on a (100) crystal plane with strained silicon pFETs on a (110) crystal plane. [0013] These and other objects and advantages are achieved in the present invention by utilizing a method that provides a multiple orientation strained SCOI substrate including bonding, masking, etching and epitaxial regrowth process steps. Specifically, the method of the present invention comprises the steps of [0014] providing an initial structure having a first device region and a second device region positioned on and separated by an insulating material, said first device region comprising a first orientation material and said second device region comprising an insulating layer atop a second orientation material, wherein said first orientation material and said second orientation material have different crystallographic orientations; [0015] forming a first concentration of lattice modifying material atop said first orientation material; [0016] forming a protective layer atop said first concentration of lattice modifying material; [0017] removing said insulating layer atop said second orientation material; [0018] forming a second concentration of said lattice modifying material atop said second orientation material; [0019] removing said protective layer from said first concentration of lattice modifying material; [0020] intermixing said first concentration of lattice modifying material with said first orientation material to produce a first lattice dimension surface and said second concentration of lattice modifying material with said second orientation material to produce a second lattice dimension surface; and Continue reading about Structure and method for manufacturing planar strained si/sige substrate with multiple orientations and different stress levels... Full patent description for Structure and method for manufacturing planar strained si/sige substrate with multiple orientations and different stress levels Brief Patent Description - Full Patent Description - Patent Application Claims Click on the above for other options relating to this Structure and method for manufacturing planar strained si/sige substrate with multiple orientations and different stress levels patent application. ###  How KEYWORD MONITOR works... a FREE service from FreshPatents1. Sign up (takes 30 seconds). 2. Fill in the keywords to be monitored. 3. Each week you receive an email with patent applications related to your keywords. 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