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  Structure and fabrication of self-aligned high-performance organic fetsUSPTO Application #: 20070254402Title: Structure and fabrication of self-aligned high-performance organic fets Abstract: A low channel length organic field-effect transistor can be produced in high volume and at low cost. The transistor structure includes successively deposited patterned layers of a first conductor layer acting as a source terminal, a first dielectric layer, a second conductor layer acting as a drain terminal, a semiconductor layer, a second dielectric layer, and a third conductor layer acting as the gate terminal. In this structure, the transistor is formed on the edge of the first dielectric between the first conductor layer and the second conductor layer. The second conductor layer is deposited on the raised surfaces formed by the dielectric such that conductive ink does not flow into the trough between the dielectric raised surfaces. This is accomplished by coating a flat or rotary print plate with the conductive ink, and applying the appropriate pressure to deposit the materials only on the raised surfaces of the dielectric. The second metal is automatically aligned to the layer beneath it. Due to this self-alignment and the short channel formed by the thickness of the dielectric material, a high-performance FET is produced without the requirement of high-resolution lithography equipment. (end of abstract)
Agent: Hogan & Hartson LLP - Denver, CO, US Inventors: Klaus Dimmler, Robert R. Rotzoll USPTO Applicaton #: 20070254402 - Class: 438099000 (USPTO) Related Patent Categories: Semiconductor Device Manufacturing: Process, Having Organic Semiconductive Component The Patent Description & Claims data below is from USPTO Patent Application 20070254402. Brief Patent Description - Full Patent Description - Patent Application Claims
1. FIELD OF INVENTION [0001] The present invention relates to organic transistors and, more particularly, to a structure and method of fabricating high performing organic FETs utilizing an efficient high volume self-aligned patterning technique to produce low channel length organic FET devices. 2. DESCRIPTION OF RELATED ART [0002] Organic field-effect transistors (oFETs) have been proposed for a number of applications including displays, electronic barcodes and sensors. Low cost processes, large-area circuits and the chemically active nature of organic materials are the chief driving forces to make OFETs important in various applications. Many of these objectives depend on a method of fabrication utilizing printing techniques such as flexography, gravure, silk screen and inkjet printing. [0003] Organic MOS transistors are similar to silicon metal-oxide-semiconductor transistors in operation. The major difference in construction is that the organic MOS transistor utilizes a thin layer of a semiconducting organic polymer film to act as the semiconductor of the device, as opposed to a silicon layer as used in the more typical in-organic silicon MOS device. [0004] Referring now to FIG. 1, a cross-sectional diagram of a top-gate bottom contact organic MOS transistor 100 is shown. Two conductor regions 101 and 102 are deposited and patterned on substrate 112. The gap between conductive regions 101 and 102 is known as the "channel", and is designated as 103 in FIG. 1. A semiconductor layer 104 is deposited on the conductive regions 101 and 102. A thin film of dielectric material 106 is deposited on top of semiconductor layer 104. A conductive film 108 is deposited and patterned on top of organic semiconductor 106 to form the gate, such the gate completely overlaps the channel region 103. [0005] Through an electrical field effect, a voltage is applied between gate conductor 108 and source 101 modifies the resistance of the organic semiconductor in the channel region 103 in the vicinity of the interface between the semiconductor region 104 and the dielectric 106. When another voltage is applied between source 101 and drain 102, a current flows between the drain and the source that depends on both the gate-to-source and the drain-to-source voltages. [0006] Organic semiconductor materials are often classified as polymeric, low molecular weight, or hybrid. Pentacene, hexithiphene, TPD, and PBD are examples of low weight molecules. Polythiophene, parathenylene vinylene, and polyphenylene ethylene are examples of polymeric semiconductors. Polyvinyl carbazole is an example of a hybrid material. These materials are not classified as insulators or conductors. Organic semiconductors behave in a manner that can be described in terms analogous to the band theory in inorganic semiconductors. However, the actual mechanics giving rise to charge carriers in organic semiconductors are substantially different from inorganic semiconductors. In inorganic semiconductors, such as silicon, carriers are generated by introducing atoms of different valencies into a host crystal lattice, the quantity of which is described by the number of carriers that are injected into the conduction band, and the motion of which can be described by a wave vector k. In organic semiconductors, carriers are generated in certain materials by the hybridization of carbon molecules in which weakly bonded electrons, called .pi. electrons, become delocalized and travel relatively long distances from the atom which originally gave rise to the electron. This effect is particularly noted in materials comprising conjugated molecules or benzene ring structures. Because of the delocalization, these it electrons can be loosely described as being in a conduction band. This mechanism gives rise to a low charge mobility, a measure describing the speed with which these carriers can move through the semiconductor, resulting in dramatically lower current characteristics of organic semiconductors in comparison to inorganic semiconductors. [0007] Besides a lower mobility, the physics of carrier generation gives rise to another key difference between the operation of an organic MOS transistor and inorganic semiconductor. In the typical operation of an inorganic semiconductor, the resistance of the channel region is modified by an "inversion layer" consisting of the charge carriers made up of the type of charge that exists as a minority in the semiconductor. The silicon bulk is doped with the opposite type of carrier as compared to that used for conduction. For example, a p-type inorganic semiconductor is built with an n-type semiconductor, but uses p-type carriers, also called holes, to conduct current between the source and drain. In the typical operation of an organic semiconductor, however, the resistance of the channel region is modified by an "accumulation layer" consisting of charge carriers made up of the type of charge that exists as a majority in the semiconductor. For example, a PMOS organic transistor uses a P-type semiconductor and p-carriers, or holes, to generate the current in typical operation. [0008] Though organic transistors have much lower performance than inorganic transistors, the materials and processing techniques to produce organic transistors cost significantly less those used to produce inorganic transistors. Therefore, organic transistor technology has application where low cost is desired and low performance is acceptable. The performance of a transistor, both organic and inorganic, depends in part on the channel length, defined as the space between and source and drain. The maximum frequency of operation is inversely proportional to the square of this channel length. Therefore, it is desirable to reduce this space as much as possible. Low cost printing techniques are generally limited to a minimum range of 25.mu.. Printing at resolutions finer than this is generally not possible. [0009] In the prior art, transistors structures wherein the source and drain are vertical to each other have been proposed. This type of structure has the advantage that a small gap between the source and drain can be achieved without having to print at such high resolution. FIG. 2 illustrates the basic structure. The first conductor metal-source 204 and second conductor metal-drain 206 are deposited on either side of a first dielectric layer 208. The channel of the transistor is defined by the surface 209 between the first metal and the second metal conductors, thereby defining the channel length by the thickness of the first dielectric. A second dielectric 207 and a third conductor 214 are then deposited on that surface to complete the transistor. A high performance short-channel length transistor has thereby been produced without the need to print the short gap between the source and drain. [0010] A key to successful implementation of this structure is the alignment of metal-drain 206 and the beginning of the slope 211 of first dielectric 208. [0011] FIG. 3 illustrates the consequences of poor alignment between metal-drain 306 and the underlying first dielectric layer 308. When layers are aligned, there is always an alignment tolerance which specifies the accuracy by which one layer can be produced with respect to another layer below it. If the conductor is printed onto the slope, the ink will flow to short to the metal-source 304, rending the transistor nonfunctional. Therefore, it is necessary to allow a tolerance from the edge of the slope so that it can be guaranteed that the ink will not print on the slope 309 of dielectric 308. Consequently, the metal-drain layer 306 must be produced allowing a gap on the surface of dielectric 308 to ensure that in the worse case misalignment, the metal-drain 306 layer falls on point 311 at the edge of the dielectric slope 309. However, the channel length of the nominal device is now defined by the total distance between metal-drain 306 and metal-source 304, which now is now the slope 309 plus the gap 313 on the surface of dielectric 308. Since the alignment tolerance is likely to be large compared to the thickness of dielectric 308, the additional gap 313 is likely to be quite large in comparison. The advantages of the short channel length that can potentially be obtained through vertical transistors is consequently lost. For this reason, an effective vertical transistor requires a process that eliminates this alignment tolerance. [0012] One such method known in the prior art to eliminate this alignment tolerance is described by Natalie Stutzmann, Richard Friend, and Henning Sirringhause in Science on Mar. 21, 2004 in an article entitled "Self-Aligned, Vertical-Channel Polymer Field-Effect Transistors." FIG. 4 illustrates the methodology by which this is done. Referring to FIG. 4, a V-shaped impression die 410 is pressed through previously deposited layers consisting of first metal metal-source 404, first dielectric 406, and second metal 408. When the impression die 410 is lifted, a cut is made through the layers forming a sloped dielectric 406 while cutting the second metal 408 at the top of the dielectric slope. However, several issues make this fabrication method impractical. A serious problem with this method is that the metal 408 layer smears when pressing the impression die through the layers, thereby shorting second conductor 408 and first conductor 404. Another problem with this method is that the die impression forms a point at the bottom of the device, which is very difficult to deposit layers of controlled thickness in this region. One further problem with this method is that pressure controls the impression die depth of penetration. If the impression die pressure is too light, the impression will not penetrate to the first metal layer 404. If the impression die pressure is too heavy, the impression die will penetrate substrate 402, adversely affecting the performance of the transistors. The range of pressure is therefore defined by the thickness of the first conductor 404, a pressure variation that is too narrow for high-volume low-cost manufacturing methods. [0013] What is desired, therefore, is a practical structure for an organic FET that brings about a small channel length utilizing low cost printing techniques. SUMMARY OF THE INVENTION [0014] According to the present invention, a structure and method of fabrication is disclosed that can produce low channel length devices in high volume and at low cost. The structure includes successively deposited patterned layers of a first conductor layer acting as a source terminal, a first dielectric layer, a second conductor layer acting as a drain terminal, a semiconductor layer, a second dielectric layer, and a third conductor layer acting as the gate terminal. In this structure, the transistor is formed on the edge of the first dielectric between the first conductor layer and the second conductor layer. [0015] The second conductor layer is deposited on the raised surfaces formed by the dielectric such that the ink does not flow into the trough between the dielectric raised surfaces. In an embodiment of the invention, this is accomplished by coating a flat or rotary print plate with a conductive ink, and applying the appropriate pressure to deposit the materials only on the raised surfaces of the dielectric. In this manner, the second metal is automatically aligned to the layer beneath it. Due to this self-alignment and the short channel formed by the thickness of the dielectric material, a high-performance FET is produced without the requirement of high-resolution lithography equipment. BRIEF DESCRIPTION OF THE DRAWINGS [0016] The present invention is illustrated by way of example and not by limitation in the accompanying figures in which like reference numerals indicate similar elements and in which: [0017] FIG. 1 is a cross-sectional view of an organic FET transistor including an insulating substrate, organic polymer film, dielectric layer, and conductive gate according to the prior art; [0018] FIG. 2 is a cross-sectional view of an vertical FET transistor including an insulating substrate, organic polymer film, dielectric layer, and conductive gate according to the prior art; [0019] FIG. 3 is a cross-sectional view of an vertical FET transistor according to the prior art illustrating the consequences of poor alignment between the metal and dielectric layers; [0020] FIG. 4 is a cross-sectional view illustrating the "V-grove" method of achieving self-alignment between metal and dielectric according to the prior art; Continue reading... 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