| Stress-relief layers and stress-compensation collars with low-temperature solders for board-level joints, and processes of making same -> Monitor Keywords |
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Stress-relief layers and stress-compensation collars with low-temperature solders for board-level joints, and processes of making sameRelated Patent Categories: Semiconductor Device Manufacturing: Process, Coating With Electrically Or Thermally Conductive Material, To Form Ohmic Contact To Semiconductive Material, Forming Solder Contact Or Bonding PadStress-relief layers and stress-compensation collars with low-temperature solders for board-level joints, and processes of making same description/claimsThe Patent Description & Claims data below is from USPTO Patent Application 20070190772, Stress-relief layers and stress-compensation collars with low-temperature solders for board-level joints, and processes of making same. Brief Patent Description - Full Patent Description - Patent Application Claims
[0001] This application is a divisional of U.S. patent application Ser. No. 10/954,999, filed on Sep. 29, 2004, which is incorporated herein by reference. TECHNICAL FIELD [0002] Disclosed embodiments relate to a stress-relief layer and a stress-compensation collar that surround a low melting-point solder in a microelectronic device package. BACKGROUND INFORMATION [0003] Chip packaging is often intensely involved with heat removal. Thermal expansion-mismatch challenges exist between the die, the underfill material, and the substrate to which the die is mounted, and to connecting structures such as the motherboard. The thermal mismatch often is exhibited at the joint of a solder bump and its bond pad. [0004] One challenge with chip packaging technology is premature solder joint failure due to thermal stress. Future packaging technology especially in the chipset application, will drive finer pitch as package size shrinks. With miniaturization of pitch, smaller ball size poses an increasing challenge to solder joint performance. [0005] Two types of failure have been observed in solder bumps. One type is fatigue due to thermal stressing at the solder joint. Another type of failure results from mishandling the packages during processing, assembly, and transportation. These failures are primarily due to higher stress levels at the solder bump-contact pad interface. The solder joint has been observed to crack at the edges, and due to poor adhesion of the bumps to the pad, the solder has been observed to break away from the pad. BRIEF DESCRIPTION OF THE DRAWINGS [0006] In order to understand the manner in which embodiments are obtained, a more particular description of various embodiments briefly described above will be rendered by reference to the appended drawings. These drawings depict embodiments that are not necessarily drawn to scale and are not to be considered to be limiting in scope. Some embodiments will be described and explained with additional specificity and detail through the use of the accompanying drawings in which: [0007] FIG. 1 is a cross-section of a solder composition according to an embodiment; [0008] FIG. 2 is a process flow depiction of a solder during reflow according to an embodiment; [0009] FIG. 3A is a cross-section of a chip package during processing according to an embodiment; [0010] FIG. 3B is a cross-section of the chip package depicted in FIG. 3A during further processing according to an embodiment; [0011] FIG. 3C is a cross-section of the chip package depicted in FIG. 3B during further processing according to an embodiment; [0012] FIG. 3D is a cross-section of the chip package depicted in FIG. 3C during further processing according to an embodiment; [0013] FIG. 4 is a detail section taken from FIG. 3D according to an embodiment; [0014] FIG. 5 is a detail section taken from FIG. 3D according to an embodiment; [0015] FIG. 6A is a cross-section of the chip package depicted in FIG. 3B during further processing according to an embodiment; [0016] FIG. 6B is a cross-section of the chip package depicted in FIG. 6A during further processing according to an embodiment; [0017] FIG. 7 is a detail section taken from FIG. 6B according to an embodiment; [0018] FIG. 8A is a plan of a chip package during processing according to an embodiment; [0019] FIG. 8B is a plan of the chip package depicted in FIG. 8A during further processing according to an embodiment; [0020] FIG. 9A is a plan of a chip package during processing according to an embodiment; [0021] FIG. 9B is a plan of the chip package depicted in FIG. 9A during further processing according to an embodiment; Continue reading about Stress-relief layers and stress-compensation collars with low-temperature solders for board-level joints, and processes of making same... Full patent description for Stress-relief layers and stress-compensation collars with low-temperature solders for board-level joints, and processes of making same Brief Patent Description - Full Patent Description - Patent Application Claims Click on the above for other options relating to this Stress-relief layers and stress-compensation collars with low-temperature solders for board-level joints, and processes of making same patent application. ###  How KEYWORD MONITOR works... a FREE service from FreshPatents1. Sign up (takes 30 seconds). 2. Fill in the keywords to be monitored. 3. Each week you receive an email with patent applications related to your keywords. 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