|Static information storage and retrieval patents - Monitor Patents|
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Static information storage and retrievalBelow are recently published patent applications awaiting approval from the USPTO. Recent week's RSS XML file available below.
Listing for abstract view: USPTO application #, Title, Abstract excerpt,Patent Agent. Listing format for list view: USPTO National Class full category number, title of the patent application. 09/04/2014 > 48 patent applications in 26 patent subcategories.
08/28/2014 > 82 patent applications in 41 patent subcategories.
20140241022 - Memory dies, stacked memories, memory devices and methods: Memory die, stacks of memory dies, memory devices and methods, such as those to construct and operate such die, stacks and/or memory devices are provided. One such memory die includes an identification configured to be selectively coupled to an external select connection node depending on how the die is arranged... Agent: Micron Technology, Inc.
20140241025 - Dram cell design with folded digitline sense amplifier: The present invention is generally directed to a DRAM cell design with folded digitline sense amplifier. In one illustrative embodiment, a memory array having a plurality of memory cells having an effective size of 6F2 is disclosed which has a plurality of dual bit active areas, each of the active... Agent: Micron Technology, Inc.
20140241023 - Memory elements and cross point switches and arrays for same using nonvolatile nanotube blocks: Under one aspect, a covered nanotube switch includes: (a) a nanotube element including an unaligned plurality of nanotubes, the nanotube element having a top surface, a bottom surface, and side surfaces; (b) first and second terminals in contact with the nanotube element, wherein the first terminal is disposed on and... Agent:
20140241024 - Multi channel semiconductor memory device and semiconductor device including the same: Disclosed is a semiconductor memory device that includes a plurality of channel memories mounted within a package and is capable of minimizing or reducing the number of through-silicon vias. With the semiconductor memory device, a row command or a row address on two or more channels is applied through a... Agent: Samsung Electronics Co., Ltd.
20140241026 - Interconnections for 3d memory: Apparatuses and methods for interconnections for 3D memory are provided. One example apparatus can include a stack of materials including a plurality of pairs of materials, each pair of materials including a conductive line formed over an insulation material. The stack of materials has a stair step structure formed at... Agent: Micron Technology, Inc.
20140241029 - Semiconductor memory device: A memory cell array comprises first wiring lines, second wiring lines, and memory cells disposed at intersections thereof. A control circuit comprises a first power-supply line supplying a first voltage to selected ones of the first or second wiring lines, and first selection circuits connected between the first or second... Agent: Kabushiki Kaisha Toshiba
20140241027 - Static random access memory unit cell structure and static random access memory unit cell layout structure: A static random access memory unit cell layout structure is disclosed, in which a slot contact is disposed on one active area and another one across from the one. A static random access memory unit cell structure and a method of fabricating the same are also disclosed, in which, a... Agent: United Microelectronics Corp.
20140241028 - Two-bit read-only memory cell: A read-only memory (ROM) cell has first and second transistors connected in series between a true bit line and a voltage reference (e.g., ground), and third and fourth transistors connected in series between a complement bit line and the voltage reference. The gates of the first and third transistors are... Agent: Lsi Corporation
20140241030 - Shift register and shift register type magnetic memory: A shift register according to an embodiment includes: a magnetic nanowire; a first control electrode group and a second control electrode group arranged with the magnetic nanowire being sandwiched therebetween, the first control electrode group including a plurality of first control electrodes arranged to be spaced apart from each other... Agent:
20140241031 - Dielectric-based memory cells having multi-level one-time programmable and bi-level rewriteable operating modes and methods of forming the same: In some aspects, a memory cell is provided that includes a steering element and a memory element. The memory element includes a first conductive material layer, a first dielectric material layer disposed above the first conductive material layer, a second conductive material layer disposed above the first dielectric material layer,... Agent: Sandisk 3d LLC
20140241040 - Electronic device: An electronic device comprising a semiconductor memory unit that may include a variable resistance element configured to be changed in a resistance value thereof in response to current flowing through both ends thereof, a toggle data generation unit configured to generate toggle data of which logic value toggles with a... Agent: Sk Hynix Inc.
20140241043 - Electronic device and method for operating electronic device: An electronic device comprising a semiconductor memory unit that may include a plurality of data transfer lines; a plurality of columns including a plurality of memory cells; at least one redundancy column including a plurality of redundancy memory cells and configured to replace at least one column among the plurality... Agent: Sk Hynix Inc.
20140241039 - Electronic device and method for operating the same: An electronic device including a semiconductor memory. The semiconductor memory includes a plurality of variable resistance elements; a plurality of read voltage application terminals configured to supply different levels of read voltages to respective one ends of the plurality of variable resistance elements; and an analog-to-digital conversion unit configured to... Agent: Sk Hynix Inc.
20140241042 - Electronic device and method for operating the same: An electronic device including a semiconductor memory. The semiconductor memory includes a cell array divided into at least two regions each of which includes a plurality of memory cells each including a transistor and a resistance variable element; a write driver circuit configured to supply write current to a memory... Agent: Sk Hynix Inc.
20140241033 - Management of variable resistance data storage device: Various embodiments may generally be directed to a variable resistance data storage device and a method of managing the device. A data storage device may have at least a controller configured to re-characterize at least one variable resistance memory cell in response to an identified variance from a predetermined resistance... Agent: Seagate Technology LLC
20140241036 - Memory system: A memory system according to the embodiment comprises a cell array of unit cell arrays each including memory cells; and an access circuit, wherein the memory cell changes from a first resistance state to a second resistance state on application of a first polarity voltage, and changes from the second... Agent: Kabushiki Kaisha Toshiba
20140241032 - Methods and apparatuses using a transfer function to predict resistance shifts and/or noise of resistance-based memory: Two or more workload indicators affecting a memory cell of a resistance-based, non-volatile memory are measured. The two or more workload indicators are applied to a transfer function that predicts a resistance shift and/or resistance noise variance in response to the two or more workload indicators. A result of the... Agent: Seagate Technology LLC
20140241041 - Reference column of semiconductor memory, and electronic device including the same: A reference column of a semiconductor memory includes a reference bit line; a reference source line; and first to Nth resistive memory cells disposed between the reference bit line and the reference source line. Data of a first state is stored in the first resistive memory cell and data of... Agent: Sk Hynix Inc.
20140241035 - Reram forming with reset and iload compensation: FORMING reversible resistivity-switching elements is described herein. The FORMING voltage may be halted if the current through the memory cell reaches some reference current. The reference current may depend on how many groups of memory cells have been FORMED. This can help to increase the accuracy of determining when to... Agent: Sandisk 3d LLC
20140241034 - Resistive switching random access memory structure and method to recreate filament and recover resistance window: The present disclosure provides one embodiment of a method for operating a resistive random access memory (RRAM) cell. The method includes performing a forming operation to the RRAM cell with a forming voltage; performing a number of set/reset operation cycles to the RRAM cell; and performing a recreating process to... Agent: Taiwan Semiconductor Manufacturing Company, Ltd.
20140241038 - Semiconductor device and method of controlling semiconductor device: A memory cell is included which has a selection transistor and a variable resistance device connected to a bit line through the selection transistor. The variable resistance device includes a first electrode which has a first metal material and is connected to the selection transistor, a second electrode which has... Agent: Renesas Electronics Corporation
20140241037 - Semiconductor memory device: A memory cell array includes first wiring lines, and second wiring lines, the first and second wiring lines intersecting, and memory cells disposed in the intersections of the first and second wiring lines, the memory cells including a variable resistance element. A control circuit controls voltages of selected first and... Agent: Kabushiki Kaisha Toshiba
20140241044 - Structure of a switching device in an array: A switching device has a bottom conductor, a top conductor, and a device body formed between the top and bottom conductors. The device body has a switching layer that is switchable by means of current passed through the device body and between the top and bottom conductors. A lower via... Agent:
20140241045 - Semi-conductor storing apparatus: A semi-conductor storing apparatus is provided, which comprises plural storing units, each having a line buffer including plural flip-flop circuits and a clock supplying circuit for supplying a clock to the plural flip-flop circuits, a clock-controlling unit, which controls on/off operation of the clock supplying circuit to decide whether to... Agent: Casio Computer Co., Ltd.
20140241046 - Semiconductor memory devices with a power supply: A semiconductor device includes a virtual power supplier, a driving signal generator and a load driver. The virtual power supplier boosts a driving voltage to generate a virtual voltage. The driving signal generator generates a driving signal based on the virtual voltage, such that the driving signal has a voltage... Agent: Samsung Electronics Co., Ltd.
20140241047 - Self-aligned process for fabricating voltage-gated mram: A STT-MRAM comprises apparatus and a method of manufacturing a spin-torque magnetoresistive memory and a plurality of a three-terminal magnetoresistive memory element having a voltage-gated recording. A bit line is coupled to the memory element through an upper electrode provided on the top surface of a reference layer, a select... Agent: T3memory, Inc.
20140241049 - Apparatuses, sense circuits, and methods for compensating for a wordline voltage increase: Apparatuses, sense circuits, and methods for compensating for a voltage increase on a wordline in a memory is described. An example apparatus includes a bitline, a memory cell coupled to the bitline, a bipolar selector device coupled to the memory cell, a wordline coupled to the bipolar selector device, and... Agent: Micron Technology, Inc.
20140241050 - Nonvolatile semiconductor memory device: According to one embodiment, a nonvolatile semiconductor memory device includes a memory cell which stores data with two or more levels. The memory cell includes a structure includes a first electrode layer, a first semiconductor layer, a phase change film, an electrical insulating layer, a second semiconductor layer, and a... Agent:
20140241048 - Phase change memory management: A three dimensional (3D) stack of phase change memory (PCM) devices which includes PCM devices stacked in a 3D array, the PCM devices having memory regions; a memory management unit on at least one of the PCM devices; a stack controller in the memory management unit to monitor an ambient... Agent: International Business Machines Corporation
20140241051 - Semiconductor device and its manufacturing method: In a semiconductor device including a memory cell array formed of memory cells using a storage element by a variable resistor and a select transistor, a buffer cell is arranged between a sense amplifier and the memory cell array and between a word driver and the memory cell array. The... Agent: Renesas Electronics Corporation
20140241052 - Carbon nanotube memory cell with enhanced current control: A desired current through a carbon nano tube (CNT) element of a CNT memory device can be controlled by a wordline voltage, and a voltage on the CNT common node can be held constant. The common node can be constant at a source voltage if a p-channel metal-oxide-semiconductor field-effect transistor... Agent: Honeywell International Inc.
20140241053 - Trench isolation implantation: Embodiments of the disclosure include a shallow trench isolation structure having a dielectric material with energetic species implanted to a predetermined depth of the dielectric material. Embodiments further include methods of fabricating the trench structures with the implant of energetic species to the predetermined depth. In various embodiments the implant... Agent: Micron Technology, Inc.
20140241054 - Semiconductor device and electronic device: To provide a semiconductor device with such a new structure that the effect of variation in transistor characteristics can be reduced to achieve less variation in the output voltage of a memory cell. A memory cell includes a source follower (common drain) transistor for reading data held in a gate.... Agent: Semiconductor Energy Laboratory Co., Ltd.
20140241055 - Method and system for reducing the complexity of electronically programmable nonvolatile memory: Embodiments relate to memory devices and methods for firmly programming at least a portion of a plurality of electronically programmable and erasable nonvolatile memory cells in a processing of the nonvolatile memory devices.... Agent: Infineon Technologies Ag
20140241057 - Nonvolatile semiconductor memory device: A nonvolatile semiconductor memory device according to an embodiment includes a memory cell array having a plurality of memory cell transistors connected in series therein; a plurality of bit lines; and a control circuit for executing a read operation. The control circuit is configured capable of executing the read operation,... Agent: Kabushiki Kaisha Toshiba
20140241058 - Nonvolatile semiconductor memory device and method of controlling same: According to an embodiment, a semiconductor memory device includes a memory cell array and a control circuit. The memory cell array comprises a plurality of memory cells that each include a control gate and a charge accumulation layer and that each are configured to have a threshold set to be... Agent: Kabushiki Kaisha Toshiba
20140241056 - Reduced complexity reliability computations for flash memories: Methods and apparatus are provided for computing reliability values, such as log likelihood ratios (LLRs), with reduced complexity for flash memory devices. Data from a flash memory device that stores M bits per cell using 2̂M possible states is processed by obtaining at least two soft read voltage values corresponding... Agent: Lsi Corporation
20140241059 - Method and device for storing and reading reliable information in a nand array: A method (and device) includes producing first data in a page region of a memory, the first data including a first number of memory sets, each of the memory sets having a second number of bits, where the first number is a positive number more than one and the second... Agent: Elpida Memory, Inc.
20140241060 - Sub-block decoding in 3d memory: Some embodiments relate to apparatuses and methods associated with blocks of memory cells. The blocks of memory cells may include two or more sub-blocks of memory cells. Sub-blocks may comprise a vertical string of memory cells including a source select transistor and a drain select transistor. An apparatus may include... Agent: Micron Technology, Inc.
20140241061 - Fast access with low leakage and low power technique for read only memory devices: A Read Only Memory (ROM) and method for providing a high operational speed with reduced leakage, no core cell standby leakage, and low power consumption. The source of the ROM cell (NMOS) is connected to a virtual ground line (VNGD) instead of VSS. Thus, the ROM cell can be operatively... Agent: Lsi Corporation
20140241062 - Modular, scalable rigid flex memory module: A memory card in a computer system includes a plurality of memory elements on a NAND flash board. The NAND flash board is connected to a controller board by a flexible connector. The flexible connector allows the memory elements and NAND flash controller to be physically separated so that waste... Agent: Lsi Corporation
20140241064 - Nonvolatile memory and operating method of nonvolatile memory: An operating method of a nonvolatile memory is provided which includes adjusting a threshold voltage of at least one first memory cell adjacent to a substrate in each cell string to be higher than a threshold voltage distribution of an erase state; and reading a second memory cell located above... Agent:
20140241063 - Semiconductor memory device: A semiconductor memory device comprises a memory string including first and second selection transistors, and first and second groups of memory cell transistors connected in series between the first and second selection transistors; a bit line and a source line respectively connected to the first and second selection transistors; first... Agent: Kabushiki Kaisha Toshiba
20140241065 - Vertically-integrated nonvolatile memory devices having laterally-integrated ground select transistors: Nonvolatile memory devices utilize vertically-stacked strings of nonvolatile memory cells (e.g., NAND-type strings) that can be selectively coupled to common source lines within a substrate. This selective coupling may be provided by lateral ground select transistors having different threshold voltages that account for different lateral spacings between the vertically-stacked strings... Agent:
20140241066 - Dual-function read/write cache for programmable non-volatile memory: A non-volatile memory, such as a one-time programmable memory, with a dual purpose read/write cache. The read/write cache is used as a write cache during programming, and stores the data to be written for a full row of the memory array. The programming operation simultaneously programs all cells in the... Agent: Texas Instruments Incorporated
20140241067 - Method and apparatus for reading data stored in flash memory by referring to binary digit distribution characteristics of bit sequences read from flash memory: A method for reading data stored in a flash memory includes at least the following steps: controlling the flash memory to perform a plurality of read operations upon a plurality of memory cells included in the flash memory; obtaining a plurality of bit sequences read from the memory cells, respectively,... Agent: Silicon Motion Inc.
20140241069 - Memory system and memory access method: Systems and methods of sequentially accessing memory cells in a nonvolatile memory device (NVM) are provided. The NVM has a plurality of strings and a common signal line coupled to the plurality of strings. Each string includes a plurality of memory cells and a selection transistor coupled between the plurality... Agent:
20140241068 - Non-volatile semiconductor storage device: In one embodiment, a non-volatile semiconductor storage device includes a memory cell array in which a plurality of non-volatile memory cells is aligned, and a control unit which repeats a write operation of applying a write voltage to a selected memory cell, a verify operation of checking whether or not... Agent:
20140241077 - Tracking circuit: A current flowing through a voltage line and/or a data line in a column of a tracking circuit is determined. A threshold tracking time delay of the tracking circuit is determined. Based on the determined current handled by the voltage line and/or the data line and the determined threshold tracking... Agent: Taiwan Semiconductor Manufacturing Company, Ltd.
20140241070 - Reference and sensing with bit line stepping method of memory: A sensing method for a memory is provided. The memory includes: a memory cell; a reference circuit generating a reference voltage and a clamp voltage; and a current supplying circuit receiving the clamp voltage to develop a cell current passing through the memory cell to form a cell voltage, wherein... Agent:
20140241071 - Fast power loss recovery by swapping boot and recovery data sets in a memory: Method and apparatus for managing data in a memory. In accordance with some embodiments, a recovery data set representing a current state of a storage device is stored in a rewritable non-volatile memory responsive to detection of a potentially imminent deactivation of the device. The recovery data set is swapped... Agent: Seagate Technology LLC
20140241073 - Semiconductor device: Disclosed herein is an apparatus that includes: a first terminal configured to receive a serial write data signal that includes at least four bits transferred in series with each other; a second terminal configured to receive a data strobe signal; a control circuit configured to produce a plurality of internal... Agent: Micron Technology, Inc.
20140241072 - Semiconductor memory device: A semiconductor memory device includes a memory cell array including memory cells arranged therein. A first latch circuit temporarily holds data to perform a read operation and a write operation on the memory cell array. The second latch circuit temporarily holds a control signal. A control circuit controls the memory... Agent: Kabushiki Kaisha Toshiba
20140241074 - Reference frequency setting method, memory controller and memory storage apparatus: A reference frequency setting method of a memory storage apparatus including the following steps is provided. A setting code is read from a memory module or a storage unit by a first signal transmission path and stored into a register circuit. The setting code includes a first setting information. Whether... Agent: Phison Electronics Corp.
20140241075 - Memory elements with series volatile and nonvolatile switches: A memory element includes a nonvolatile switch to be set to a first low resistance state by applying a voltage higher than a positive threshold voltage and to a second high resistance state by applying another voltage more negative than a negative threshold voltage. The memory element further includes a... Agent: Hewlett-packard Development Company, L.p.
20140241076 - Semiconductor memory device, method of testing the same and method of operating the same: A method of testing a semiconductor memory device is provided. Data is written to a plurality of memory cells disposed in a memory cell block of the semiconductor memory device. A first driving voltage is applied to a first group of word lines. A second driving voltage is applied to... Agent:
20140241080 - Bridge device architecture for connecting discrete memory devices to a system: A composite memory device including discrete memory devices and a bridge device for controlling the discrete memory devices in response to global memory control signals having a format or protocol that is incompatible with the memory devices. The discrete memory devices can be commercial off-the-shelf memory devices or custom memory... Agent: Conversant Intellectual Property Management Inc.
20140241079 - Chip die and semiconductor memory device including the same: A chip die including a first input/output (I/O) pad configured to transmit/receive an I/O signal of a memory cell array included in the chip die; a second I/O pad configured to, if a stacked chip die exists on the chip die, transmit/receive a via I/O signal of the stacked chip... Agent: Sk Hynix Inc.
20140241078 - Semiconductor memory device: A sense amplifier circuit is divided into a plurality of sense amplifier groups. The plurality of sense amplifier groups are each further divided into a plurality of sense units. A sense amplifier control circuit is configured to sequentially select the plurality of sense amplifier groups according to a physical address,... Agent: Kabushiki Kaisha Toshiba
20140241081 - Nonvolatile memory device, read method for nonvolatile memory device, and memory system incorporating nonvolatile memory device: A method of performing a read operation on nonvolatile memory device comprises receiving a read command, receiving addresses, detecting a transition of a read enable signal, generating a strobe signal based on the transition of the read enable signal, reading data corresponding to the received addresses, and outputting the read... Agent:
20140241082 - Auto-calibration for high speed input/output: A delay and calibration circuit for an input/output determines an appropriate delay by trying a range of different delays, and for each delay, determining the number of times that a given data sequence is accurately received. The data sequence may be a command, address, host data, or other data. Appropriate... Agent: Sandisk Technologies Inc.
20140241083 - Read assist circuit for an sram technical field: A memory circuit includes a bit cell that receives a word line, complementary bit lines and an array supply voltage; a word line driver coupled to the word line, the word line driver receiving one of the array supply voltage and a periphery supply voltage; and a word line suppression... Agent: Texas Instruments Incorporated
20140241086 - Memory structure: A memory structure includes a memory row of a memory array, a plurality of first bits, a first redundancy row, and a plurality of second bits. The memory row includes a plurality of memory words. The plurality of first bits is configured to indicate whether an individual memory word of... Agent: Taiwan Semiconductor Manufacturing Company, Ltd.
20140241084 - Method and apparatus for repairing defective memory cells: A method for repairing defective memory cells includes receiving an access command having an access address and an access operation. The access address includes a row address and a column address. The method further includes determining whether the row address and the column address are the same as a pre-recorded... Agent:
20140241085 - Semiconductor memory device for performing disable operation using anti-fuse and method thereof: A semiconductor memory device for performing a disable operation using an anti-fuse, and method thereof are provided. The semiconductor memory device according to an example embodiment includes a fuse circuit including at least one anti-fuse configured to store fuse data, a memory circuit configured to at least one of read... Agent: Samsung Electronics Co., Ltd.
20140241088 - Semiconductor device having complementary bit line pair: Disclosed herein is a semiconductor device comprising complementary pair of bit lines, memory cells connected to the bit lines, dummy cells having the same structure as the memory cells, a differential sense amplifier, an equalizing circuit equalizing potentials of the bit lines, and a control circuit. The memory cells are... Agent: Ps4 Luxco S.a.r.l.
20140241087 - Sense amplifier: A sense amplifier comprises a cross coupled pair of inverters, a first transistor, a second transistor, and a capacitive device. The cross coupled pair of inverters includes a first end, a second end, and a third end. The first end is configured to receive a first supply voltage. The second... Agent: Taiwan Semiconductor Manufacturing Company, Ltd.
20140241089 - Read assist circuit for an sram technical field: A memory circuit includes a bit cell that receives a word line, complementary bit lines and an array supply voltage; a word line driver coupled to the word line, the word line driver receiving one of the array supply voltage and a periphery supply voltage; and a word line suppression... Agent: Texas Instruments Incorporated
20140241091 - Sense amplifier voltage regulator: A memory is disclosed that includes a plurality of memory cells, a plurality of sense amplifiers for reading data of the memory cells, and a voltage regulator coupled to the plurality of sense amplifiers. The voltage regulator includes a reference sense amplifier, a current injector, and a current injector control... Agent:
20140241090 - Smart read scheme for memory array sensing: Methods for reducing variability in bias voltages applied to a plurality of memory cells during a sensing operation caused by IR drops along a word line shared by the plurality of memory cells are described. In some embodiments, IR drops along a shared word line may be reduced by reducing... Agent: Sandisk 3d LLC
20140241092 - Sub-block disabling in 3d memory: Some embodiments relate to apparatuses and methods associated with blocks of memory cells. The blocks of memory cells may include two or more sub-blocks of memory cells. One such sub-block may comprise a vertical string of memory cells including a select transistor. An apparatus may include a sub-block disabling circuit.... Agent: Micron Technology, Inc.
20140241093 - Devices, systems and methods with improved refresh address generation: A refresh address generator may include a lookup table including a first portion storing a first group of addresses associated with a first data retention time, and a second portion storing a second group of addresses associated with a second data retention time different from the first data retention time,... Agent: Samsung Electronics Co., Ltd.
20140241094 - Memory device refresh commands on the fly: On the fly switching from one memory device refresh rate to another is provided. Control logic associated with the memory device detects a condition to switch from a currently-applied refresh rate to a different refresh rate. In response to the condition, the refresh rate is dynamically switched. The switching does... Agent:
20140241095 - Semiconductor system: To provide a semiconductor system including a plurality of core chips and an interface chip that controls the core chips. Each of the core chips includes an internal voltage generating circuit. The interface chip includes an unused chip information holding circuit that stores therein unused chip information of the core... Agent:
20140241096 - Storage device: A storage device according to an embodiment includes first and second non-volatile semiconductor memories. In addition, the storage device includes first controller that controls the first non-volatile memory to cause the first non-volatile memory to perform processes. In addition, the storage device includes second controller that controls the second non-volatile... Agent: Kabushiki Kaisha Toshiba
20140241097 - Loading trim address and trim data pairs: Methods of loading trim address and trim data pairs to a trim register array, and apparatus configured to perform such methods. The methods maintain a correspondence between the trim address and the trim data of each trim address and trim data pair in the trim register array. The trim address... Agent:
20140241098 - Memory device and memory system including the same: A memory device may be provided which includes a memory cell array including a plurality of sub arrays each sub array having a plurality of memory cells connected to bit lines; an address buffer configured to receive a row address and a column address; and a column decoder configured to... Agent: Samsung Electronics Co., Ltd.
20140241099 - Semiconductor memory and memory system including the semiconductor memory: A memory system is provided which includes multiple semiconductor memories having arrays of memory cells and a memory controller configured to provide an address in common to the multiple memories. First and second addresses corresponding to first and second rows of memory cells in first and second memories are selected... Agent: Samsung Electronics Co., Ltd.
20140241100 - Synchronous multiple port memory with asynchronous ports: A memory system includes a multi-port memory having a first port and a second port. First registers and second registers provide first and second addresses, respectively, to the first and second ports. An access controller controls the multi-port memory to launch an access for the valid address provided by the... Agent:
20140241101 - Word line driver and related method: A word line driver includes a first transistor electrically connected to a first voltage supply node and a word line, a second transistor electrically connected to a second voltage supply node and the word line, a first switch electrically connected to the first voltage supply node and a bulk electrode... Agent: Taiwan Semiconductor Manufacturing Company, Ltd.
20140241102 - Dual clock edge triggered memory: A memory circuitry includes memory components operable in response to first edges of an internal clock; and internal clock generating circuitry to generate the internal clock in response to a system clock, wherein the first edges of the internal clock are generated in response to both a rising and a... Agent: Stmicroelectronics, Sa
20140241103 - Semiconductor device having cal latency function: A method for accessing a semiconductor device having a memory array, the method includes receiving a mode register command to set a command latency value in a mode register, receiving a chip select signal, activating a command receiver in response to the chip select signal, receiving, with the command receiver,... Agent:08/21/2014 > 49 patent applications in 32 patent subcategories.
20140233292 - 3d semiconductor device: A three-dimensional (3D) semiconductor device may include a stack of chips, including a master chip and one or more slave chips. I/O connections of slave chips need not be connected to channels on a motherboard, and only electrode pads of a master chip may be connected to the channels. Only... Agent: Samsung Electronics Co., Ltd.
20140233293 - Permutational memory cells: Various embodiments comprise apparatuses having at least two resistance change memory (RCM) cells. In one embodiment, an apparatus includes at least two electrical contacts coupled to each of the RCM cells. A memory cell material is disposed between pairs of each of the electrical contacts coupled to each of the... Agent: Micron Technology, Inc.
20140233294 - Memory cell with decoupled read/write path: A memory cell with a decoupled read/write path includes a switch comprising a first terminal connected to a first line and a second terminal connected to a second line, a resistive switching device connected between a gate of the switch and a third line, and a conductive path between the... Agent: Taiwan Semiconductor Manufacturing Company, Ltd.
20140233295 - Rom device with keepers: A ROM memory circuit is disclosed having at least one electrical line, at least one keeper circuit electrically connected to the at least one electrical line, the keeper circuit including a first transistor, a terminal of the first transistor is driven by a dedicated control signal, wherein the dedicated control... Agent: Intel Mobile Communications Gmbh
20140233296 - Ferroelectric memory device and method for manufacturing same: The present application relates to a ferroelectric memory device having a multilevel polarization (MLP) state generated due to adjustment of a displacement current and to a method for manufacturing the ferroelectric memory device.... Agent: Seoul National University R%db Foundation
20140233297 - Graphene ferroelectric device and opto-electronic control of graphene ferroelectric memory device: In accordance with an embodiment of the invention, there is provided a graphene ferroelectric device. The device comprises a graphene transistor channel and a ferroelectric gate of the graphene transistor channel, the ferroelectric gate comprising a linear polarization at a first applied gate voltage less than a threshold voltage, and... Agent:
20140233298 - Apparatus and methods for forming a memory cell using charge monitoring: Apparatuses and methods of forming a memory cell is described. In one such method, a forming charge applied to a memory cell, such as a Resistive RAM (RRAM) memory cell, is monitored to determine the progress of the forming the cell. If the cell is consuming charge too slowly, a... Agent: Micron Technology, Inc.
20140233300 - Apparatuses and operation methods associated with resistive memory cell arrays with separate select lines: The present disclosure includes methods and apparatuses that include resistive memory. A number of embodiments include a first memory cell coupled to a data line and including a first resistive storage element and a first access device, a second memory cell coupled to the data line and including a second... Agent: Micron Technology, Inc.
20140233301 - Resistive switching for non volatile memory device using an integrated breakdown element: A method of suppressing propagation of leakage current in an array of switching devices. The method includes providing a dielectric breakdown element integrally and serially connected to a switching element within each of the switching device. A read voltage (for example) is applied to a selected cell. The propagation of... Agent:
20140233299 - Set/reset algorithm which detects and repairs weak cells in resistive-switching memory device: A resistance-switching memory cell is programmed in a set or reset operation which tests the stability of the cell. A first programming phase using program voltages which increase in magnitude or duration until a program verify test is passed. A stability test phase is then performed to evaluate a stability... Agent: Sandisk 3d LLC
20140233304 - Semiconductor device and control method of the same: A semiconductor device includes non-volatile registers, each including a holding circuit to hold data in a volatile manner and a non-volatile element. An address is allocated to each of the non-volatile registers. A non-volatile register control circuit performs control such that, in response to a write instruction, data held in... Agent: Nec Corporation
20140233303 - Sram multiplexing apparatus: An SRAM multiplexing apparatus comprise a plurality of local multiplexers and a global multiplexer. Each local multiplexer is coupled to a memory bank. The global multiplexer has a plurality of inputs, each of which is coupled to a corresponding output of the plurality of local multiplexers. In response to a... Agent: Taiwan Semiconductor Manufacturing Company, Ltd.
20140233302 - Write-tracking circuitry for memory devices: A write-tracking circuit for a writable memory array has one or more dummy memory cells and is configured to write different values to the one or more dummy memory cells. Durations of pulses applied to word lines of the memory array during write operations are controlled based on durations of... Agent: Lsi Corporation
20140233306 - Bipolar spin-transfer switching: A magnetic device includes a magnetized polarizing layer, a free magnetic layer, and a reference layer. The free magnetic layer forms a first electrode and is separated from the magnetized polarizing layer by a first non-magnetic metal layer. The free magnetic layer has a magnetization vector having a first and... Agent: New York University
20140233305 - Magnetic random access memory having increased on/off ratio and methods of manufacturing and operating the same: A magnetic random access memory (MRAM), and methods of manufacturing and operating the MRAM, include a switching element and a storage node connected to the switching element, and a magnetic node configured to simultaneously store two opposite bits.... Agent: Samsung Electronics Co., Ltd.
20140233307 - Method of programming a phase change memory and phase change memory device: A method for pre-programming a matrix of phase-change memory cells, including a phase-change material positioned between two conducting electrodes and able to be reversely electrically modified so as to vary the resistivity of the memory cell. A dielectric layer is provided with the memory cell having an original resistive state... Agent: Commissariat A L'energie Atomique Et Aux Ene Alt
20140233310 - High-resolution readout of analog memory cells: A method includes storing data in an analog memory cell by writing an analog value into the memory cell. After storing the data, the data stored in the memory cell is read by discharging electrical current to flow through the memory cell, during a predefined time interval, while applying a... Agent: Apple Inc.
20140233311 - Nonvolatile semiconductor memory: A memory includes first and second select gate transistors, memory cells, a source line, a bit line, a selected word line which is connected to a selected memory cell as a target of a verify reading, a non-selected word line which is connected to a non-selected memory cell except the... Agent: Kabushiki Kaisha Toshiba
20140233309 - Semiconductor memory device: According to one embodiment, a semiconductor includes a memory cell, a bit line, a word line, a sense amplifier, and a control circuit. The memory cell stores n levels (where n is a natural number of two or greater). The control circuit controls potentials of the word line and the... Agent:
20140233312 - Semiconductor memory device for storing multivalued data: Data storage circuits are connected to the bit lines in a one-to-one correspondence. A write circuit writes the data on a first page into a plurality of 5 first memory cells selected simultaneously by a word line. Thereafter, the write circuit writes the data on a second page into the... Agent: Kabushiki Kaisha Toshiba
20140233313 - Flash memory device reducing layout area: A flash memory device reducing a layout area is provided. In the flash memory device, even power transistors and odd power transistors of a plurality of power connection portions corresponding to a plurality of pairs of bit lines and even select transistors and odd select transistors of a plurality of... Agent: Fidelix Co., Ltd.
20140233314 - Memory cell coupling compensation: Methods for memory cell coupling compensation and apparatuses configured to perform the same are described. One or more methods for memory cell coupling compensation includes determining a state of a memory cell using a voltage that is changed in accordance with a first memory cell coupling compensation voltage, performing an... Agent: Micron Technology, Inc.
20140233315 - 3d stacked nand flash memory array having ssl status check buildings for monitoring threshold voltages of string selection transistors and methods for monitoring and operating the same: Disclosed is a 3D stacked NAND flash memory array having SSL status check buildings for monitoring threshold voltages of string selection transistors, a monitoring method of threshold voltages of string selection transistors by the SSL status check buildings, and an operating method thereof.... Agent: Seoul National University R&db Foundation
20140233316 - Memory system and programming method thereof: A program method of a nonvolatile memory device is provided, which includes programming a memory cell in one string selected from a plurality of vertical strings; determining whether a mode of operation of the nonvolatile memory device is a pre-pulse mode; when the mode of operation is determined to be... Agent:
20140233318 - Dynamic data caches, decoders and decoding methods: Examples described include dynamic data caches (DDCs), decoders and decoding methods that may fit into a smaller width area. The DDCs, decoders and decoding method may be used in flash memory devices. A single column select line may be provided to select a plurality of cached bytes, while a second... Agent: Micron Technology. Inc.
20140233317 - Generation of a composite read based on neighboring data: A victim group of one or more cells is read using a first read threshold to obtain a first raw read which includes one or more values. The victim group of cells is read using a second read threshold to obtain a second raw read which includes one or more... Agent:
20140233319 - Semiconductor device with one-time programmable memory cell including anti-fuse with metal/polycide gate: A one-time programmable (OTP) memory cell includes a dual date transistor and, in some embodiments, two transistors. The dual gate transistor is formed using the same processing operations used to form floating gate transistors in other areas of the semiconductor device. The dual gate transistor includes an upper gate isolated... Agent: Wafertech, LLC
20140233308 - Semiconductor memory device and writing method thereof: A writing method of a semiconductor memory device includes applying a plurality of program voltages sequentially generated to a selected word line, and applying any one of a plurality of source selection line voltages to a source selection line when each of the plurality of program voltages is applied.... Agent:
20140233320 - Nonvolatile semiconductor memory device: A nonvolatile semiconductor memory device includes a memory cell, a bit line electrically connected to the memory cell, a sense amplifier that includes a first transistor having a first end electrically connected to the bit line, a second transistor electrically connected between a second end of the first transistor and... Agent: Kabushiki Kaisha Toshiba
20140233321 - Word-line driver for memory: A word-line driver includes first, second and third transistors. The first transistor includes a gate terminal driven by a first group selection signal, a first conduction terminal driven by a second sub-group selection signal and a second conduction terminal coupled to the word-line. The second transistor includes a gate terminal... Agent: Stmicroelectronics International N.v.
20140233322 - Adaptive architecture in a channel detector for nand flash channels: An apparatus comprising a memory configured to store data and a controller. The controller may be configured to process a plurality of input/output requests to read/write to/from the memory. The controller is configured to (i) set a value of a threshold voltage based on an estimate, (ii) determine whether the... Agent: Lsi Corporation
20140233323 - Nonvolatile semiconductor memory device: A control circuit is configured to, during an erase operation, set a voltage of a first line connected to a selected cell unit to a voltage larger than a voltage of a gate of a first transistor included in the selected cell unit by an amount of a first voltage.... Agent: Kabushiki Kaisha Toshiba
20140233329 - Compensation scheme for non-volatile memory: Methods for performing parallel voltage and current compensation during reading and/or writing of memory cells in a memory array are described. In some embodiments, the compensation may include adjusting a bit line voltage and/or bit line reference current applied to a memory cell based on a memory array zone, a... Agent: Sandisk 3d LLC
20140233324 - Data paths using a first signal to capture data and a second signal to output data and methods for providing data: Data paths, memories, and methods for providing data from memory are disclosed. An example read data path includes a delay path, and a clocked data register. The data path has a data propagation delay and is configured to receive data and propagate the data therethrough. The delay path is configured... Agent: Micron Technology, Inc.
20140233325 - Dynamic random access memory with fully independent partial array refresh function: A dynamic random access memory device includes a plurality of memory subblocks. Each subblock has a plurality of wordlines whereto a plurality of data store cells are connected. Partial array self-refresh (PASR) configuration settings are independently made. In accordance with the PASR settings, the memory subblocks are addressed for refreshing.... Agent: Conversant Intellectual Property Management Inc.
20140233327 - Compensation scheme for non-volatile memory: Methods for performing parallel voltage and current compensation during reading and/or writing of memory cells in a memory array are described. In some embodiments, the compensation may include adjusting a bit line voltage and/or bit line reference current applied to a memory cell based on a memory array zone, a... Agent: Sandisk 3d LLC
20140233326 - Low-voltage current sense amplifer: In one embodiment, an integrated programmable device has a plurality of current sense amplifiers for reading data from non-volatile memory and a reference generator that provides common bias reference voltages to the sense amplifiers. The sense amplifiers can read data from the non-volatile memory at low power supply voltage levels... Agent: Lattice Semiconductor Corporation
20140233328 - Semiconductor device: A control logic unit generates a control signal which is activated while a power supply normally operates. A charge circuit is connected to a first node on a voltage control line supplied with a voltage generated by a voltage generation circuit, so that its capacitive element is charged with electric... Agent: Renesas Electronics Corporation
20140233330 - Write assist circuit, memory device and method: A write assist circuit includes a first switch, a second switch and a bias voltage circuit. The first switch connects a cell supply voltage node of a memory cell to a power supply voltage node in response to a write control signal having a first state, and disconnects the cell... Agent: Taiwan Semiconductor Manufacturing Company, Ltd.
20140233331 - Write control circuits and wire control methods: According to various embodiments, a write control circuit configured to control writing to a memory cell by applying a writing current to the memory cell may be provided. The write control circuit may include: a current application circuit configured to apply the writing current to the memory cell; a determination... Agent:
20140233332 - Semiconductor memory system: A semiconductor memory system includes a semiconductor memory configured to provide an external circuit with a plurality of refresh characteristic information and perform an auto-refresh operation in response to a plurality of auto-refresh commands, and a memory controller configured to provide the semiconductor memory with the plurality of auto-refresh commands... Agent:
20140233333 - Methods and apparatus for synchronizing communication with a memory controller: A memory controller receives data and phase-providing signals from a memory device. The phase-providing signal is not a clock signal, but is used by the memory controller to phase align a local data-sampling signal with the incoming data. The memory controller samples the data signal with the data-sampling signal. The... Agent: Rambus Inc.
20140233334 - Semiconductor device and method of controlling the same: A device includes a command decoder that is configured to output, in a normal operation mode, a precharge signal in response to a first type transition edge of a synchronous signal, and an active signal in response to a next first type transition edge that is next to the first... Agent: Elpida Memory, Inc.
20140233335 - Semiconductor devices: A plurality of memory chips each have an alert terminal that notifies the outside that the memory chip has detected a predetermined error. The plurality of memory chips are mounted on memory module 100. Memory module 100 has a first transmission line connected to an alert terminal of each of... Agent: Elpida Memory, Inc.
20140233336 - Sense amplifier circuit and semiconductor memory device: A semiconductor device may comprise a first bit line, a second bit line, a memory cell connected to the first bit line, a bit line sense amplifier circuit and a control circuit. The bit line sense amplifier circuit may be coupled to the memory cell. The bit line sense amplifier... Agent: Samsung Electronics Co., Ltd.
20140233337 - Nonvolatile memory device and memory system including the same: A nonvolatile memory device includes a memory cell array; and a high voltage generator arranged to generate a high voltage to be supplied to the memory cell array. The high voltage generator includes a pump unit block having a plurality of pump units supplied with an external voltage and at... Agent: Samsung Electronics Co., Ltd.
20140233338 - Memory apparatus and system with shared wordline decoder: A memory device includes wordline decoder circuits that share components between adjacent memory blocks. The wordline decoder circuits include multiple levels, where at least one level is split, driving half of the wordlines in one adjacent memory block and driving half of the wordlines in another adjacent memory block. Memory... Agent: Micron Technology, Inc.
20140233339 - Apparatus and method to reduce bit line disturbs: A non-volatile memory device comprising a memory cell array including a plurality of non-volatile memory cells arranged in rows and columns, wherein memory cells arranged in a same row share a word line and memory cells arranged in a same column share a bit line; and at least an address... Agent: Spansion LLC.
20140233340 - Row decoding circuit: A row decoding circuit including row decoding blocks is provided. Each of the row decoding blocks includes row decoders. Each of the row decoders receives a pre-charge signal, and includes an inverter, a selecting transistor and at least one switch transistors. The inverter receives the corresponding pre-charge signal, and outputs... Agent: Winbond Electronics Corp.08/14/2014 > 41 patent applications in 25 patent subcategories.
20140226392 - Arrays of vertically stacked tiers of non-volatile cross point memory cells and methods of reading a data value stored by an array of vertically stacked tiers of non-volatile cross point memory cells: An array of vertically stacked tiers of non-volatile cross point memory cells includes a plurality of horizontally oriented word lines within individual tiers of memory cells. A plurality of horizontally oriented global bit lines having local vertical bit line extensions extend through multiple of the tiers. Individual of the memory... Agent: Micron Technology, Inc.
20140226389 - Hash functions used to track variance parameters of resistance-based memory elements: Parameters indicative of resistance variance of the memory elements are tracked. The resistance variance affects values of data stored in the resistance-based memory elements. A hash function is performed for each memory element. The hash function returns a reference to one of a plurality of counter elements. A value of... Agent: Seagate Technology LLC
20140226391 - Method of programming a non-volatile resistive memory: mounting said matrix on a support, with the step of mounting comprising at least one of the following steps: a step of brazing, a step of welding.... Agent: Commissariat A L'energie Atomique Et Aux Ene Alt
20140226390 - Non-volatile memory system with reset control mechanism and method of operation thereof: A method of operation of a non-volatile memory system includes: providing a control field effect transistor having a source electrode and a body-tie electrode; coupling a resistive storage element to the source electrode; and opening a well switch coupled to the body-tie electrode for increasing a well voltage and resetting... Agent: Sony Corporation
20140226388 - Optimization of variable resistance memory cells: A data storage device may generally be constructed and operated with at least one variable resistance memory cell configured with non-factory operational parameters by a controller. The non-factory operational parameters are assigned in response to an identified variance from a predetermined threshold in at least one variable resistance memory cell.... Agent: Seagate Technology LLC
20140226393 - Temperature compensation of conductive bridge memory arrays: Methods for operating a semiconductor memory array including dynamically adjusting control line voltages (e.g., unselected word line or unselected bit line voltages) based on one or more array conditions associated with the semiconductor memory array are described. The one or more array conditions may include a temperature associated with the... Agent: Sandisk 3d LLC
20140226394 - Integrated circuit, method for driving the same, and semiconductor device: An integrated circuit which can be switched to a resting state and can be returned from the resting state rapidly is provided. An integrated circuit whose power consumption can be reduced without the decrease in operation speed is provided. A method for driving the integrated circuit is provided. The integrated... Agent: Semiconductor Energy Laboratory Co., Ltd.
20140226395 - Latch-based array with robust design-for-test (dft) features: A latch-based memory includes a plurality of slave latches arranged in rows and columns. Each column of slave latches receives a latched data signal from a corresponding master latch. Each row includes a clock gating circuit and a corresponding reset circuit. If a row is active for a write operation,... Agent: Qualcomm Incorporated
20140226396 - Tamper detection and response in a memory device: A technique for detecting tampering attempts directed at a memory device includes setting each of a plurality of detection memory cells to an initial predetermined state, where corresponding portions of the plurality of detection memory cells are included in each of the arrays of data storage memory cells on the... Agent: Everspin Technologies, Inc.
20140226397 - Nonvolatile memory device and control method thereof: A vertical nonvolatile memory device which includes a plurality of cell strings formed in a direction intersecting with a substrate is provided. The vertical nonvolatile memory device is configured to apply a non-selection read voltage to at least one selection line connected to a cell string from among the plurality... Agent:
20140226399 - System and method for reading memory cells by accounting for inter-cell interference: A system including a read module and a detector module. The read module is configured to generate a plurality of read signals by reading a plurality of memory cells located along a bit line or a word line. The detector module is configured to detect a sequence of data stored... Agent: Marvell World Trade Ltd.
20140226398 - Systems and methods to update reference voltages of non-volatile memory: A data storage device includes non-volatile memory and a controller. The controller is configured to read first data from the non-volatile memory. The first data indicates a first count of storage elements of the group that have a first activation status when sensed with a first reference voltage at a... Agent: Sandisk Technologies Inc.
20140226401 - Memory device and semiconductor device: A memory device in which data can be retained for a long time is provided. The memory device includes a memory element and a transistor which functions as a switching element for controlling supply, storage, and release of electrical charge in the memory element. The transistor includes a second gate... Agent: Semiconductor Energy Laboratory Co., Ltd.
20140226400 - Semiconductor device: According to one embodiment, a semiconductor device includes a nonvolatile memory, a volatile memory, and a controller. The controller is configured to transition a part of the volatile memory to a self-refresh mode when a request for stopping supplying of power to the nonvolatile memory is received.... Agent:
20140226405 - Bit line resistance compensation: Methods for compensating for variations in bit line resistance during sensing of memory cells are described. The variations in bit line resistance may occur die-to-die or plane-to-plane on the same die. In some embodiments, for each die or memory plane on a die, a plurality of bit line read voltages... Agent: Sandisk Technologies, Inc.
20140226402 - Fast-reading nand flash memory: In a flash memory two or more pages in a plane are read in rapid succession by maintaining global word line voltages throughout multiple page reads, and by simultaneously transitioning the old selected word line from a discrimination voltage to a read voltage and transitioning the new selected word line... Agent: Sandisk Technologies Inc.
20140226403 - Memory system and method of driving memory system using zone voltages: A method is provided for driving a nonvolatile memory device, including multiple strings, where each string is formed by penetrating plate-shaped word lines stacked on a substrate. The method includes configuring the word lines of a string in multiple zones based on zone configuration information, and applying zone voltages to... Agent:
20140226404 - Memory system performing multi-step erase operation based on stored metadata: A memory system, comprising a flash memory comprising multiple memory blocks, and a controller configured to erase each of the memory blocks using multiple steps. The controller stores, for each of the memory blocks, metadata indicating which of the multiple steps have been completed, and erases each of the memory... Agent:
20140226406 - Efficient smart verify method for programming 3d non-volatile memory: In a programming operation of a 3D stacked non-volatile memory device, an initial set of memory cells on a selected word line layer, involving fewer than all memory cells on a selected word line layer, are programmed first as a test case to determine optimal conditions for programming the remaining... Agent:
20140226407 - Nonvolatile semiconductor memory device: An erase verify operation is executed divided into at least a first erase verify operation and a second erase verify operation. The first erase verify operation is an operation that applies a verify read voltage only to a first group of memory cells among the plurality of memory cells included... Agent: Kabushiki Kaisha Toshiba
20140226409 - Mixed voltage non-volatile memory integrated circuit with power saving: An integrated circuit die has a first die pad for receiving a first voltage and a second die pad for receiving a second voltage. The second voltage is less than the first voltage and is generated by a voltage regulator that receives the first voltage. A first circuit which is... Agent:
20140226408 - Nonvolatile memory device: According to one embodiment, a nonvolatile memory device includes a core unit and a peripheral circuit unit. The core unit is configured to be capable of storing data. The peripheral circuit unit is configured to program and read the data to and from the core unit. The peripheral circuit unit... Agent: Kabushiki Kaisha Toshiba
20140226410 - Semiconductor integrated circuit adapted to output pass/fail results of internal operations: In a semiconductor integrated circuit, an internal circuit is capable of executing a first operation and a second operation concurrently, and an output circuit outputs to the outside of the semiconductor integrated circuit information indicating whether or not the first operation is being executed and information indicating whether or not... Agent: Kabushiki Kaisha Toshiba
20140226411 - Method of programming flash memory: A method of programming a NAND flash memory cell string. The method includes a pre-boost stage configured to elevate channel voltage of a selected memory cell, and a boost stage is introduced after the pre-boost stage. The pre-boost stage has at least the following steps of biasing a bit line... Agent: Macronix International Co., Ltd.
20140226412 - Data writing method, and memory control circuit unit and memory storage apparatus using the same: A data writing method for writing data into a memory cell of a rewritable non-volatile memory module, and a memory control circuit unit and a memory storage apparatus using the same area provided. The method includes recording a wear degree of the memory cell and detecting an operating temperature of... Agent: Phison Electronics Corp.
20140226414 - Group word line erase and erase-verify methods for 3d non-volatile memory: An erase operation for a 3D stacked memory device assigned storage elements to groups according to an expected erase speed. The storage elements are then erased according to their group to provide a more uniform erase depth and a tighter erase distribution. In one approach, the control gate voltages are... Agent: Sandisk Technologies Inc.
20140226413 - Non-volatile buffering to enable sloppy writes and fast write verification: Method and apparatus for managing data in a memory. In accordance with some embodiments, input write data having a selected logical address are stored in a rewriteable non-volatile (NV) buffer. A copy of the input write data is transferred to an NV main memory using a sloppy write process. A... Agent: Seagate Technology LLC
20140226415 - Non-volatile memory including bit line switch transistors formed in a triple-well: Non-volatile memory and methods of operating non-volatile memory reduce breakdown and leakage associated with bit line (BL) switch transistors. The BL switch transistors for a memory array are formed in a well that is electrically isolated from a well associated with the memory array. The well of the BL switch... Agent: Sandisk Technologies Inc.
20140226416 - Erase operation with controlled select gate voltage for 3d non-volatile memory: An erase process for a 3D stacked memory device controls a drain-side select gate (SGD) and a source-side select gate (SGS) of a NAND string. In one approach, SGD and SGS are driven to provide a predictable drain-to-gate voltage across the select gates while an erase voltage is applied to... Agent: Sandisk Technologies Inc.
20140226418 - Weak keeper circuit for memory device: A memory circuit is provided comprising a plurality of bit cells coupled to a bit line that permits accessing information from each of the plurality of bit cells. A sense inverter is coupled to an output of the bit line. A keeper circuit has an output coupled to the bit... Agent: Qualcomm Incorporated
20140226417 - Load and short current measurement by current summation technique: Methods for monitoring one or more load currents corresponding with one or more voltage regulators used during operation of a semiconductor memory are described. The one or more load currents may be due to the biasing of memory cells within a memory array or due to the presence of shorts... Agent: Sandisk 3d, LLC
20140226419 - Semiconductor apparatus: A semiconductor apparatus includes: a memory cell block configured to store data; a fuse block including a plurality of fuses configured to store fuse information; an I/O driver configured to output the data transmitted through a global line to a pad; and a fuse driver configured to output the fuse... Agent: Sk Hynix Inc.
20140226420 - Strobe-offset control circuit: A method of operation in a memory controller is disclosed. The method includes receiving a strobe signal having a first phase relationship with respect to first data propagating on a first data line, and a second phase relationship with respect to second data propagating on a second data line. A... Agent: Rambus Inc.
20140226421 - Clock signal generation apparatus for use in semiconductor memory device and its method: A clock signal generation apparatus for generating a reference clock signal for outputting data in synchronization with an external clock signal from a semiconductor memory device, including: a clock signal generation unit for receiving an internal clock signal to generate the reference clock signal according to a control signal; and... Agent: ConversantIPN.b. 868 Inc.
20140226423 - Device: Provided is a device, including: a first terminal which receives an external clock signal; a clock generation circuit connected to the first terminal to generate an internal clock signal based on the external clock signal; word lines and bit lines; amplifier circuits connected to the bit lines, respectively; and a... Agent: Elpida Memory, Inc.
20140226422 - Semiconductor memory device and method of testing the same: A semiconductor memory device including an open bit line structure is disclosed. The semiconductor memory device including an open bit line structure includes a first mat, a second mat contiguous to the first mat, a first sense amplifier coupled to a first bit line of the first mat, a second... Agent: Sk Hynix Inc.
20140226424 - Memory device and corresponding reading method: An electrically erasable and programmable non-volatile memory device includes memory cells arranged in rows and columns, and each column of memory cells is associated with a respective local bit line. The local bit lines are divided into packets of local bit lines, each packet of local bit lines associated with... Agent: Stmicroelectronics S.r.l.
20140226425 - Current mode sense amplifier with passive load: Memories, current mode sense amplifiers, and methods for operating the same are disclosed, including a current mode sense amplifier including cross-coupled p-channel transistors and a load circuit coupled to the cross-coupled p-channel transistors. The load circuit is configured to provide a resistance to control at least in part the loop... Agent: Micron Technology, Inc.
20140226426 - Protection for system configuration information: Systems and methods for detecting power attacks related to subnormal read voltage on an integrated circuit. Upon initiating power up of the integrated circuit and prior to reading configuration information from non-volatile memory (NVM), test cells associated with the NVM are read first. The test cells share a common power... Agent: Qualcomm Incorporated
20140226427 - Memory device word line drivers and methods: Memory subsystems and methods, such as those involving a memory cell array formed over a semiconductor material of a first type, such as p-type substrate. In at least one such subsystem, all of the transistors used to selectively access cells within the array are transistors of a second type, such... Agent: Micron Technology, Inc.
20140226428 - Semiconductor device, information processing system including same, and controller for controlling semiconductor device: A system includes a control chip includes a plurality of command terminals receiving a plurality of command signals, respectively; a command decoder coupled to the command terminals, the command decoder being configured to output an internal command in response to the command signals; and a layer address buffer configured to... Agent: Elpida Memory, Inc.Previous industry: Electric power conversion systems
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