|Static information storage and retrieval patents - Monitor Patents|
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Static information storage and retrievalBelow are recently published patent applications awaiting approval from the USPTO. Recent week's RSS XML file available below.
Listing for abstract view: USPTO application #, Title, Abstract excerpt,Patent Agent. Listing format for list view: USPTO National Class full category number, title of the patent application. 05/16/2013 > 48 patent applications in 29 patent subcategories.
20130121053 - Methods and circuits for limiting bit line leakage current in a content addressable memory (cam) device: A content addressable memory (CAM) device can include a number of bit lines. One or more of the bit lines can be connected to storage circuits of CAM cells in a corresponding column. Each CAM cell can include compare circuits that compare a stored value one or more compare data... Agent: Netlogic Microsystems, Inc.
20130121054 - Three-dimensional integrated circuit: A three-dimensional integrated circuit comprising a submicroscale integrated-circuit substrate and n nanoscale layers stacked above the submicroscale integrated-circuit substrate, a nanowire-junction memory element in each of which is independently controlled by two submicroscale subcomponents within the submicroscale integrated-circuit substrate, the first submicroscale subcomponent coupled through a first set of switches... Agent:
20130121055 - Word line driver cell layout for sram and other semiconductor devices: A word line driver cell suitable for RAM devices such as SRAM, static random access memory devices, is provided. The word line driver cell is compatible with double pattern processing techniques and enables the formation of all word lines from a single metal layer which, in turn, enables overlying and... Agent: Taiwan Semiconductor Manufacturing Co., Ltd.
20130121056 - Apparatuses and operation methods associated with resistive memory cell arrays with separate select lines: The present disclosure includes methods and apparatuses that include resistive memory. A number of embodiments include a first memory cell coupled to a data line and including a first resistive storage element and a first access device, a second memory cell coupled to the data line and including a second... Agent: Micron Technology, Inc.
20130121058 - Circuit and method for controlling write timing of a non-volatile memory: A circuit and a method for controlling the write timing of a non-volatile memory are provided. The method includes the following steps. First, a resistance state switching of at least one memory cell of the non-volatile memory executing a writing operation is monitored to output a control signal. The memory... Agent: Industrial Technology Research Institute
20130121063 - Memory device, semiconductor storage device, method for manufacturing memory device, and reading method for semiconductor storage device: A memory device that can prevent degradation in characteristics of a diode and the destruction due to the miniaturization includes: a substrate; first electrodes, a second electrode, and a third electrode that are stacked above the substrate; a variable resistance layer between the first and second electrodes; and a non-conductive... Agent:
20130121059 - Multi-valued logic device having nonvolatile memory device: A multi-valued logic device having an improved reliability includes a conversion unit configured to convert a multi level signal into a plurality of partial signals; and a plurality of nonvolatile memory devices configured to individually store the plurality of partial signals, wherein a number of bits of each of the... Agent: Samsung Electronics Co., Ltd.
20130121060 - Non-volatile memory elements and memory devices including the same: Non-volatile memory elements, memory devices including the same, and methods for operating and manufacturing the same may include a memory layer between a first electrode and a second electrode spaced apart from the first electrode. The memory layer may include a first material layer and a second material layer, and... Agent: Samsung Electronics Co., Ltd.
20130121061 - Nonvolatile memory cell comprising a diode and a resistance-switching material: A method is provided for programming a memory cell in a memory array. The memory cell includes a resistivity-switching layer of a metal oxide or nitride compound, and the metal oxide or nitride compound includes exactly one metal. The method includes programming the memory cell by changing the resistivity-switching layer... Agent: Sandisk 3d LLC
20130121057 - Resistor thin film mtp memory: An integrated circuit is formed having an array of memory cells located in the dielectric stack above a semiconductor substrate. Each memory cell has two adjustable resistors and two heating elements. A dielectric material separates the heating elements from the adjustable resistors. One heating element alters the resistance of one... Agent: Stmicroelectronics Pte Ltd.
20130121062 - Rewriting a memory array: A method for rewriting a memory array (408) with a number of memory elements (206) includes performing a rewrite process to change the memory array (408) from an initial state to a target state in a manner that avoids violating to a set of weight constraints at any time during... Agent:
20130121064 - Memory based illumination device: The invention contained herein provides electrical circuits and driving methods to operate a memory cell comprising a capacitance coupled to a breakover conduction switch such as a thyristor, DIAC or one or more complementary transistor pairs. The memory cell comprises a cell capacitance for storing a memory state and for... Agent:
20130121065 - Dynamic wordline assist scheme to improve performance tradeoff in sram: A dynamic wordline assist circuit for improving performance of an SRAM. An SRAM is disclosed that includes a plurality of memory cells, wherein each memory cell is coupled to a wordline and a pair of bitlines; and a wordline assist circuit coupled to the wordline, wherein the wordline assist circuit... Agent: International Business Machines Corporation
20130121066 - Circuit and method for generating a reference level for a magnetic random access memory element: A method of establishing a reference level includes providing first and second non-overlapping paths from a first node to a second node, providing first and second reference magnetic random access memory (MRAM) elements in the first path, providing third and fourth reference MRAM elements in the second path, measuring a... Agent: Qualcomm Incorporated
20130121067 - High speed low power magnetic devices based on current induced spin-momentum transfer: A high speed, low power method to control and switch the magnetization direction and/or helicity of a magnetic region in a magnetic device for memory cells using spin polarized electrical current. The magnetic device comprises a reference magnetic layer with a fixed magnetic helicity and/or magnetization direction and a free... Agent: New York University
20130121068 - Magnetic memory cell: The disclosed subject matter relates to a non-volatile memory bit cell (500 or 600) for solid-state data storage, including, e.g., an elongated magnetic element (102) or “dot”. For appropriate geometry and dimensions of the dot, a two-fold, energetically-degenerate micromagnetic configuration (100 or 200) can be stabilized. Such a stable configuration... Agent: City University Of Hong Kong
20130121069 - Internal voltage generating circuit of phase change random access memory device and method thereof: An internal voltage generating circuit includes a divided voltage generator configured to generate a divided voltage by dividing a feedback internal voltage level at a division ratio corresponding to an operation mode control signal, a voltage detector configured to detect a level of the divided voltage based on a reference... Agent: Sk Hynix Inc.
20130121070 - Memory device: A memory device includes first and second inverters cross-coupled between first and second nodes. The first inverter is configured to be supplied by a first supply voltage via a first transistor and the second inverter is configured to be supplied by the first supply voltage via a second transistor. A... Agent: Stmicroelectronics (crolles 2) Sas
20130121071 - Reducing effects of program disturb in a memory device: The programming disturb effects in a semiconductor non-volatile memory device can be mitigated by biasing unselected memory cells with a negative voltage while a well containing the memory cells receives a positive voltage. A selected memory cell in the well can be biased with a negative voltage while the well... Agent: Micron Technology, Inc.
20130121072 - Method for non-volatile memory with background data latch caching during read operations: Part of the latency from memory read or write operations is for data to be input to or output from the data latches of the memory via an I/O bus. Methods and circuitry are present for improving performance in non-volatile memory devices by allowing the memory to perform some of... Agent: Sandisk Technologies, Inc.
20130121073 - Semiconductor device: According to an embodiment, a semiconductor device includes a substrate, a connector, a volatile semiconductor memory element, multiple nonvolatile semiconductor memory elements, and a controller. A wiring pattern includes a signal line that is formed between the connector and the controller and that connects the connector to the controller. On... Agent:
20130121074 - Semiconductor device: According to an embodiment, a semiconductor device includes a substrate, a connector, a volatile semiconductor memory element, multiple nonvolatile semiconductor memory elements, and a controller. A wiring pattern includes a signal line that is formed between the connector and the controller and that connects the connector to the controller. On... Agent:
20130121075 - Systems and methods for operating multi-bank nonvolatile memory: A non-volatile memory system that has multiple memory banks initially assigns logical addresses to memory banks according to an assignment scheme, maintains this assignment for a period of time, then identifies frequently-written data (“hot-data”) assigned to a memory bank that is heavily worn over that period of time and reassigns... Agent:
20130121076 - Three dimensional stacked nonvolatile semiconductor memory: A three dimensional stacked nonvolatile semiconductor memory according to an example of the present invention includes a memory cell array comprised of first and second blocks. The first block has a first cell unit which includes a memory cell to be programmed and a second cell unit which does not... Agent: Kabushiki Kaisha Toshiba
20130121077 - Three dimensional stacked nonvolatile semiconductor memory: In a three dimensional stacked nonvolatile semiconductor memory according to the present invention, a first block has a selected first cell unit including a memory cell to be read and a non-selected second cell unit not including a memory cell to be read. A read potential or a transfer potential... Agent: Kabushiki Kaisha Toshiba
20130121078 - Three-dimensional array of re-programmable non-volatile memory elements having vertical bit lines and a single-sided word line architecture: A three-dimensional array especially adapted for memory elements that reversibly change a level of electrical conductance in response to a voltage difference being applied across them. Memory elements are formed across a plurality of planes positioned different distances above a semiconductor substrate. A two-dimensional array of bit lines to which... Agent: Sandisk 3d LLC
20130121079 - Nor flah memory cell and structure thereof: The present invention provides a NOR flash memory cell. The NOR flash memory cell includes a first transistor, a second transistor and at least one third transistor. The first transistor has a control terminal, a first terminal and a second terminal. The control terminal used to receive a word line... Agent: Ememory Technology Inc.
20130121080 - Adaptive estimation of memory cell read thresholds: A method for operating a memory (28) that includes a plurality of analog memory cells (32) includes storing data in the memory by writing first storage values to the cells. Second storage values are read from the cells, and a Cumulative Distribution Function (CDF) of the second storage values is... Agent: Apple Inc.
20130121081 - Nonvolatile semiconductor memory device: A nonvolatile semiconductor memory device includes a memory unit and a control unit. The memory unit includes a multilayer structure including electrode films and inter-electrode insulating films alternately stacked in a first direction; a semiconductor pillar piercing the multilayer structure in the first direction; a memory layer provided between the... Agent: Kabushiki Kaisha Toshiba
20130121082 - Method of operating nonvolatile memory device: A method of operating a nonvolatile memory device includes determining whether a program operation is performed on even memory cells coupled to even bit lines of a selected page, setting a coupling resistance value between odd bit lines of the selected page and page buffers depending on whether the program... Agent: Sk Hynix Inc.
20130121083 - Non-volatile memory device, method of operating the same, and electronic device having the same: In one embodiment, the method includes detecting a noise level of a common source line, and adjusting a frequency of program-verify operations on a memory cell during a programming loop based on the detected noise level.... Agent:
20130121084 - Method and apparatus to provide data including hard bit data and soft bit data to a rank modulation decoder: A method includes providing data including hard bit data and soft bit data to a rank modulation decoder.... Agent: Sandisk Technologies Inc.
20130121085 - Method of operating a split gate flash memory cell with coupling gate: A method of operating a memory cell that comprises first and second regions spaced apart in a substrate with a channel region therebetween, a floating gate disposed over the channel region and the first region, a control gate disposed over the channel region and laterally adjacent to the floating gate... Agent:
20130121086 - Memory configured to provide simultaneous read/write access to multiple banks: A memory includes at least first and second banks of single-port memory elements, a first local controller adapted to send read and write instructions to the first memory bank, and a second local controller adapted to send read and write instructions to the second memory bank. A global controller is... Agent: Qualcomm Incorporated
20130121088 - Memory word line boost using thin dielectric capacitor: A memory including a boost circuit configured to supply a voltage higher than a supply voltage to a word line. The boost circuit includes a first capacitor having a first capacitor dielectric thickness. The boost circuit further includes a transmission gate coupled to the word line and the first capacitor,... Agent: Taiwan Semiconductior Manufacturing Company, Ltd.
20130121087 - Semiconductor manufacturing method: A memory bit cell includes a latch, a write port coupled to the latch, and a read port coupled to the latch. The write port includes a first set of devices having a first threshold voltage and a second set of devices having a second threshold voltage that is greater... Agent: Taiwan Semiconductor Manufacturing Co., Ltd.
20130121089 - Systems and methods for reducing peak power consumption in a solid state drive controller: In accordance with an embodiment of the disclosure, systems and methods are provided for reducing an amount of peak power consumption in a device. In certain implementations, a first signal and a second signal are received, wherein the first signal and the second signal are indicative of amounts of power... Agent: Marvell World Trade Ltd.
20130121090 - Semiconductor memory device, operating method thereof, and data storage apparatus including the same: A semiconductor memory device includes memory cells arranged at regions where word lines and bit lines cross each other; a randomizing and de-randomizing circuit configured to perform a first randomizing operation on data to be programmed to the memory cells, based on a seed value, so as to generate first... Agent: Sk Hynix Inc.
20130121091 - System with controller and memory: According to the system of the present invention, data (DQ) signals are outputted/received between a controller 100 and a memory 200 based on a data strobe signal sent out from the controller 100. The data strobe signal is independently and completely separated from a clock signal. The data strobe signal... Agent: Elpida Memory, Inc.
20130121093 - Memory access control device and manufacturing method: A memory access control device including: a bit position information storage unit storing bit position information indicating one or more bit positions in a bit sequence of a predetermined length; a reading unit configured to attempt to read a bit sequence from the range specified by the logical address received... Agent:
20130121092 - Semiconductor device including plural semiconductor chips stacked to one another: Disclosed herein is a device that includes a first semiconductor chip outputting a read command and a clock signal, a plurality of second semiconductor chips stacked to the first semiconductor chip, and a signal path electrically connected between the first and second semiconductor chips. Each of the second semiconductor chips... Agent: Elpida Memory, Inc.
20130121096 - Delay locked loop implementation in a synchronous dynamic random access memory: A clock applying circuit for a synchronous memory is comprised of a clock input for receiving a clock input signal, apparatus connected to the synchronous memory for receiving a driving clock signal, and a tapped delay line for receiving the clock input signal for delivering the clock driving signal to... Agent: Mosaid Technologies Incorporated
20130121094 - Integrated circuit comprising a delay-locked loop: Embodiments of an integrated circuit (IC) comprising a delay-locked loop (DLL) are described. Some embodiments include first circuitry to generate a first clock signal by delaying an input clock signal by a first delay, second circuitry to determine a code based on the input clock signal and the first clock... Agent: Rambus Inc.
20130121095 - Memory controller, system including the controller, and memory delay amount control method: A DRAM coupled to a system LSI, the DRAM receiving a test pattern from the system LSI to store the test pattern, if a power source of the system LSI is turned on, outputting the stored test pattern to the system LSI, receiving a delay set value from the system... Agent: Renesas Electronics Corporation
20130121097 - Address output circuit and semiconductor memory device: A semiconductor memory device includes a signal generation unit configured to generate a toggling signal and first and second pulse signals in response to a test signal and a burst pulse signal. An address output unit may be configured to receive first to fourth input addresses and output sequentially first... Agent: Hynix Semiconductor Inc.
20130121098 - Serial memory with fast read with look-ahead: A serial memory may have memory arranged in a plurality of memory blocks, a serial interface for receiving a read instruction and associated memory address; and a controller configured to only store a plurality of most significant bits from each memory block which are accessed in parallel before an entire... Agent: Microchip Technology Incorporated
20130121099 - Amplifier circuit and semiconductor memory device: An amplifier circuit includes an amplification unit and a back-bias voltage providing unit. The amplification unit amplifies input data. The back-bias voltage providing unit provides selectively back-bias voltages of different levels to the amplification unit in an initial operation period of the amplification unit and a period after the initial... Agent:
20130121100 - Device and method to perform memory operations at a clock domain crossing: A device and method to perform memory operations at a clock domain crossing is disclosed. In a particular embodiment, a method includes providing a first clock signal to a write clock input of a memory to write data to the memory. The data is read from the memory according to... Agent: Qualcomm Incorporated05/09/2013 > 45 patent applications in 29 patent subcategories.
20130114322 - Associative memory: An associative memory that can reduce search errors is provided. An associative memory includes R distance/time conversion circuits DT1 to DTR. The R distance/time conversion circuits DT1 to DTR each include a NAND circuit 40 and N bit stages 41 to 4k. The N bit stages 41 to 4k delay... Agent: Hiroshima University
20130114323 - Semiconductor device and data storage apparatus: A semiconductor device according to an embodiment includes: a rectangular substrate having a first and a second principal surfaces ; a first semiconductor chip; one or more second semiconductor chips; and one or more third semiconductor chips. The substrate has first connection terminals connected to electrodes of the one or... Agent: Kabushiki Kaisha Toshiba
20130114324 - Integrated circuit comprising a fram memory and method for granting read-access to a fram memory: An electronic device includes an integrated circuit with a FRAM memory and an integrated capacitor connected between a power supply for the FRAM memory and ground. The integrated capacitor has a capacitance sufficient to store the charge necessary for a complete read-and-write-back cycle of the FRAM memory. When granting read-access... Agent: Texas Instruments Incorporated
20130114328 - Low-complexity electronic circuit and methods of forming the same: An electronic circuit such as a latch or a sequencer includes a plurality of transistors, all of the transistors being either NMOS transistors or PMOS transistors, and dissipates less than or approximately the same amount of power as an equivalent CMOS circuit.... Agent:
20130114329 - Multilayer memory array: A multilayer crossbar memory array includes a number of layers. Each layer includes a top set of parallel lines, a bottom set of parallel lines intersecting the top set of parallel lines, and memory elements disposed at intersections between the top set of parallel lines and the bottom set of... Agent:
20130114325 - Non-volatile random access memory coupled to a first, second and third voltage and operation method thereof: A non-volatile random access memory (NV-RAM) and an operation method thereof are provided. The NV-RAM includes a latch unit, a switch, and a first to fourth non-volatile memory elements. First terminals of the first and the third non-volatile memory elements respectively couple to a first voltage and a second voltage.... Agent: Industrial Technology Research Institute
20130114326 - Semiconductor memory apparatus and test circuit therefor: Disclosed is a semiconductor memory apparatus, including: a memory cell array configured to include a plurality of memory cells; a switching unit configured to be coupled to data input and output pads and control a data transfer path of data applied to the data input and output pads in response... Agent: Hynix Semiconductor Inc.
20130114327 - Variable resistance nonvolatile memory device: A variable resistance nonvolatile memory device including memory cells provided at cross-points of first signal lines and second signal lines, each memory cell including a variable resistance element and a current steering element connected to the variable resistance element in series, the variable resistance nonvolatile memory device including a write... Agent:
20130114331 - Control signal generation circuit and sense amplifier circuit using the same: A control signal generation circuit includes a voltage detection unit which detects a level of an external voltage and generates first and second detection signals and a control signal control unit which delays a sense amplifier enable signal in response to the first and second detection signals and generates first... Agent: Hynix Semiconductor Inc.
20130114330 - Semiconductor memory device and driving method thereof: In a conventional DRAM, a decrease in the capacitance of a capacitor causes an error in reading data. A plurality of memory blocks MB is connected to one bit line BL_m. Each memory block MB includes a sub bit line SBL, a plurality of memory cells, and a precharge transistor.... Agent: Semiconductor Energy Laboratory Co., Ltd.
20130114332 - Reducing read disturbs and write fails in a data storage cell: A data storage cell having a data line configured to transmit a data value to and from the storage cell, a feedback loop configured to store the data value, a first access device to provide access between the data line and a first point in the feedback loop, a second... Agent: Arm Limited
20130114333 - Semiconductor memory device and fabrication process thereof: A SRAM includes a first CMOS inverter of first and second MOS transistors connected in series, a second CMOS inverter of third and fourth MOS transistors connected in series and forming a flip-flop circuit together with the first CMOS inverter, and a polysilicon resistance element formed on a device isolation... Agent: Fujitsu Semiconductor Limited
20130114334 - Magnetoresistive random access memory cell with independently operating read and write components: A new class of the memory cell is proposed. There are two separated pulse data writing and sensing current paths. The in-plane pulse current is used to flip the magnetization direction of the perpendicular-anisotropy data storage layer sandwiched between a heavy metal writing current-carrying layer and a dielectric layer. The... Agent:
20130114335 - Memory sensing circuit: A sensing circuit includes a sense amplifier circuit having a first and second nodes through which a magnetic memory element is sensed. A first current source is coupled to the first node a second current source is coupled to the second node. A reference magnetic memory element has a resistance... Agent: Avalanche Technology, Inc.
20130114336 - Three port mtj structure and integration: A two-transistor one-MTJ (2T1MTJ) three port structure includes two separate pin layer structures coupled to one free layer structure. The pin layer structures may include an anti-ferromagnetic layer (AFM) layer coupled to a pin layer. The free layer structure includes free layer coupled to a barrier layer and a cap... Agent: Qualcomm Incorporated
20130114338 - Voltage supply controller, nonvolatile memory device and memory system: A nonvolatile memory device includes a voltage supply controller (VSC) detecting a level of a power supply voltage and generating a first internal voltage in response thereto. The VSC provides the first internal voltage at a level equal to an external high voltage when a power supply voltage is normally... Agent: Samsung Electronics Co., Ltd.
20130114339 - Storage apparatus and data control method: Data capacity efficiency is improved by de-duplicating data assigned with a code that is different for each data. A storage apparatus comprising a flash memory control device equipped with one or more flash memory modules, wherein the flash memory module comprises at least one flash memory chip for providing a... Agent: Hitachi, Ltd.
20130114340 - Secure memory which reduces degradation of data: A method for managing a non-volatile memory may include a first phase of writing data to a first bank of a memory plane of the non-volatile memory, and then a second phase of writing the same data to a second bank of the same memory plane of the non-volatile memory... Agent: Stmicroelectronics (rousset) Sas
20130114341 - Method and apparatus for indicating bad memory areas: Regardless of data values stored on data memory cells, all read operations on the data memory cells are disallowed. For example, current flow is disallowed through a string of the data memory cells and one or more select line memory cells. The particular select value stored in a first select... Agent: Macronix International Co., Ltd.
20130114342 - Defective word line detection: Methods and non-volatile storage systems are provided for detecting defects in word lines. A “broken” word line defect may be detected. Information may be maintained as to which storage elements were intended to be programmed to a tracked state. Then, after programming is complete, the storage elements are read to... Agent:
20130114344 - Erratic program detection for non-volatile storage: Methods and non-volatile storage systems are provided for determining erratically programmed storage elements, including under-programmed and over-programmed storage elements. Techniques do not require any additional data latches. A set of data latches may be used to store program data for a given memory element. This program data may be maintained... Agent:
20130114343 - Semiconductor device with one-time programmable memory cell including anti-fuse with metal/polycide gate: A one-time programmable (OTP) memory cell includes two transistors including a dual gate transistor. The dual gate transistor is formed using the same processing operations used to form floating gate transistors in other areas of the semiconductor device. The dual gate transistor includes an upper gate isolated from a floating... Agent: Wafertech, LLC
20130114345 - Nonvolatile memory device and driving method thereof: According to example embodiments, a nonvolatile memory device includes a plurality of strings having a plurality of serially-connected selection transistors and a plurality of memory cells connected in series to one end of the serially-connected selection transistors. A control logic is configured to perform a program operation for setting a... Agent:
20130114346 - Method of operating a flash eeprom memory: The invention is a new method for operating a flash EEPROM memory device and in particular for programming and erasing the device. The memory device has a first semiconductor region within a second semiconductor region, source and drain regions in the first semiconductor region, a well terminal inside the first... Agent:
20130114337 - Method of testing data retention of a non-volatile memory cell having a floating gate: A method of decreasing the test time to determine data retention (e.g. leakage current) of a memory cell having a floating gate for the storage of charges thereon. The memory cell is characterized by the leakage current having a rate of leakage which is dependent upon the absolute value of... Agent: Silicon Storage Technology, Inc.
20130114354 - Nonvolatile memory device and related method of operation: A memory device comprises a nonvolatile memory device and a controller. The nonvolatile memory comprises a first memory area comprising single-bit memory cells and a second memory area comprising multi-bit memory cells. The controller is configured to receive a first unit of write data, determine a type of the first... Agent: Samsung Electronics Co., Ltd.
20130114348 - Self refresh pulse generation circuit: A self refresh pulse generation circuit includes a control signal generator configured to generate a control signal asserted for an initial period of a self refresh mode, and a self refresh pulse generator configured to generate a self refresh pulse having a period controlled in response to the control signal,... Agent: Hynix Semiconductor Inc.
20130114351 - Semiconductor device, semiconductor system having the same and operating method thereof: A semiconductor device includes a data storage unit configured to receive input data, outputs the input data with a difference in voltage level between logic levels, and output comparison data whose logic level is distinguished from the input data; a test operation unit configured to determine a logic level of... Agent:
20130114352 - Semiconductor memory device: A semiconductor memory device includes a pipe latch circuit configured to receive parallel input data and output serial data or set an output terminal of the pipe latch circuit at a predetermined voltage level in response to an enable signal, and a synchronization circuit configured to output an output data... Agent:
20130114347 - Semiconductor memory device and semiconductor system: A semiconductor system includes a semiconductor memory device configured to, during a test mode, store received data in a memory cell in response to a write command, read the stored data as information data in response to a read command, and internally store the information data, in response to the... Agent: Hynix Semiconductor Inc.
20130114350 - Semiconductor memory device including initialization signal generation circuit: An initialization signal generation circuit includes: an initialization signal output unit configured to generate an initialization signal which is enabled during at least a portion of an auto refresh operation period of the initialization mode, in response to a flag signal; a refresh signal generation unit configured to generate a... Agent: Hynix Semiconductor Inc.
20130114349 - Semiconductor system including a controller and memory: A semiconductor system includes three or more memory chips and a controller with first and second memory buffers configured to communicate with the three or more memory chips. The first and second memory buffers alternately transmit data to sequentially communicate with the three or more memory chips.... Agent: Hynix Semiconductor Inc.
20130114353 - Memory methods and systems with adiabatic switching: A memory system includes wordlines and pairs of complementary bitlines that provide access to memory storage elements. Capacitive and resistive loads associated with wordlines and bitlines are driven relatively slowly between voltage levels to reduce peak current, and thus power dissipation. Power dissipation is further reduced by charging complementary bitlines... Agent: Rambus Inc.
20130114355 - Method for adjusting voltage characteristics of semiconductor memory element, method for adjusting voltage characteristics of semiconductor memory device, charge pump and method for adjusting voltage of charge pump: Voltages are applied to supply voltage application points of memory cells of an SRAM, a semiconductor substrate, a word line and bit lines so that voltage Vdd takes value V1, substrate voltage Vsub becomes 0 V, word line voltage Vw1 takes value V1, bit line voltage Vbll becomes 0 V,... Agent: Semiconductor Technology Academic Research Center
20130114356 - Semiconductor memory apparatus, and divisional program control circuit and program method therefor: A semiconductor memory apparatus includes a program pulse generation block configured to generate write control signals and a program completion signal; a divisional program control circuit configured to generate a divisional programming enable signal according to a predetermined number of program division times, in response to the program completion signal;... Agent: Hynix Semiconductor Inc.
20130114357 - Semiconductor memory apparatus, and successive program control circuit and program method therefor: A semiconductor memory apparatus includes a program pulse generation block configured to generate write control signals and a program completion signal in response to a programming enable signal; a successive program control circuit configured to generate a successive programming enable signal in response to received program addresses and data count... Agent: Hynix Semiconductor Inc.
20130114358 - Address decoding method and semiconductor memory device using the same: A semiconductor memory device includes: a strobe clock generator configured to generate a strobe clock signal having a delay time controlled according to a plurality of test mode signals which are selectively enabled in response to a read signal or write signal; an internal address generator configured to latch an... Agent: Hynix Semiconductor Inc.
20130114359 - Input/output circuit and method of semiconductor apparatus and system with the same: A system includes a controller which is capable of operating at one of a first speed and a second speed slower than the first speed; a semiconductor memory apparatus operating at the first speed; and an input/output device which is connected between the semiconductor memory apparatus and the controller, and... Agent: Sk Hynix Inc.
20130114360 - Method for detecting permanent faults of an address decoder of an electronic memory device: An embodiment of a method for detecting permanent faults of an address decoder of an electronic memory device including a memory block formed by a plurality of memory cells, including the steps of: selecting an address, which identifies a selected set of memory cells; writing at the selected address a... Agent: Stmicroelectronics S.r.l.
20130114361 - Sense amplifier having an isolated pre-charge architecture, a memory circuit incorporating such a sense amplifier and associated methods: Disclosed are a sense amplifier and a memory circuit that incorporates it. The amplifier comprises cross-coupled inverters, each with a pull-down transistor and a pull-up transistor connected in series. One inverter has a voltage-controlled switch controlling the electrical connection between drain nodes of the transistors. During a read operation, the... Agent: International Business Machines Corporation
20130114362 - Data transmission circuit: A data transmission circuit includes an enable signal generation unit configured to receive a first enable signal and generate a second enable signal having a pulse width controlled according to a swing width of data inputted through a first data line, and a sense amplification unit configured to sense and... Agent: Hynix Semiconductor Inc.
20130114363 - Multi-modal memory interface: A multi-modal memory interface that supports each of current-mode and voltage-mode signaling by a memory controller with a memory which includes one or more memory devices. In a first type of system, the memory interface is configured to provide differential current-mode signaling from the memory controller to a first type... Agent: Rambus Inc.
20130114364 - Semiconductor device performing refresh operation: Disclosed herein is a device that includes a first semiconductor chip. The first semiconductor chip includes a first data storage area storing data, a first refresh circuit repeating a first refresh operation on the first data storage area to make the first data storage area retain the data, a first... Agent: Elpida Memory, Inc.
20130114365 - Semiconductor memory device and method of driving the same: Disclosed is a semiconductor memory device, including a plurality of internal voltage generation units configured to be enabled in response to each of a plurality of decoding signals and to generate an internal voltage, a controller configured to generate a plurality of control signals in response to a power up... Agent:
20130114366 - Semiconductor device having plural selection lines selected based on address signal: Disclosed herein is a device that includes: a set of address terminals supplied with a set of address signals, each of the address signals being changed in logic level; memory mats to which address ranges are allocated, respectively, the address ranges being different from each other, each of the memory... Agent: Elpida Memory, Inc.05/02/2013 > 54 patent applications in 32 patent subcategories.
20130107602 - 3-d nonvolatile memory devices and methods of manufacturing the same: A three-dimensional (3-D) nonvolatile memory device includes a channel layer protruded from a substrate, a plurality of memory cells stacked along the channel layer, a source line coupled to the end of one side of the channel layer, a bit line coupled to the end of the other side of... Agent: Sk Hynix Inc.
20130107603 - Circuit and method for generating a read signal: A circuit includes a fuse circuit and a control circuit. The fuse circuit has an electrical fuse. The control circuit is configured to receive an input signal having an input pulse, and, based on a feedback signal from the fuse circuit, generates a read pulse smaller than the input pulse... Agent: Taiwan Semiconductor Manufacturing Company, Ltd.
20130107607 - Bipolar resistive-switching memory with a single diode per memory cell: According to various embodiments, a resistive-switching memory element and memory element array that uses a bipolar switching includes a select element comprising only a single diode that is not a Zener diode. The resistive-switching memory elements described herein can switch even when a switching voltage less than the breakdown voltage... Agent: Intermolecular, Inc.
20130107604 - Method for forming resistive switching memory elements with improved switching behavior: Methods for producing RRAM resistive switching elements having optimal switching behavior include crystalline phase structural changes. Structural changes indicative of optimal switching behavior include hafnium oxide phases in an interfacial region between a resistive switching layer and an electrode.... Agent: Intermolecular, Inc.
20130107606 - Nonvolatile latch circuit, nonvolatile flip-flop circuit, and nonvolatile signal processing device: A nonvolatile latch circuit according to the present invention wherein the outputs of an inverter circuit and other inverter circuit which are cross-coupled are connected to each other via a series circuit in which a transistor, a variable resistance element, and other transistor are connected in this order; a store... Agent:
20130107605 - Performing forming processes on resistive memory: The present disclosure includes apparatuses and methods for performing forming processes on resistive memory. A number of embodiments include applying a formation signal to the storage element of a resistive memory cell, wherein the formation signal includes a first portion having a first polarity and a first amplitude, a second... Agent: Micron Technology, Inc.
20130107608 - Sram cell with individual electrical device threshold control: A static random access memory cell is provided formed in a silicon layer over a buried oxide layer on a substrate and including first and second inverters each having a pull-up and pull-down transistor configured to form a cell node. Each of the pull-down transistors of the first and second... Agent: Globalfoundries Inc.
20130107609 - Static random access memory cell: A static random access memory cell comprising a first inverter, a second inverter, a first transistor, a second transistor, and a third transistor. The first inverter is cross-coupled with the second inverter. The first transistor is connected with a write word line, a write bit line, and a first output... Agent: National Tsing Hua University
20130107610 - Sram cell with individual electrical device threshold control: A static random access memory cell is provided that includes first and second inverters formed on a substrate each having a pull-up and pull-down transistor configured to form a cell node. Each of the pull-down transistors of the first and second inverters resides over first regions below the buried oxide... Agent: Globalfoundries Inc.
20130107616 - Magnetoresistive effect element and random access memory using same: A magnetoresistive effect element is provided that exhibits a low writing current density while maintaining a high TMR ratio. A laminated structure of a second ferromagnetic layer/a non-magnetic layer/a first ferromagnetic layer is employed as a recording layer. A material of bcc crystalline structure, such as CoFeB, is employed as... Agent:
20130107611 - Memory device with soft-decision decoding: According to embodiments of the present invention, a memory device with soft decision decoding is provided. The memory device includes a memory cell configured to store an input data bit; a memory sensor configured to read out a parameter associated with a state of the memory cell; a detector configured... Agent: Agency For Science, Technology And Research
20130107613 - Memory sensing circuit: A sensing circuit includes a sense amplifier circuit having a first and second nodes through which a magnetic memory element is sensed. A first current source is coupled to the first node a second current source is coupled to the second node. A reference magnetic memory element has a resistance... Agent: Avalanche Technology, Inc.
20130107614 - Memory sensing circuit: A sensing circuit includes a sense amplifier circuit having a first and second nodes through which a magnetic memory element is sensed. A first current source is coupled to the first node a second current source is coupled to the second node. A reference magnetic memory element has a resistance... Agent: Avalanche Technology, Inc.
20130107615 - Memory sensing circuit: A sensing circuit includes a sense amplifier circuit having a first and second nodes through which a magnetic memory element is sensed. A first current source is coupled to the first node a second current source is coupled to the second node. A reference magnetic memory element has a resistance... Agent: Avalanche Technology, Inc.
20130107612 - Spin-torque transfer magnetic random access memory (sttmram) device with shared transistor and minimal written data disturbance: A spin-torque transfer memory random access memory (STTMRAM) cell is disclosed comprising a selected magnetic tunnel junction (MTJ) identified to be programmed; a first transistor having a first port, a second port and a gate, the first port of the first transistor coupled to the selected MTJ; a first neighboring... Agent: Avalanche Technology, Inc.
20130107617 - Quantum memory: A quantum memory component including a quantum dot molecule having first and second quantum dots provided in respective first and second layers separated by a barrier layer; an exciton comprising an electron and hole bound state in said quantum dot molecule, the spin state of said exciton forming a qubit;... Agent: Kabushiki Kaisha Toshiba
20130107619 - Conditioning phase change memory cells: A method for conditioning at least one Phase Change Memory, PCM, cell. The PCM cell is characterized by a number of pre-defined characteristics or properties. For pre-conditioning, at least one conditioning pulse is applied to the PCM such that at least one selected characteristic of the number of pre-defined characteristics... Agent: International Business Machines Corporation
20130107618 - Modified reset state for enhanced read margin of phase change memory: Subject matter disclosed herein relates to techniques involving a structural relaxation (SR) phenomenon for increasing resistance of a Reset state of phase change memory.... Agent: Micron Technology, Inc.
20130107620 - Methods and apparatuses including a select transistor having a body region including monocrystalline semiconductor material and/or at least a portion of its gate located in a substrate: Some embodiments include apparatuses and methods having a memory cell string including memory cells located in different levels of the apparatuses and a select transistor coupled to the memory cell string. In at least one of such apparatuses, the select transistor can include a body region including a monocrystalline semiconductor... Agent:
20130107625 - Flash memory apparatus and method for controlling flash memory apparatus: The invention provides a flash memory apparatus. In one embodiment, the flash memory apparatus comprises a flash memory and a flash memory controller. The flash memory comprises a write circuit and a memory cell array comprising a plurality of memory cells, wherein the write circuit is coupled to the memory... Agent: Silicon Motion, Inc.
20130107623 - Memory cell sensing: This disclosure concerns memory cell sensing. One or more methods include determining a data state of a first cell coupled to a first data line in response to a request to sense a data state of a second cell coupled to a second data line, applying a reference voltage to... Agent: Micron Technology, Inc.
20130107624 - Semiconductor memory device and operation method thereof: A programming method of a semiconductor memory device including memory cells of a first data distribution and a second data distribution includes forming an initialization distribution between the first data distribution and the second data distribution, and performing a programming operation by using the initialization distribution as a reference.... Agent:
20130107626 - Methods for segmented programming and memory devices: Methods for segmented programming, program verify, and memory devices are disclosed. One such method for programming includes biasing memory cells with a programming voltage and program verifying the memory cells with a plurality of ramped voltage signal segments, wherein each ramped voltage signal segment has a different start voltage and... Agent: Micron Technology, Inc.
20130107627 - Back-biasing word line switch transistors: Back biasing word line switch transistors is disclosed. One embodiment includes word line switch transistors that are in a well in a substrate. A memory array having non-volatile storage devices may be in a separate well in the substrate. The well of the word line switch transistors may be biased... Agent:
20130107629 - Nonvolatile memory devices and operating methods thereof: According to example embodiments of inventive concepts, a nonvolatile memory device includes a memory cell array including a plurality of memory cells; a word line driver configured to at least one of select and unselect a plurality of word lines connected with the plurality of memory cells, respectively, and to... Agent: Samsung Electronics Co., Ltd.
20130107628 - Selective word line erase in 3d non-volatile memory: An erase process for a 3D stacked memory device allows a portion of a block of memory cells to be erased. In one approach, in a U-shaped NAND string configuration, memory cells in the drain- or source-side columns are erased. In another approach, such as in a U-shaped or a... Agent:
20130107631 - Method of programming a split gate non-volatile floating gate memory cell having a separate erase gate: A non-volatile memory cell includes first and second regions and a channel region therebetween, a word line gate over a first portion of the channel region, a floating gate over another portion of the channel region and adjacent to the word line gate, a coupling gate over the floating gate,... Agent: Silicon Storage Technology, Inc.
20130107632 - Mixed voltage non-volatile memory integrated circuit with power saving: An integrated circuit die has a first die pad for receiving a first voltage and a second die pad for receiving a second voltage. The second voltage is less than the first voltage. A first circuit which is operable at the first voltage is in the integrated circuit die. A... Agent: Silicon Storage Technology, Inc.
20130107630 - Non-volatile memory devices having vertical drain to gate capacitive coupling: Vertically fabricated non-volatile memory devices having capacitive coupling between a drain region and a floating gate. A two terminal programmable non-volatile device includes a floating gate disposed vertically about a substrate, wherein the floating gate comprises a first side, a second side, and a bottom portion. A source region is... Agent: Invensas Corporation
20130107633 - Nonvolatile memory device and reading method thereof: In a method of reading a nonvolatile memory device, the method comprising, a reading operation of reading data of a selected memory cell; and a read retry operation of performing one or more read operations by changing a non-selection read voltage applied to non-selected memory cells until the read operation... Agent: Hynix Semiconductor Inc.
20130107621 - Built-in self trim for non-volatile memory reference current: A non-volatile memory built-in self-trim mechanism is provided by which product reliability can be improved by minimizing drift of reference current used for accessing the non-volatile memory and for performing initial trimming of the reference current. Embodiments perform these tasks by using an analog-to-digital converter to provide a digital representation... Agent:
20130107622 - Sequence detection for flash memory with inter-cell interference: A system including a read module and a sequence detector module. The read module is configured to read a plurality of memory cells located along a bit line or a word line of a memory array and to generate a plurality of read signals. The sequence detector module is configured... Agent: Marvell World Trade Ltd.
20130107634 - Nonvolatile semiconductor memory device: According to an aspect of the present invention, it is provided: a nonvolatile semiconductor memory device comprising: a plurality of bit lines arranged in a first direction; a plurality of source lines arranged in the first direction, the plurality of source lines being parallel to the plurality of bit lines,... Agent: Genusion, Inc.
20130107635 - Common doped region with separate gate control for a logic compatible non-volatile memory cell: An array of memory cells, in which one or more memory cells have a common doped region. Each memory cell includes a transistor with a floating gate, source and drain regions, and separate gate and drain voltage controls. Each memory cell also includes a coupling capacitor electrically coupled to and... Agent: Invensas Corporation
20130107637 - Memory program discharge circuit of bit lines with multiple discharge paths: A memory integrated circuit has an array of nonvolatile memory cells, bit lines accessing the array of nonvolatile memory cells, and bit line discharge circuitry. The bit lines have multiple discharge paths for a bit line at a same time, during a program operation.... Agent:
20130107636 - Semiconductor memory device: A semiconductor memory device includes a memory bank configured to store data, a buffering unit including a plurality of buffers, which are disposed to extend to a X-axis of the memory bank to store data transferred from the memory bank, a plurality of data transmission lines configured to transfer the... Agent: Sk Hynix Inc.
20130107639 - Semiconductor memory device and operation method thereof: A semiconductor memory device includes a memory cell block including memory cells, a random value generation circuit configured to generate random value data using a page address and a column address, a page buffer section connected to bit lines of the memory cell block and configured to store input data... Agent:
20130107638 - Semiconductor storage device: A semiconductor storage device according to the present embodiment includes a plurality of memory units respectively comprising a plurality of memory cells. A data bus is shared by the memory units and transfers data from the memory units or to the memory units. A timing controller includes a delay time... Agent: Kabushiki Kaisha Toshiba
20130107640 - Apparatuses, integrated circuits, and methods for measuring leakage current: Methods, apparatuses, and integrated circuits for measuring leakage current are disclosed. In one such example method, a word line is charged to a first voltage, and a measurement node is charged to a second voltage, the second voltage being less than the first voltage. The measurement node is proportionally coupled... Agent: Micron Technology, Inc.
20130107641 - Semiconductor system including semiconductor device: A semiconductor system includes a controller configured to apply code signals for setting levels of a reference voltage and data, and to receive output data. The semiconductor system also includes a semiconductor device configured to receive the data for the respective levels of the reference voltage set according to the... Agent: Hynix Semiconductor Inc.
20130107642 - Voltage generator of nonvolatile memory device: A voltage generator of a nonvolatile memory device includes a pump circuit for generating a pump output voltage by performing a pumping operation and raise or maintain the output voltage in response to a double enable signal or a single enable signal, a first regulator for comparing a first division... Agent:
20130107643 - Semiconductor memory device and driving method thereof: A semiconductor memory device using a termination scheme in a global data line includes a global data line and a data line drive unit. The global data line transfers data between an interface region and a plurality of core regions each having a memory bank. The data line drive unit... Agent:
20130107644 - Storage device, control method of storage device, and control method of storage control device: Memory cell regions as units of erasing operation are sectors S, and units of reading operation and/or writing operation are blocks B0 to B3 in a sector, in which a block address BA for selecting one of blocks B0 to B3 is held in block address buffer (BAB) 3. Holding... Agent: Spansion LLC
20130107645 - Nonvolatile memory and writing method thereof, and semiconductor device: A write-once memory can be written only once to each memory cell; therefore, a defective bit cannot be detected by an actual inspection of writing. Accordingly, as described above, the measures, in which a redundant circuit is provided and the defective bit is modified before shipping, cannot be taken; thus,... Agent: Semiconductor Energy Laboratory Co., Ltd.
20130107647 - Semiconductor device and method of operating the same: The present disclosure relates to a semiconductor device and a method of operating the semiconductor device. The semiconductor device includes a ROM for storing a program algorithm, an erase algorithm, a reading algorithm, and a reset algorithm and outputting ROM data corresponding to a selected algorithm, a program counter for... Agent: Sk Hynix Inc.
20130107646 - Semiconductor device and testing method thereof: A semiconductor device comprises a plurality of cell blocks activated in response to a plurality of selection signals, respectively, a pre-selection signal generator configured to generate a plurality of pre-selection signals corresponding to the cell blocks, respectively, and activate at least two of the pre-selection signals by decoding addresses in... Agent:
20130107648 - Memory device, semiconductor memory device and control method thereof: A semiconductor memory device comprises a memory cell array, first and second bit lines, first and second amplifiers, and a sense amplifier control circuit. An amplifying element in the first sense amplifier amplifiers the signal of the first bit line and converts it into an output current. The second bit... Agent: Elpida Memory, Inc.
20130107649 - Semiconductor device including test circuit and burn-in test method: A semiconductor device includes a test circuit configured to generate a buffer control signal in response to input data, decode test commands in response to the buffer control signal, and generate test mode signals and a counting enable signal for counting row addresses and column addresses; and a data input/output... Agent: Hynix Semiconductor Inc.
20130107650 - Semiconductor device having hierarchical bit line structure: A device includes a plurality of restoring circuits each provided for an associated one of local bit lines, remaining one or ones of the restoring circuits other than the restoring circuit provided for the selected one of the local bit lines being configured to receive, through remaining one or ones... Agent:
20130107651 - Semiconductor device with reduced leakage current and method for manufacture the same: A semiconductor device with reduced leakage current and a method of manufacturing these reduced leakage current semiconductor devices are disclosed. The reduced leakage current semiconductor devices may be used for both static circuits and dynamic circuits. The reduced leakage current semiconductor devices reduce leakage current in the device when the... Agent: Cold Brick Semiconductor, Inc.
20130107652 - Semiconductor memory device: A semiconductor memory device including a memory cell array including at least one word line, at least one cell bit line, and at least one memory cell that is disposed in a region where the at least one word line and the at least one cell bit line cross each... Agent:
20130107653 - Nonvolatile memory having stacked structure and related method of operation: A method is provided for operating a nonvolatile memory comprising memory cells stacked on a substrate. The method comprises counting a number of program loops performed in a first program operation of selected memory cells connected to a selected wordline, and controlling an increment of a program voltage between successive... Agent:
20130107654 - Semiconductor memory apparatus, high voltage generation circuit, and program method thereof: A high voltage generation circuit includes: a high voltage generator configured to boost an input voltage and generate first and second high voltages; and a high voltage transmitter configured to drive the first and second high voltages at the same time and generate a selected word line voltage and an... Agent: Hynix Semiconductor Inc.
20130107655 - Lookahead scheme for prioritized reads: A circular queue implementing a scheme for prioritized reads is disclosed. In one embodiment, a circular queue (or buffer) includes a number of storage locations each configured to store a data value. A multiplexer tree is coupled between the storage locations and a read port. A priority circuit is configured... Agent:04/25/2013 > 37 patent applications in 24 patent subcategories.
20130100722 - Three-dimensional non-volatile memory device, memory system including the same, and method of manufacturing the same: A 3D non-volatile memory device including a substrate that includes a first region and a second region; a pipe channel film that is formed on the substrate in the first region; a pipe gate that substantially encloses the pipe channel film; and a driving gate that is formed on the... Agent: Sk Hynix Inc.
20130100723 - Semiconductor memory device and driving method thereof: A semiconductor memory device in which capacitance of a capacitor is lower and integration degree is higher. A plurality of memory blocks is connected to one bit line BL_m. A memory block MB_n_m includes a sub bit line SBL_n_m, a write switch, and a plurality of memory cells. A sub... Agent: Semiconductor Energy Laboratory Co., Ltd.
20130100724 - High density molecular memory storage with read and write capabilities: A memory element is provided that includes a ferromagnetic (FM) layer having one or more ferromagnetic materials. One or more first molecule layers are positioned on the FM layer where charge transfer and interface chemistry between the one or more first molecule layers and FM layer induces a magnetic moment... Agent: Massachusetts Institute Of Technology
20130100726 - Multi-level memory cell with continuously tunable switching: The present disclosure provides a data storage device that includes multi-level memory cells. The data storage device may include circuitry configured to write data to the multi-level memory cell. The write circuitry may include compliance circuitry configured to implement continuously tunable switching. The write circuitry may be configured to select... Agent:
20130100727 - Overwriting a memory array: A data storage system including a memory array including a plurality of memory devices programmable in greater than two states. A read/write control module may overwrite data in the memory array without violating a constraint during the overwrite process. The memory array may be an m×n memory array.... Agent:
20130100725 - System and method for mram having controlled averagable and isolatable voltage reference: A memory has a plurality of non-volatile resistive (NVR) memory arrays, each with an associated reference voltage generating circuit coupled by a reference circuit coupling link to a reference line, the reference coupled to a sense amplifier for that NVR memory array. Reference line coupling links couple the reference lines... Agent: Qualcomm Incorporated
20130100729 - Dynamic memory cell provided with a field-effect transistor having zero swing: A memory cell is provided with a transistor which includes source and drain electrodes formed in a semiconductor film by respectively N-doped and P-doped areas. The transistor includes first and second devices for generating a potential barrier in the semiconductor film. The two potential barriers are shifted laterally and are... Agent: Commissariat A L'energie Atomique Et Aux Energies Alternatives
20130100728 - Semiconductor device and method for forming the same: A method for forming a semiconductor device is disclosed. An anti-fuse is formed at a buried bit line such that the area occupied by the anti-fuse is smaller than that of a conventional planar-gate-type anti-fuse, and a breakdown efficiency of an insulation film is increased. This results in an increase... Agent: Hynix Semiconductor Inc.
20130100731 - Independenty-controlled-gate sram: The present invention provides an IG 7T FinFET SRAM, which adopts independently-controlled-gate super-high-VT FinFETs to achieve a stacking-like property, whereby to eliminate the read disturb and half-select disturb. Further, the present invention uses keeper circuits and read control voltage to reduce leakage current of the bit lines during read. Furthermore,... Agent:
20130100730 - Method and apparatus for word line suppression: A memory access operation on a bit cell of a digital memory, e.g., a static random access memory (SRAM), is assisted by reducing the word line control voltage for reading and boosting it for writing, thus improving data integrity. The bit cell has cross coupled inverters for storing and retrieving... Agent: Taiwan Semiconductor Manufacturing Co., Ltd.
20130100732 - Array structural design of magnetoresistive random access memory (mram) bit cells: Spin Transfer Torque Magnetoresistive Random Access Memory (STT-MRAM) bit cells are disclosed. The bit cells include a source line formed in a first plane and a bit line formed in a second plane. The bit line has a longitudinal axis that is parallel to a longitudinal axis of the source... Agent: Qualcomm Incorporated
20130100733 - Memory device and electronic apparatus: A memory device includes: a memory including a first magnetic layer having no retaining force and a second magnetic layer having a retaining force, the first magnetic layer and the second magnetic layer being stacked; a first magnet to magnetize the first magnetic layer in a first direction; and a... Agent: Fujitsu Limited
20130100736 - Mapping between two buses using serial addressing bits: A solution is provided to flexibly choose a combination of flash memory devices to reduce the overall cost of the flash memory devices or increase the overall utilization of the flash memory devices, while satisfying the capacity requirements for the flash memory devices in a system design, wherein a decoding... Agent:
20130100737 - Nonvolatile memory device and related method of operation: A nonvolatile memory comprises a memory block having memory cells stacked in a three dimensional structure. The nonvolatile memory device performs an erase operation to erase a selected sub block among sub blocks of the memory block, a verification operation to determine whether program states of memory cells of an... Agent:
20130100739 - Semiconductor device: The present invention provides a semiconductor device having a nonvolatile memory function capable of shortening an erase time and executing data access efficiently. When, under the control of a command register/control circuit, an erase voltage is applied to an embedded erase gate wiring disposed in a memory cell boundary region,... Agent: Renesas Electronics Corporation
20130100738 - Three-dimensional nonvolatile memory devices: A three-dimensional (3-D) nonvolatile memory device includes channel layers protruded from a substrate, word line structures configured to include word lines stacked over the substrate, first junctions and second junctions formed in the substrate between the word line structures adjacent to each other, source lines coupled to the first junctions,... Agent: Sk Hynix Inc.
20130100741 - 3-d nonvolatile memory device and method of manufacturing the same, and memory system including the 3-d nonvolatile memory device: A three-dimensional (3-D) nonvolatile memory device includes vertical channel layers protruded from a substrate, interlayer insulating layers and memory cells, which are alternately stacked along the vertical channel layers, and select transistors including planar channel layers, each contacted with at least one of the vertical channel layers and being parallel... Agent:
20130100740 - Compact sense amplifier for non-volatile memory suitable for quick pass write: A compact and versatile sense amp is presented. Among its other features this sense amp arrangement provides a way to pre-charge bit lines while doing data scanning. Another feature is that the sense amp circuit can provide a way to set three different bit line levels used in the quick... Agent:
20130100743 - Method for operating a semiconductor structure: A method for operating a semiconductor structure is provided. The semiconductor structure includes a first conductor extending in a first direction, a second conductor extending in a second direction different from the first direction, and a dielectric layer between the first conductor and the second conductor. The method for operating... Agent: Macronix International Co., Ltd.
20130100742 - Nonvolatile memory device: A nonvolatile memory device is provided. The device may include a plurality of cell strings that are configured to share a bit line, word lines, and selection lines. Each of the cell strings may include a plurality of memory cells connected in series to each other and a string selection... Agent: Samsung Electronics Co., Ltd.
20130100734 - Apparatus and method for trimming reference cell in semiconductor memory device: A method of trimming a reference cell in a semiconductor memory device comprises the steps of: generating a reference current based on a bias voltage applied to the reference cell; generating a first current and a second current based on the value of a control voltage and the resistance of... Agent: Elite Semiconductor Memory Technology, Inc.
20130100735 - Flash memory device and operating method for concurrently applying different bias voltages to dummy memory cells and regular memory cells during erasure: Integrated circuit flash memory devices, such as NAND flash memory devices, include an array of regular flash memory cells, an array of dummy flash memory cells and an erase controller. The erase controller is configured to concurrently apply a different predetermined bias voltage to the dummy flash memory cells than... Agent: Samsung Electronics Co., Ltd.
20130100744 - Compact sense amplifier for non-volatile memory: A compact and versatile sense amp is presented. Among its other features this sense amp arrangement provides a way to pre-charge bit lines while doing data scanning. Another feature is that the sense amp circuit can provide a way to set three different bit line levels used in the quick... Agent:
20130100745 - Method and apparatus of performing an erase operation on a memory integrated circuit: Various discussed approaches include an improved grouping of edge word lines and center word lines of an erase group during erase verify and erase sub-operations of an erase operation. In another approach, changed voltage levels of edge word lines to address the over-erase issue of the erase group, and also... Agent:
20130100749 - Nano-sense amplifier: A sense amplifier for a series of cells of a memory, including a writing stage comprising a CMOS inverter, the input of which is directly or indirectly connected to an input terminal of the sense amplifier, and the output of which is connected to an output terminal of the sense... Agent: Soitec
20130100750 - Semiconductor device: Disclosed is a semiconductor device which is intended to reduce the total number of storage element blocks that constitute a desired logic circuit. The semiconductor device includes N address lines (N is an integer equal to two or more), N data lines, and a plurality of storage sections. Each of... Agent: Taiyo Yuden Co., Ltd.
20130100748 - Semiconductor memory device and method for driving the same: In a conventional DRAM, data read errors are more likely to occur along with miniaturization of DRAM. A small change in the potential of a first bit line is inverted by a first inverter constituted by an n-channel transistor and a p-channel transistor, and is output to a second bit... Agent: Semiconductor Energy Laboratory Co., Ltd.
20130100747 - Semiconductor memory device and method of operating the same: A semiconductor memory device includes a memory cell array having memory cells coupled to a plurality of word lines and a peripheral circuit group configured to supply a pass voltage to unselected word lines among the plurality of word lines, wherein the peripheral circuit group stepwise raises the pass voltage... Agent:
20130100746 - Methods and apparatus of stacking drams: Large capacity memory systems are constructed using stacked memory integrated circuits or chips. The stacked memory chips are constructed in such a way that eliminates problems such as signal integrity while still meeting current and future memory standards.... Agent: Google Inc.
20130100751 - Precharge signal generation circuit, semiconductor device including the same, and method for generating precharge signal: A precharge signal generation circuit includes a control signal generation unit configured to activate a control signal in response to a read command or write command and a precharge signal generation unit configured to use a clock signal in a period when the control signal is activated to activate a... Agent:
20130100752 - Method of restoring reconstructed memory spaces: A method of restoring reconstructed memory spaces is applied for restoring usable memory spaces in an inked die to form the memory with a standardized or non-standardized memory capacity. The method comprises the steps of scanning at least one selected from a block, a page and a cell in a... Agent: FluiditechIPLimited
20130100753 - Data transmission circuit and semiconductor apparatus using the same: A data transmission circuit includes a read data transmission unit configured to, when a read signal is asserted, detect and amplify a voltage level of a first data line, transmit an amplified voltage level to a second data line, and substantially prevent a voltage level of the second data line... Agent: Hynix Semiconductor Inc.
20130100754 - Non-volatile semiconductor memory device and method of reading data thereof: A memory string includes a semiconductor layer, a charge accumulation layer, and a conductive layer. The semiconductor layer extends in a direction perpendicular to the semiconductor substrate and functions as a body of a memory cell. The charge accumulation layer may accumulate charges. The conductive layer sandwiches the charge accumulation... Agent: Kabushiki Kaisha Toshiba
20130100755 - Semiconductor memory device implementing comprehensive partial array self refresh scheme: A semiconductor memory device performing a comprehensive partial self refresh (CPSR) scheme, in which a CPSR operation of not performing a self refresh operation on the segments included in each bank is disclosed. The semiconductor memory device includes a mask information register configured to generate mask information by storing information... Agent: Samsung Electronics Co., Ltd.
20130100756 - Electrical fuse memory arrays: A mechanism of reconfiguring an eFuse memory array to have two or more neighboring eFuse bit cells placed side by and side and sharing a program bit line. By allowing two or more neighboring eFuse bit cells to share a program bit line, the length of the program bit line... Agent: Taiwan Semiconductor Manufacturing Company, Ltd.
20130100757 - Dual-port memory and a method thereof: A dual-port memory is provided. The dual-port memory includes a first single-port memory and a second single-port memory. The first single-port memory is configured to store data in an even address of the dual-port memory. The second single-port memory is configured to store data in an odd address of the... Agent: O2micro Inc.
20130100758 - Local word line driver: A memory circuit with a word line driver and control circuitry is disclosed. The word line driver receives a first voltage reference signal, a second voltage reference signal, and an input signal. The word line driver has an output coupled to a word line. The control circuitry is configured to... Agent:Previous industry: Electric power conversion systems
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