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Static information storage and retrieval

Below are recently published patent applications awaiting approval from the USPTO. Recent week's RSS XML file available below.
Listing for abstract view: USPTO application #, Title, Abstract excerpt,Patent Agent. Listing format for list view: USPTO National Class full category number, title of the patent application.
  
09/25/2014 > 48 patent applications in 30 patent subcategories.

20140286072 - Identifying a result using multiple content-addressable memory lookup operations: In one embodiment, a first search operation is performed based on a base lookup word on a first plurality of content-addressable memory entries of an overall plurality of priority-ordered content-addressable memory entries to identify a first matching entry and a corresponding first overall search position of the first matching entry... Agent: Cisco Technology, Inc., A Corporation Of California

20140286073 - Semiconductor device and method for driving semiconductor device: To provide a semiconductor device which can write and read a desired potential. The semiconductor device includes a first transistor (Tr), a second Tr, and a capacitor. In the semiconductor device, operation of writing data is performed by a first step and a second step. In the first step, a... Agent: Semiconductor Energy Laboratory Co., Ltd.

20140286074 - System and memory module: A system includes: a controller, a first memory module connected to the controller through a first data bus, and a second memory module connected to the controller through a second data bus, wherein the first memory module includes: first and second memory chips; a first data terminal connected to the... Agent: Ps4 Luxco S.a.r.l.

20140286075 - Resistance change memory: According to one embodiment, a memory includes a memory cell array including blocks arranged in a column direction, first and second main global conductive lines each extending from a first end to a second end of the memory cell array in the column direction, a first resistance change element connected... Agent:

20140286076 - Semiconductor device: A nonvolatile semiconductor device which can be driven at low voltage is provided. A nonvolatile semiconductor device with low power consumption is provided. A Schmitt trigger NAND circuit and a Schmitt trigger inverter are included. Data is held in a period when the supply of power supply voltage is continued,... Agent: Semiconductor Energy Laboratory Co., Ltd.

20140286082 - Memory device: According to one embodiment, a memory device includes a memory cell, a sense amplifier, and a resistor. The sense amplifier includes a first input and a second input, outputs a signal in accordance with a difference between the first and second inputs, and is selectively coupled at a second input... Agent:

20140286079 - Nonvolatile semiconductor memory device and method of controlling the same: c

20140286078 - Resistance change memory: According to one embodiment, a memory includes a resistance change element connected between first and second conductive lines, a write buffer which writes data in the resistance change element by flowing a write current to the resistance change element through the first and second conductive lines in a writing, a... Agent:

20140286080 - Resistance change memory: According to one embodiment, a resistance change memory includes the following configuration. A first inverter includes first input and first output terminals and first and second voltage terminals. A second inverter includes second input and second output terminals and third and fourth voltage terminals. The second input terminal is connected... Agent:

20140286081 - Resistance change memory: According to one embodiment, a resistance change memory includes a memory cell, a sense amplifier and a global bit line. The memory cell is disposed at a location where a local bit line and a word line intersect each other. The memory cell is connected to both the local bit... Agent:

20140286077 - Resistance change type memory: According to one embodiment, a resistance change type memory includes a first and a second bit lines, a memory cell connected between the first and second bit lines and including a variable resistance element as a memory element and a first select element including a first control terminal connected to... Agent:

20140286083 - Systems and methods of pipelined output latching involving synchronous memory arrays: Systems and methods of synchronous memories and synchronous memory operation are disclosed. According to one illustrative implementation, a memory device is disclosed comprising memory circuitry having a memory output, the memory circuitry including a sense amplifier having a first output and a second output, a first data path coupled to... Agent: Gsi Technology, Inc.

20140286084 - Magnetoresistive element: According to one embodiment, a magnetoresistive element comprises a storage layer having perpendicular magnetic anisotropy with respect to a film plane and having a variable direction of magnetization, a reference layer having perpendicular magnetic anisotropy with respect to the film plane and having an invariable direction of magnetization, a tunnel... Agent:

20140286088 - Memory device: According to one embodiment, a memory device includes a memory cell, a sense amplifier, unit structures and a reference signal generator. Each structure includes a first end, a first transistor, a first local line, a variable resistance element, a second transistor, a second local line, and a third transistor coupled... Agent:

20140286085 - Power supply circuit and protection circuit: According to one embodiment, a power supply circuit includes a first circuit connected to a first line, to which a power supply voltage is applied, and a second line, and a power supply clamp circuit connected to the first and second lines. The power supply clamp circuit includes a current... Agent:

20140286086 - Semiconductor memory device: According to one embodiment, a semiconductor memory device includes first word lines connected to a memory cell array, second word lines connected to a redundancy area, a first row decoder configured to perform selecting from the first word lines based on a row address, a judgment circuit configured to determine... Agent:

20140286087 - Semiconductor memory device: According to one embodiment, a semiconductor memory device includes a memory cell array, a buffer configured to hold data input to an input/output circuit and to hold data read from the memory cell array, and a controller configured to receive a first command and an address from the outside and... Agent:

20140286089 - Semiconductor integrated circuit system and method for driving the same: A semiconductor integrated circuit system includes a phase-change line including a first phase-change area constituting a first memory cell and a second phase-change area constituting a second memory cell, a write current providing unit configured to phase-change a selected one of the first and second phase-change areas, and a phase-change... Agent:

20140286090 - Semiconductor integrated circuit system and method for driving the same: A semiconductor integrated circuit system includes a phase-change line including a first phase-change area constituting a first memory cell and a second phase-change area constituting a second memory cell, a write current providing unit configured to phase-change a selected one of the first and second phase-change areas, and a phase-change... Agent: Sk Hynix Inc.

20140286092 - Memory kink checking: This disclosure concerns memory kink checking. One embodiment includes selectively applying one of a plurality of voltages to a first data line according to a programming status of a first memory cell, wherein the first memory cell is coupled to the first data line and to a selected access line.... Agent: Micron Technology, Inc.

20140286094 - Data modulation for groups of memory cells: Methods, devices, and systems for data modulation for groups of memory cells. Data modulation for groups of memory cells can include modulating N units of data to a combination of programmed states. Each memory cell of a group of G number of memory cells can be programmed to one of... Agent: Micron Technology, Inc.

20140286093 - Semiconductor memory device: According to one embodiment, a semiconductor memory device includes a NAND string and a sense amplifier. The NAND string includes a memory cell transistor to be capable of holding any of three or more levels of values. The NAND string includes one end connected to a bit line and the... Agent: Kabushiki Kaisha Toshiba

20140286095 - Non-volatile semiconductor memory device: A non-volatile semiconductor memory device includes first through third memory strings, a first word line group shared by first and second memory strings and a second word line group shared by second and third memory strings, the first and second word line groups extending in a first direction and disposed... Agent: Kabushiki Kaisha Toshiba

20140286096 - Memory device and method of controlling leakage current within such a memory device: A memory device includes an array of memory cells arranged as a plurality of rows and columns, each row being coupled to an associated read word line, and each column forming at least one column group, where the memory cells of each column group are coupled to an associated read... Agent: Arm Limited

20140286097 - Thermally assisted flash memory with diode strapping: A memory includes an array of memory cells including rows and columns. The memory includes circuitry coupled to the word lines applying a first bias voltage to a first set of spaced-apart locations on a word line or word lines in the array, while applying a second bias voltage different... Agent: Macronix International Co., Ltd.

20140286098 - Nonvolatile semiconductor memory device: A nonvolatile semiconductor memory device according to an embodiment includes a memory string having a plurality of electrically rewritable memory transistors connected in series therein. The memory string includes a first semiconductor layer including a columnar portion extending in a perpendicular direction to a substrate; a tunnel insulating film formed... Agent: Kabushiki Kaisha Toshiba

20140286099 - Semiconductor memory device, controller, and memory system: A semiconductor memory device includes a memory cell array that is capable of storing data in a nonvolatile manner, and a control section that controls data access to the memory cell array. The memory cell array stores the same data redundantly in a plurality of pages. The control section executes... Agent: Kabushiki Kaisha Toshiba

20140286100 - Nonvolatile semiconductor memory device: A nonvolatile semiconductor memory device includes a control circuit configured to control a soft program operation of setting nonvolatile memory cells to a first threshold voltage distribution state of the nonvolatile memory cells. When a characteristic of the nonvolatile memory cells is in a first state, the control circuit executes... Agent: Kabushiki Kaisha Toshiba

20140286101 - Back bias during program verify of non-volatile storage: Different back bias (or body bias) conditions are applied to a non-volatile storage system during different program verify operations of a programming operation. A back bias may be applied during verify of an intermediate state (e.g., a lower page, middle page). The intermediate state is a state that exists during... Agent: Sandisk Technologies Inc.

20140286091 - Semiconductor integrated circuit: A semiconductor integrated circuit includes a reference voltage generation circuit configured to generate a reference voltage, and a voltage changing circuit configured to generate a second voltage from a first voltage based on a difference between the second voltage and the reference voltage and apply the second voltage to a... Agent: Kabushiki Kaisha Toshiba

20140286102 - Method of optimizing solid state drive soft retry voltages: A method of optimizing solid state drive (SSD) soft retry voltages comprises limiting a number of voltage reads and properly spacing and determining the reference voltage at which each voltage is read based on desired Bit Error Rate (BER) and channel throughput. The method determines each reference voltage for a... Agent: Lsi Corporation

20140286103 - Non-volatile semiconductor memory device: A non-volatile semiconductor memory device includes a memory cell configured to allow electrical writing and erasing, a bit line configured to transmit a potential corresponding to data stored in the memory cell in a column direction, a sense amplifier circuit configured to detect a potential of the bit line, and... Agent: Kabushiki Kaisha Toshiba

20140286104 - Non-volatile semiconductor memory device: According to one embodiment, a non-volatile semiconductor memory device which is provided with a memory cell array, bit lines, word lines, and a sense amplifier circuit is presented. The memory cell array includes memory cells. The bit lines are electrically connected to the memory cells. The word lines are electrically... Agent: Kabushiki Kaisha Toshiba

20140286106 - Memory devices having source lines directly coupled to body regions and methods: Memory devices, memory cell strings and methods of operating memory devices are shown. Configurations described include directly coupling an elongated body region to a source line. Configurations and methods shown should provide a reliable bias to a body region for memory operations such as erasing.... Agent:

20140286105 - Nand flash memory unit, operating method and reading method: A NAND flash memory unit, an operating method and a reading method are provided. The NAND flash memory unit includes a plurality of gate layers, a tunnel layer, a charge trapping layer, a conductor layer and a second dielectric layer. A first dielectric layer is included between two adjacent gate... Agent:

20140286107 - Memory system and control method therefor: A memory system includes a plurality of memory devices having data terminals that are commonly connected to a memory controller. Each of the memory devices includes a data output circuit that outputs read data that is read from a memory cell array in response to a read command to the... Agent:

20140286109 - Semiconductor device including output circuit constituted of plural unit buffer circuits in which impedance thereof are adjustable: A semiconductor device includes an output circuit having a plurality of unit buffer circuits, an impedance of each unit buffer circuit of the plurality of unit buffer circuits being adjustable, a control circuit configured to selectively activate one or more unit buffer circuits of the plurality of unit buffer circuits,... Agent:

20140286108 - Semiconductor memory device: According to one embodiment, a semiconductor memory device includes n (n being a natural number of 2 or more) data retention circuits connected to a data input/output terminal; n buses connected respectively to the n data retention circuits; m×n data latch circuits connected to the buses, with m (m being... Agent: Kabushiki Kaisha Toshiba

20140286110 - Semiconductor memory device: A semiconductor memory device comprises: a plurality of on-die termination circuits connected to each of a plurality of input/output pads; and a control circuit for controlling the on-die termination circuit. The on-die termination circuit comprises: a pull-up element connected between a first terminal and an output terminal; and a pull-down... Agent: Kabushiki Kaisha Toshiba

20140286111 - Domain crossing circuit of semiconductor apparatus: A domain crossing circuit of a semiconductor apparatus includes a delay-locked loop block configured to generate a delay-locked loop clock signal in response to a clock signal and a clock enable signal; a clock enable block configured to generate the clock enable signal in response to the clock signal and... Agent:

20140286112 - Semiconductor device: Disclosed herein is an apparatus that includes a first semiconductor chip including a first electrode, and a second semiconductor chip including a second electrode connected to the first electrode. One of the first and second semiconductor chips includes a first temperature sensor circuit generating a first detection signal, the first... Agent: Micron Technology, Inc.

20140286113 - Semiconductor device having roll call circuit: Disclosed herein is an apparatus that includes: a plurality of memory banks each including a plurality of memory cells; a plurality of redundant circuits each allocated to an associated one of the plurality of memory banks to replace a defective memory cell among the plurality of memory cells included in... Agent: Micron Technology, Inc.

20140286114 - Semiconductor device, method for inspecting the same, and method for driving the same: A method for limiting writing of data to a specific memory cell without disconnecting a wiring of a memory cell array or placing a prober in contact with a memory cell, a row, or a column is provided. Row address data and column address data of a memory cell to... Agent: Semiconductor Energy Laboratory Co., Ltd.

20140286115 - Nonvolatile random access memory: According to one embodiment, a memory includes a memory cell array with banks, each bank including rows, a first word lines provided in corresponding to the rows, an address latch circuit which latches a first row address signal, a row decoder which activates one of the first word lines, and... Agent:

20140286116 - Noise tolerant sense circuit: A device and a method for a sense circuit have been disclosed. In an implementation, the sense circuit includes a sense amplifier and at least one decoupling device. The decoupling device is coupled to the sense amplifier through at least one reference line. The sense amplifier reads a data value... Agent: Stmicroelectronics International N.v.

20140286117 - Semiconductor memory with sense amplifier: In an exemplary aspect, the present invention provides a semiconductor memory device including sense amplifiers that drive bit lines to which memory cells are connected, and driver transistors that supply a power supply to the sense amplifiers, wherein the sense amplifiers are arranged in rows and constitutes a first sense-amplifier... Agent: Renesas Electronics Corporation

20140286118 - Semiconductor device verifying signal supplied from outside: A method for accessing a semiconductor device having a memory array, includes receiving a chip select signal, receiving a command signal and an address signal, receiving a verification signal, calculating an error signal based on the address signal, the command signal, and the verification signal, generating an internal chip select... Agent:

20140286119 - Memory devices, systems and methods employing command/address calibration: During a command/address calibration mode, a memory controller may transmit multiple cycles of test patterns as signals to a memory device. Each cycle of test pattern signals may be transmitted at an adjusted relative phase with respect to a clock also transmitted to the memory device. The memory device may... Agent: Samsung Electronics Co., Ltd.

  
09/18/2014 > 171 patent applications in 52 patent subcategories.

20140268972 - Tcam with efficient multiple dimension range search capability: An embodiment of the invention includes first and second Ternary Content Addressable Memories (TCAMs), a first vector, and TCAM match-merge unit. Each of the TCAMs includes a plurality of words, stores TCAM match entries and outputs a TCAM match signal for each word in the plurality of words. The first... Agent: Texas Instruments Incorporated

20140268971 - Tcam with efficient range search capability: An embodiment of the invention includes a ternary content addressable memory (TCAM) that has input search data bits, TCAM words and range search input data bits. Each TCAM word is operable to store a match pattern and provide a match output. The match output indicates a match when the match... Agent: Texas Instruments Incorporated

20140268973 - 276-pin buffered memory card with enhanced memory system interconnect: An embodiment is a memory card including a rectangular printed circuit card having a first side and a second side, a first length of between 151.35 and 161.5 millimeters, and first and second ends having a second length smaller than the first length. The memory card also includes a first... Agent: International Business Machines Corporation

20140268974 - Apparatuses and methods for improving retention performance of hierarchical digit lines: Apparatuses and methods for improving retention performance of hierarchical digit lines are disclosed herein. An example apparatus may include a first digit line portion and a second digit line portion. The apparatus may further include a first selector configured to selectively couple the first digit line portion to the second... Agent: Micron Technology, Inc.

20140268977 - Electrical lines with coupling effects: A circuit includes a first line, a second line, a first sub-circuit, and a second sub-circuit. The first line has a first signal. The second line has a second signal. The first sub-circuit is configured to generate a first output signal. The second sub-circuit is configured to generate a second... Agent: Taiwan Semiconductor Manufacturing Company, Ltd.

20140268976 - Ground-referenced single-ended memory interconnect: A system is provided for transmitting signals. The system comprises a first processing unit, a memory subsystem, and a package. The first processing unit is configured to include a first ground-referenced single-ended signaling (GRS) interface circuit. The memory subsystem is configured to include a second GRS interface circuit. The package... Agent: Nvidia Corporation

20140268975 - Integrated circuit system with non-volatile memory stress suppression and method of manufacture thereof: An integrated circuit system, and a method of manufacture thereof, including: an integrated circuit die; a non-volatile memory cell in the integrated circuit die and having a bit line for reading a data condition state of the non-volatile memory cell; and a voltage clamp in the integrated circuit die, the... Agent: Sony Corporation

20140268979 - Semiconductor device and semiconductor package: A semiconductor device includes a system-on-chip (SOC) and at least one wide input/output memory device. The SOC includes a plurality of SOC bump groups which provide input/output channels, respectively, independent from each other. The at least one wide input/output memory device is stacked on the system-on-chip to transmit/receive data to/from... Agent: Samsung Electronics Co., Ltd.

20140268978 - Semiconductor memory device having asymmetric access time: A semiconductor memory device may include a plurality of data input/output DQ pads and a plurality of first and second memory cell arrays. Each path of a first set of data paths from each of the plurality of first memory cell arrays to a corresponding DQ pad is physically shorter... Agent: Snu R&db Foundation

20140268980 - Memory chip package, memory system having the same and driving method thereof: A memory chip package includes memory chips stacked, electrically connected one another, and configured to input and output an optical signal through an optical line formed by a via penetrating the memory chips. The memory chips input and output optical signals with different wavelengths, and each of the memory chips... Agent:

20140268981 - Racetrack memory with electric-field assisted domain wall injection for low-power write operation: Embodiments are directed to injecting domain walls in a magnetic racetrack memory. In some embodiments, a racetrack comprising a nanowire is coupled with a gate in order to manipulate an anisotropy associated with the nanowire. The racetrack and gate is coupled with a pinning layer configured to establish a magnetization... Agent: International Business Machines Corporation

20140268982 - Racetrack memory with electric-field assisted domain wall injection for low-power write operation: Embodiments are directed to injecting domain walls in a magnetic racetrack memory. In some embodiments, a racetrack comprising a nanowire is coupled with a gate in order to manipulate an anisotropy associated with the nanowire. The racetrack and gate is coupled with a pinning layer configured to establish a magnetization... Agent: International Business Machines Corporation

20140268983 - Otprom array with leakage current cancelation for enhanced efuse sensing: Disclosed herein are memory cell arrays and methods for operating memory cell arrays. In one embodiment, a memory cell array includes a plurality of bitcells, a first bitline, a second bitline, a first wordline and a second wordline. The bitcells are arranged into rows and columns and each include a... Agent: Globalfoundries, Inc.

20140268984 - Semiconductor device and electronic apparatus: Provided is a semiconductor device that includes: a storage element including a first terminal, a second terminal, and a third terminal, and in which a resistance state between the second terminal and the third terminal is changed from a high resistance state to a low resistance state based on a... Agent: Sony Corporation

20140268986 - Read only memory array architecture and methods of operation: An encoded ROM array structure couples a first one of a first set of bitlines to a second one of a second set of bitlines through a transistor when the wordline connected to the gate terminal of that transistor is asserted. This encoded arrangement can be extended to any number... Agent:

20140268985 - Read only memory bitline load-balancing: A Read Only Memory (ROM) bitline cell apparatus and programming method therefore. The programming methodology ensures a ROM structure having open state and/or breaks in the diffusion and/or dummy wordline rows to provide bitline load balancing. The ROM bitline cell apparatus and programming method exhibits improved load balancing for any... Agent: International Business Machines Corporation

20140268987 - Thermally-assisted mram with ferromagnetic layers with temperature dependent magnetization: A technique is provided for a thermally assisted magnetoresistive random access memory device. The device has a synthetic antiferromagnetic layer disposed on an antiferromagnetic layer. The synthetic antiferromagnetic layer has a first ferromagnetic storage layer, a non-magnetic coupling layer disposed on the first ferromagnetic storage layer, and a second ferromagnetic... Agent: International Business Machines Corporation

20140269001 - Amorphous silicon rram with non-linear device and operation: A non-volatile memory device includes a resistive switching device having a first electrode, a second electrode, and a resistive switching element, wherein the resistive switching element comprises a silicon material disposed in an overlapping region between the first electrode and the second electrode, wherein the second electrode comprises at least... Agent: Crossbar, Inc.

20140268991 - Chalcogenide material and methods for forming and operating devices incorporating the same: Embodiments disclosed herein may relate to a memory cell comprising a chalcogenide material mixture having a chalcogenide composition and a metallic glass-forming composition.... Agent: Micron Technology, Inc.

20140269007 - Complementary metal oxide or metal nitride heterojunction memory devices with asymmetric hysteresis property: A resistive memory device is disclosed. The resistive memory device comprises one or more metal oxide layers. The resistive memory device displays a property of asymmetric hysteresis loop formation when positive and negative electrical biases are applied across the device.... Agent:

20140269005 - Electronic devices having semiconductor memory units and method for fabricating the same: The disclosed technology provides an electronic device and a fabrication method thereof. An electronic device according to an implementation of the disclosed technology may include: a first interlayer insulating layer formed over a substrate; first and second contact plugs passing through the first interlayer insulating layer to contact the substrate... Agent: Sk Hynix Inc.

20140269006 - Fast read speed memory device: A memory device includes an array of resistive memory cells. Each resistive memory cell in the array includes a first resistive memory element, a second resistive memory element electrically coupled with the first resistive memory element at a common node between a first terminal of the first resistive memory element... Agent: Rambus Inc.

20140269003 - Memory cell with volatile and non-volatile storage: The invention concerns a non-volatile memory element comprising: first and second transistors (106, 108) forming an inverter (104) coupled between a first storage node (112) and an output (110) of the memory element; a third transistor (116) coupled between the first storage node (112) and a first supply voltage (GND,... Agent: Centre National De La Recherche Scientifique

20140268992 - Memory cells, memory systems, and memory programming methods: Memory cells, memory systems and methods are described. In one embodiment, a memory cell includes electrodes and a memory element, and a first electrically conductive structure is formed within dielectric material providing the memory element in a low resistance state as a result of a first voltage of a first... Agent: Micron Technology, Inc.

20140269004 - Method for improving data retention of reram chips operating at low operating temperatures: Programming a resistive memory structure at a temperature well above the operating temperature can create a defect distribution with higher stability, leading to a potential improvement of the retention time. The programming temperature can be up to 100 C above the operating temperature. The memory chip can include embedded heaters... Agent: Intermolecular, Inc.

20140269008 - Non-volatile memory using bi-directional resistive elements: A memory cell includes a first bidirectional resistive memory element (BRME), and a second BRME, a first storage node, and a second storage node . A resistive memory write to the cell includes placing the first BRME and the second BRME in complementary resistive states indicative of the value being... Agent: Freescale Semiconductor, Inc.

20140268993 - Nonvolatile resistive memory element with an oxygen-gettering layer: A nonvolatile resistive memory element includes an oxygen-gettering layer. The oxygen-gettering layer is formed as part of an electrode stack, and is more thermodynamically favorable in gettering oxygen than other layers of the electrode stack. The Gibbs free energy of formation (ΔfG°) of an oxide of the oxygen-gettering layer is... Agent: Intermolecular Inc.

20140268997 - Programming two-terminal memory cells with reduced program current: Providing for programming a two-terminal memory cell array with low sneak path current is described herein. Groups of two-terminal memory cells can be arranged into blocks or sub-blocks, along sets of bitlines and local wordlines. Further, groups of local wordlines within a given sub-block can be electrically isolated from bitlines... Agent: Crossbar, Inc.

20140268988 - Resistive memory cell: The present invention discloses a resistive memory cell, including a unipolar type RRAM and a MOS transistor as a selection transistor serially connected to the unipolar type RRAM, wherein the MOS transistor is fabricated over a partial depletion SOI substrate and provides a large current for program and erase of... Agent: Peking University

20140268989 - Resistive non-volatile memory: A multi-bit NVM cell includes a storage unit having resistive elements, such as phase change resistive elements. The NVM cell may be configured as a single port or dual port multi-bit cell. The NVM cell includes primary and secondary cell selectors. The primary selector selects the multi-bit cell while the... Agent: Globalfoundries Singapore Pte. Ltd.

20140268998 - Rram with dual mode operation: A two-terminal memory cell comprises a dual mode of operation in a unipolar mode and bipolar mode for a programming or On-state and for an erase or Off-state of the cell. The two-terminal memory cell is field programmable and can be flexibly designed or integrated into existing architecture. The two-terminal... Agent: Crossbar, Inc.

20140268995 - Semiconductor device and electronic device including the same: A semiconductor device includes: a vertical electrode provided over a substrate; a variable resistance layer provided at least a sidewall of the vertical electrode; a plurality of horizontal electrodes extending from the sidewall of the vertical electrode and having the variable resistance layer interposed; a transition metal oxide layer provided... Agent:

20140268999 - Semiconductor storage device: According to one embodiment, provided is a semiconductor storage device that includes a control circuit to control the voltage that is applied to the memory cell. The control circuit is configured to execute a reset operation that applies a reset voltage of a first polarity to a selected memory cell... Agent: Kabushiki Kaisha Toshiba

20140269000 - Semiconductor storage device: According to one embodiment, a semiconductor storage device includes multiple memory cells that include a variable resistance element and a control circuit to control the voltage that is applied to the memory cell. The control circuit is configured so that, during the set operation in which the variable resistance element... Agent: Kabushiki Kaisha Toshiba

20140268990 - Stackable non-volatile memory: A multi-bit NVM cell includes a storage unit having resistive elements, such as phase change resistive elements. The NVM cell may be configured as a single port or dual port multi-bit cell. The NVM cell includes a cell selector. The cell selector selects the multi-bit cell. When appropriate signals are... Agent: Globalfoundries Singapore Pte. Ltd.

20140269002 - Two-terminal memory with intrinsic rectifying characteristic: Providing for two-terminal memory having an inherent rectifying characteristic(s) is described herein. By way of example, the two-terminal memory can be a resistive switching device having one or more “on” states and an “off” state, to facilitate storage of digital information. A conductive filament can be electrically isolated from an... Agent: Crossbar, Inc.

20140268996 - Variable resistance memory device and method of driving the same: A variable resistance memory device and a driving method thereof are provided. The variable resistance memory device includes a base layer and a pillar-shaped gate electrode formed on the base layer and extending substantially perpendicular to a surface of the base layer. A current transfer layer is formed to surround... Agent: Sk Hynix Inc.

20140268994 - Write-time based memristive physical unclonable function: A physical unclonable function (PUF) device consisting of a hybrid CMOS-memristor circuit that leverages variations in the required write-time of a memristor. Variations in the time required to write, or SET, a memristor from a high to low resistance state arise from variability in physical parameters such as the memristor... Agent:

20140269009 - Dram with pulsed sense amp: Disclosed is a pulsed sense amplifier approach for resolving data on a bit line.... Agent:

20140269010 - Ground-referenced single-ended memory interconnect: A system is provided for transmitting signals. The system includes a ground-referenced single-ended signaling (GRS) driver circuit that is configured to pre-charge a first capacitor to store a first charge between a first output node and a first reference node based on a first input data signal during a first... Agent: Nvidia Corporation

20140269012 - Ground-referenced single-ended system-on-package: A system of interconnected chips comprising a multi-chip module (MCM) includes a first processor chip, a system function chip, and an MCM package configured to include the first processor chip and the system function chip. The first processor chip is configured to include a first ground-referenced single-ended signaling (GRS) interface... Agent:

20140269014 - Memory device: A memory device with a novel structure that is suitable for a register file is provided. The memory device includes a first memory circuit and a second memory circuit. The first memory circuit includes a first logic element and a second logic element each of which is configured to perform... Agent: Semiconductor Energy Laboratory Co., Ltd.

20140269013 - Memory device and semiconductor device: A memory device includes a first memory circuit including a silicon transistor, a selection circuit including a silicon transistor, and a second memory circuit including oxide semiconductor transistors and a storage capacitor, in which one terminal of the storage capacitor is connected to a portion where two oxide semiconductor transistors... Agent: Semiconductor Energy Laboratory Co., Ltd.

20140269011 - Multi-phase ground-referenced single-ended signaling: A system includes a control circuit and first, second, and third ground-referenced single-ended signaling (GRS) driver circuits that are each coupled to an output signal. The control circuit is configured to generate a first, second, and third set of control signals that are each based on a respective phase of... Agent:

20140269015 - Use of hydrocarbon nanorings for data storage: Hydro-carbon nanorings may be used in storage. Sufficiently cooled, an externally hydrogen doped carbon nanoring may be used to create a radial dipole field to contain streams of electrons. Similarly, an internally hydrogen doped carbon nanoring may be used to create a radial dipole field to contain streams of positrons.... Agent:

20140269023 - Biasing bulk of a transistor: A circuit comprises a first transistor of a first type, a second transistor of a second type, and a third transistor of the first type or the second type. The first transistor and the second transistor form an inverter. The third transistor is coupled with an output of the inverter.... Agent: Taiwan Semiconductor Manufacturing Company, Ltd.

20140269019 - Dual-port static random access memory (sram): In one embodiment, a memory cell circuit for storing data includes a pair of cross-coupled inverters for storing states of the memory cell circuit. Access devices provide access to the pair of cross-coupled inverters. The memory cell circuit also includes a set of electrically inactive p-type metal oxide semiconductor (PMOS)... Agent:

20140269024 - Memory device and method for writing therefor: A method of writing a memory cell includes, during a write cycle, causing a voltage level at a power terminal of the memory cell to change from a supply voltage level toward a first voltage level. The voltage level at the power terminal of the memory cell is maintained at... Agent: Taiwan Semiconductor Manufacturing Company, Ltd.

20140269025 - Memory with redundant sense amplifier: Embodiments of a memory are disclosed that may reduce the likelihood of a miss-read while reading a weak data storage cell. The memory may include a number of data storage cells, a column multiplexer, a first sense amplifier and a second sense amplifier, and an output circuit. The gain level... Agent: Apple Inc.

20140269016 - Multiport memory with matching address control: A multiport SRAM has an array of cells, a first port, and a second port. During a period of different row addresses for the ports, the first port uses first word lines and first bit lines. The second port uses second word lines and second bit lines. In response to... Agent:

20140269017 - Process corner sensor for bit-cells: An integrated circuit is disclosed. The integrated circuit includes a plurality of bit-cells arranged to store data. The integrated circuit also includes a sensor configured to generate an output for determining whether the bit-cells are operating at a process corner. The sensor comprises the same circuitry as the bit-cells.... Agent: Qualcomm Incorporated

20140269020 - System and method to regulate operating voltage of a memory array: A method includes measuring a temperature of a sensor associated with a memory array. The method also includes calculating, at a voltage regulating device, an operating voltage based on the temperature and based on fabrication data associated with the memory array. The method further includes regulating, at the voltage regulating... Agent: Qualcomm Incorporated

20140269022 - Three-dimensional (3d) memory cell separation among 3d integrated circuit (ic) tiers, and related 3d integrated circuits (3dics), 3dic processor cores, and methods: A three-dimensional (3D) memory cell separation among 3D integrated circuit (IC) (3DIC) tiers is disclosed. Related 3DICs, 3DIC processor cores, and methods are also disclosed. In embodiments disclosed herein, memory read access ports of a memory block are separated from a memory cell in different tiers of a 3DIC. 3DICs... Agent:

20140269021 - Timing logic for memory array: Among other things, techniques and systems are provided for devising a schedule for performing read/write operations on a memory cell. A control signal is provided to timing logic. Using one or more properties of the control signal, such as a voltage property, the timing logic is configured to adjust a... Agent:

20140269018 - Write-assisted memory with enhanced speed: A write-assisted memory includes a pre-charge assist circuit that assists the pre-charge of the power supply voltage on a power supply lead for an accessed memory cell in a bit-line-multiplexed group of memory cells subsequent to a write-assist period by coupling charge from the power supply leads for the remaining... Agent: Qualcomm Incorporated

20140269027 - Amplifier: A circuit comprises a first data line, a second data line, a charging circuit, a first circuit, a second circuit, a first switching circuit, and a second switching circuit. The charging circuit and the first circuit are each coupled with the first data and the second data line. The first... Agent:

20140269026 - Tracking circuit: A circuit is in a memory macro and comprises a write path, a read path, a selection circuit, and a clock generator circuit. The write path includes a first signal generated based on a first edge of a clock signal in a write operation of the memory macro. The read... Agent: Taiwan Semiconductor Manufacturing Company, Ltd.

20140269032 - Architecture for magnetic memories including magnetic tunneling junctions using spin-orbit interaction based switching: A magnetic memory includes memory array tiles (MATs), intermediate circuitry, global bit lines and global circuitry. Each MAT includes bit lines, word lines, and magnetic storage cells having magnetic junction(s), selection device(s) and at least part of a spin-orbit interaction (SO) active layer adjacent to the magnetic junction(s). The SO... Agent: Samsung Electronics Co., Ltd.

20140269035 - Cross point array mram having spin hall mtj devices: Cross point array magnetoresistive random access memory (MRAM) implementing spin hall magnetic tunnel junction (MTJ)-based devices and methods of operation of such arrays are described. For example, a bit cell for a non-volatile memory includes a magnetic tunnel junction (MTJ) stack disposed above a substrate and having a free magnetic... Agent:

20140269039 - Electronic device and variable resistance element: A variable resistance element includes: first and second magnetic layers having a lanthanide series element alloyed in a nickel-iron compound; and a tunnel barrier layer interposed between the first and second magnetic layers.... Agent: Sk Hynix Inc.

20140269041 - Emulation of static random access memory (sram) by magnetic random access memory (mram): A magnetic memory system includes a magnetic random access memory (MRAM) including a plurality of magnetic memory banks and operative to store data during a write operation initiated by a write command. The magnetic memory system further includes a first-in-first-out (FIFO) interface device coupled to the MRAM and including a... Agent: Avalanche Technology, Inc.

20140269034 - Integrated capacitor based power distribution: An embodiment provides power (having low voltage, high current, and high current density) to ultra low voltage non-CMOS based devices using a distributed capacitor that is integrated onto the same chip as the non-CMOS devices. For example, an embodiment provides a spin logic gate adjacent dielectric material and first and... Agent:

20140269033 - Magnetic memory: According to one embodiment, a magnetic memory includes magnetoresistive effect elements each including a first magnetic layer, a tunnel barrier layer, and a second magnetic layer which are successively stacked, and a ferroelectric capacitor provided above the magnetoresistive effect elements via an insulating layer, and including a lower electrode, a... Agent: Kabushiki Kaisha Toshiba

20140269038 - Magnetic memory: A magnetic memory according to an embodiment includes at least one MTJ element, the MTJ element including: a magnetic multilayer structure including a first magnetic layer in which a direction of magnetization is fixed, a second magnetic layer in which a direction of magnetization is changeable, and a tunnel barrier... Agent: Kabushiki Kaisha Toshiba

20140269036 - Magnetic memory devices and methods of writing data to the same: Magnetic memory devices include a magnetoresistive cell including a free layer having a variable magnetization direction and a pinned layer having a fixed magnetization direction, a bit line on the magnetoresistive cell and including a spin Hall effect material layer exhibiting a spin Hall effect and contacting the free layer;... Agent:

20140269037 - Magnetic memory element and nonvolatile memory device: A magnetic memory element includes a first stacked unit and a second stacked unit. The first stacked unit includes a first ferromagnetic layer, a second ferromagnetic layer, and a first nonmagnetic layer. The second ferromagnetic layer is stacked with the first ferromagnetic layer. The second ferromagnetic layer has a first... Agent: Kabushiki Kaisha Toshiba

20140269030 - Method and apparatus for mram sense reference trimming: A trimming process for setting a reference current used in operating an MRAM module comprising an operational MRAM cell coupled to a bit line, multiple reference MRAM cells coupled to a reference bit line, and a sense amplifier coupled to the bit line and the reference bit line is disclosed... Agent: Taiwan Semiconductor Manufacturing Co., Ltd.

20140269040 - Pulse programming techniques for voltage-controlled magnetoresistive tunnel junction (mtj): A method of programming a voltage-controlled magnetoresistive tunnel junction (MTJ) includes applying a programming voltage pulse (Vp), reading the voltage-controlled MTJ, and determining if the voltage-controlled MTJ is programmed to a desired state and if not, changing the Vp and repeating the applying and reading steps until the voltage-controlled MTJ... Agent: Avalanche Technology, Inc.

20140269029 - Selective self-reference read: This disclosure relates to selectively performing a read with increased accuracy, such as a self-reference read, from a memory. In one aspect, data is read from memory cells, such as magnetoresitive random access memory (MRAM) cells, of a memory array. In response to detecting a condition associated with reading from... Agent: Micron Technology, Inc.

20140269042 - Self-referenced magnetic random access memory: The present disclosure concerns a magnetic random access memory cell containing a magnetic tunnel junction formed from an insulating layer comprised between a sense layer and a storage layer. The present disclosure also concerns a method for writing and reading the memory cell comprising, during a write operation, switching a... Agent:

20140269031 - System and method of sensing a memory cell: A method includes sensing a state of a data cell to generate a data voltage. The state of the data cell corresponds to a state of a programmable resistance based memory element of the data cell. The method further includes sensing a state of a reference cell to generate a... Agent: Qualcomm Incorporated

20140269028 - Thermally-assisted mram with ferromagnetic layers with temperature dependent magnetization: A technique is provided for a thermally assisted magnetoresistive random access memory device. The device has a synthetic antiferromagnetic layer disposed on an antiferromagnetic layer. The synthetic antiferromagnetic layer has a first ferromagnetic storage layer, a non-magnetic coupling layer disposed on the first ferromagnetic storage layer, and a second ferromagnetic... Agent: International Business Machines Corporation

20140269046 - Apparatuses and methods for use in selecting or isolating memory cells: Methods and devices for selection and/or isolation of memory cells include use of a thyristor For example, a memory storage component may be selected for access, at least in part, by initiating application of a triggering potential to affect a gate of a thyristor that is coupled in series with... Agent: Micron Technology, Inc.

20140269045 - Cell programming verification: Technology for verifying cell programming for a phase change memory array is disclosed. In an example, a method may include sending a reset pulse to a phase change memory cell. The method may further include sensing a threshold voltage of the phase change memory cell in response to applying first... Agent:

20140269044 - Methods and apparatuses for controlling memory write sequences: Subject matter disclosed herein relates to memory operations regarding changing an order of program bits to be programmed into a memory array.... Agent: Micron Technology, Inc.

20140269043 - Phase change memory mask: Technology for writing data to a phase change memory array is disclosed. In an example, a method may include identifying mask logic for masking cells in the phase change memory array and routing the mask logic to the cells. The method may further include routing input data to the cells.... Agent:

20140269047 - Apparatus and methods relating to a memory cell having a floating body: An apparatus is disclosed for a memory cell having a floating body. A memory cell may include a transistor over an insulation layer, the transistor including a source, and a drain. The memory cell may also include a floating body including a first region positioned between the source and the... Agent: Micron Technology, Inc.

20140269050 - Determining read voltages for reading memory: A method of reading data at a data storage device that includes a non-volatile memory having a three-dimensional (3D) configuration includes identifying a first set of storage elements of a first word line of the non-volatile memory that satisfy a condition. The condition is based on one or more states... Agent: Sandisk Technologies Inc.

20140269054 - Non-volatile memory and method of operation thereof: A method of altering threshold voltage distribution of a non-volatile MLC memory before the memory is programmed according to a pre-designated coding table. The method includes grouping a plurality of cells which are pre-designated to have the same first bit voltage in a same main state and then grouping the... Agent: Macronix International Co., Ltd.

20140269057 - Non-volatile memory device and programming method: A method of programming a non-volatile memory device includes; defining a set of verification voltages, setting a maximum verification voltage among verification voltages that are less than or equal to a first target programming voltage to be a target verification voltage, calculating a number of extra pulses based on the... Agent: Samsung Electronics Co., Ltd.

20140269058 - Non-volatile memory program algorithm device and method: A non-volatile memory device and method for programming cells using repeated pulses of program voltages, with interleaved read operations to determine the level of read current, until the desired programming state is achieved. Each successive program pulse has one or more program voltages increased by a step value relative to... Agent: Silicon Storage Technology, Inc.

20140269053 - Nonvolatile memory data recovery after power failure: A method for data recovery after a power failure is disclosed. The method may include steps (A) to (D). Step (A) may determine that a last power-down of a solid-state drive was an unsafe power-down. Step (B) may search at least some of a plurality of pages of a nonvolatile... Agent: Lsi Corporation

20140269051 - Programming schemes for 3-d non-volatile memory: A method includes providing data for storage in a memory, which includes multiple analog memory cells arranged in a three-dimensional (3-D) configuration having a first dimension associated with bit lines, a second dimension associated with word lines, and a third dimension associated with sections. The data is stored in the... Agent: Apple Inc.

20140269055 - Semiconductor memory device: Each memory cell has a threshold voltage to distinguish a storage data item. A controller generates one of storage data items from one or more sets of reception data, stores the storage data item, randomizes data transmission for memory cells, instructs the cells to store the randomized data, uses read... Agent: Kabushiki Kaisha Toshiba

20140269059 - Shifting cell voltage based on grouping of solid-state, non-volatile memory cells: Cells of a solid-state, non-volatile memory are assigned to one of a plurality of groups. Each group is defined by expected symbols stored in the cells in view of actual symbols read from the cells. Based on cell counts within the groups, it can be determined that a shift in... Agent: Seagate Technology LLC

20140269056 - Solid state drive encountering power failure and associated data storage method: A solid state drive and its associated data storage method are provided. The data storage method comprising steps of: receiving data-for-writing from a host, and transforming the data-for-writing to data-for-storage; comparing a supply voltage and a predetermined voltage; and when the supply voltage is lower than the predetermined voltage, proceeding... Agent: Lite-on It Corporation

20140269052 - System and method of determining reading voltages of a data storage device: A data storage device includes a memory and a controller. In a particular embodiment, a method is performed in the data storage device. The method is performed during a read threshold voltage update operation and includes determining a first read threshold voltage of a set of storage elements of a... Agent: Sandisk Technologies Inc.

20140269061 - High speed sensing for advanced nanometer flash memory device: Improved sensing circuits and improved bit line layouts for advanced nanometer flash memory devices are disclosed.... Agent:

20140269060 - Integrated circuits and methods for operating integrated circuits with non-volatile memory: Integrated circuits and methods for fabricating integrated circuits are provided. In an exemplary embodiment, an integrated circuit includes a semiconductor substrate doped with a first conductivity-determining impurity. The semiconductor substrate has formed therein a first well doped with a second conductivity-determining impurity that is different from the first conductivity-determining impurity,... Agent: Globalfoundries, Inc.

20140269062 - Low leakage, low threshold voltage, split-gate flash cell operation: A method of reading a memory device having rows and columns of memory cells formed on a substrate, where each memory cell includes spaced apart first and second regions with a channel region therebetween, a floating gate disposed over a first portion of the channel region, a select gate disposed... Agent: Silicon Storage Technology, Inc.

20140269063 - Method for driving semiconductor device and semiconductor device: To read multilevel data from a memory cell having a transistor using silicon and a transistor using an oxide semiconductor, without switching a signal for reading the multilevel data in accordance with the number of the levels of the multilevel data. The electrical charge of a bit line is discharged,... Agent: Semiconductor Energy Laboratory Co., Ltd.

20140269064 - Source line floating circuits, memory devices including the same and methods of reading data in a memory device: A source line floating circuit includes a plurality of floating units. The floating units directly receive decoded row address signals or voltages of word lines as floating control signals, respectively. The decoded row address signals are activated selectively in response to a row address signal. The floating units control electrical... Agent:

20140269066 - Methods for extending the effective voltage window of a memory cell: Methods for operating a non-volatile storage system in which cross-coupling effects are utilized to extend the effective threshold voltage window of a memory cell and to embed additional information within the extended threshold voltage window are described. In some cases, additional information may be embedded within a memory cell storing... Agent: Sandisk Il Ltd.

20140269065 - Nand flash memory: Serial NAND flash memory may be provided with the characteristics of continuous read of the memory across page boundaries and from logically contiguous memory locations without wait intervals, while also being clock-compatible with the high performance serial flash NOR (“HPSF-NOR”) memory read commands so that the serial NAND flash memory... Agent: Winbond Electronics Corporation

20140269070 - Compensation for temperature dependence of bit line resistance: Techniques for sensing the threshold voltage of a memory cell during reading and verify operations by compensating for changes, including temperature-based changes, in the resistance of a bit line or other control line. A memory cell being sensed is in a block in a memory array and the block is... Agent: Sandisk Technologies Inc.

20140269071 - Preserving data from adjacent word lines while programming binary non-volatile storage elements: A system and methods for programming non-volatile memory elements by using latches to transfer data. Upon discovering errors in previously programmed non-volatile memory elements, the system recovers the corresponding data from the latches and programming the recovered data to other non-volatile memory elements.... Agent: Sandisk Technologies Inc.

20140269073 - Semiconductor memory device: An aspect of the present embodiment, there is provided a semiconductor memory device including memory cell arrays, each of the memory cell arrays including memory cells, including a clock generator configured to generate clock, an input-output circuit configured to input and output data, buses, a portion of each of the... Agent: Kabushiki Kaisha Toshiba

20140269072 - Storage device: According to one embodiment, a storage device includes a nonvolatile memory and a controller. The nonvolatile memory includes blocks which store data. Each of the blocks is an erase unit. The controller controls an operation of the nonvolatile memory. The controller executes writes and erases with respect to a first... Agent:

20140269069 - Tracking cell erase counts of non-volatile memory: A data storage device includes a memory and a controller and may perform a method that includes updating, in a controller of the data storage device, a value of a particular write/erase (W/E) counter of a set of counters in response to an erase operation to a particular region of... Agent: Sandisk Technologies Inc.

20140269067 - Tracking erase operations to regions of non-volatile memory: A data storage device includes a memory and a controller and may perform a method that includes updating, in the controller, a value of a particular counter of a set of counters in response to an erase operation to a particular region of the non-volatile memory that is tracked by... Agent: Sandisk Technologies Inc.

20140269068 - Tracking erase pulses for non-volatile memory: A data storage device includes a memory and a controller and may perform a method that includes comparing, in the controller, a count of erase pulses to an erase pulse threshold. The count of erase pulses corresponds to a particular region of the non-volatile memory. The method includes, in response... Agent: Sandisk Technologies Inc.

20140269074 - Management of non-volatile memory: A method for programming a non-volatile memory including a plurality of blocks, each block including a plurality of sections, each section including at least one page, and each page including a plurality of memory cells. The method includes checking a current section of the plurality of sections against a damaged... Agent: Macronix International Co., Ltd.

20140269075 - 2t and flash memory array: Flash memory arrays are described. In one embodiment, a flash memory array includes memory sectors of Two-Transistor (2T) AND memory cells. Within each of the memory sectors, a row of sector selection transistors is configured such that writing data onto a memory column within the memory sector is controlled by... Agent: Nxp B.v.

20140269077 - Array arrangement for 3d nand memory: A semiconductor device includes a plurality of active strips, where active strips in the plurality are coupled together at one end by a pad and terminated at another end by a conductive line. The device includes memory cells at cross-points between the plurality of active strips and a plurality of... Agent: Macronix International Co., Ltd.

20140269083 - Bit line current trip point modulation for reading nonvolatile storage elements: Upon selecting non-volatile storage elements to be sensed, the system obtains information about the position of these non-volatile storage elements, determines sensing parameters based at least in part on this information, pre-charges a charge storage device and, while maintaining the voltage level of the bit lines of these memory cells... Agent: Sandisk Technologies Inc.

20140269078 - Memory architecture of thin film 3d array: A 3D memory device includes an improved dual gate memory cell. The improved dual gate memory cell has a channel body with opposing first and second side surfaces, charge storage structures on the first and second side surfaces, and a gate structure overlying the charge storage structures on both the... Agent: Macronix International Co., Ltd.

20140269076 - Non-volatile memory and programming in thereof: A non-volatile memory system includes a bit line and a plurality of memory cells associated with the bit line and coupled in a serial manner. The system further has a control circuitry in communication with the memory cells, wherein the control circuitry programs a target cell selected from the memory... Agent: Macronix International Co., Ltd.

20140269080 - Non-volatile memory device and method of programming the same: A non-volatile memory device includes a memory cell array and a voltage generator. The memory cell array has a plurality of cell strings in which a plurality of memory cells are connected with each other in series between a string select transistor and a ground select transistor. The voltage generator... Agent:

20140269084 - Non-volatile semiconductor memory device: n

20140269079 - Nonvolatile semiconductor memory device: A nonvolatile semiconductor memory device according to an embodiment includes a memory cell array that includes NAND cell units; and a write/erase circuit configured to execute a select gate write operation, the select gate write operation executing a programming operation for setting a threshold voltage of a drain side select... Agent: Kabushiki Kaisha Toshiba

20140269082 - Operation for non-volatile storage system with shared bit lines: A non-volatile storage system is disclosed that includes pairs of NAND strings (or other groupings of memory cells) in the same block being connected to and sharing a common bit line. To operate the system, two selection lines are used so that the NAND strings (or other groupings of memory... Agent: Sandisk Technologies Inc.

20140269081 - Soft erase operation for 3d non-volatile memory with selective inhibiting of passed bits: An erase operation for a 3D stacked memory device selectively inhibits subsets of memory cells which meet a verify condition as the erase operation progresses. As a result, the faster-erasing memory cells are less likely to be over-erased and degradation is reduced. Each subset of memory cells can be independently... Agent: Sandisk Technologies Inc.

20140269085 - Determining read voltages for reading memory: A method of reading data at a data storage device that includes a non-volatile memory includes identifying a first set of storage elements of a first word line of the non-volatile memory that satisfy a condition. The condition is based on one or more states of one or more storage... Agent: Sandisk Technologies Inc.

20140269087 - Lithography-friendly local read circuit for nand flash memory devices and manufacturing method thereof: A flash memory device comprising a local sensing circuitry is provided in a hierarchical structure with local and global bit lines. The local sensing circuitry comprise read and pass circuits configured to sense and amplify read currents during read operations, wherein the amplified read signals may be passed to a... Agent: Mosaid Technologies Incorporated

20140269089 - Semiconductor memory device and method of testing the same: A semiconductor memory device comprises a first-supplied-voltage-supplying pad, a second-supplied-voltage-supplying pad, a data input/output pad, a memory body, a buffer circuit and an impedance-controlling circuit. A first supplied voltage is supplied to the memory body. A second supplied voltage is supplied to the buffer circuit. The impedance-controlling circuit controls an... Agent: Kabushiki Kaisha Toshiba

20140269086 - System and method of accessing memory of a data storage device: Flash memory devices and methods of reading data from flash memory devices reduce an overall number of sensing operations when data is to be read from one word line in accordance with one or more flags set according to data read from another word line.... Agent: Sandisk Technologies Inc.

20140269088 - System and method of reading data from memory concurrently with sending write data to the memory: A data storage device includes a memory, a controller, and a communication bus coupled to the memory and to the controller. The controller is configured to send a read-write command and write data to the memory via the communication bus. The read-write command indicates an address of requested data to... Agent: Sandisk Technologies Inc.

20140269090 - Periodic erase operation for a non-volatile medium: An apparatus, system, and method are disclosed for managing erase operations for a data storage medium. A method includes determining whether a use threshold for one or more non-volatile storage cells is satisfied. A method includes performing a default erase operation for the one or more storage cells in response... Agent: Fusion-io, Inc.

20140269049 - Hybrid chargepump and regulation means and method for flash memory device: A hybrid charge pump and control circuit for use in a memory device is disclosed.... Agent:

20140269048 - Retention detection and/or channel tracking policy in a flash memory based storage system: A method for determining a retention time in a solid state device (SSD), comprising the steps of providing a plurality of write operations to a memory, determining a reference voltage for each of the write operations, determining a difference between (i) the reference voltage after each of the write operations... Agent: Lsi Corporation

20140269092 - Continuous-time floating gate memory cell programming: Aspects of a continuous-time memory cell circuit are described. In various embodiments, the memory cell circuit may comprise a memory cell, a current source coupled to the memory cell, and circuitry for programming the memory cell at an adaptive rate, based on a target voltage for programming, using a feedback... Agent: West Virginia University

20140269091 - Memory device and method of controlling leakage current within such a memory device: A memory device includes an array of memory cells arranged as a plurality of rows and columns, each row being coupled to an associated read word line, and each column forming at least one column group, where the memory cells of each column group are coupled to an associated read... Agent:

20140269097 - Non-volatile semiconductor memory device and method of controlling the non-volatile semiconductor memory device: According to one embodiment, a non-volatile semiconductor memory device includes a memory cell array and a sense amplifier. The memory cell array includes a plurality of memory cell transistors. The sense amplifier reads data held in the memory cell transistors. The sense amplifier writes data to the memory cell transistors.... Agent: Kabushiki Kaisha Toshiba

20140269096 - Non-volatile semiconductor memory device and method of programming the same: A first transistor can transfer a first voltage to a bit line. A latch circuit is electrically connected to a gate of the first transistor. A sensing portion is electrically connected to the bit line. A second transistor is connected to the sensing portion and the latch circuit. A third... Agent: Kabushiki Kaisha Toshiba

20140269093 - Semiconductor memory device: A semiconductor memory device includes a sense amplifier, and the sense amplifier includes a bus, first and second latch circuits, and a third transistor. The first latch circuit includes a first transistor connected to the bus, and the second latch circuit includes a second transistor connected to the bus. When... Agent: Kabushiki Kaisha Toshiba

20140269094 - Semiconductor memory device: A semiconductor memory device includes a plurality of memory cells, a plurality of bit lines, each of which is electrically connected to a string of the memory cells, and a sense module provided for each of the bit lines. Each sense module includes a sense transistor that is configured to... Agent: Kabushiki Kaisha Toshiba

20140269095 - Semiconductor storage: A semiconductor storage includes memory cells, a bit line, and a sense amplifier having a first transistor that controls precharging of the bit line, a second transistor that controls charging of a first node, a third transistor that controls connection of the bit line to the first node, a fourth... Agent: Kabushiki Kaisha Toshiba

20140269098 - Dynamic programming of advanced nanometer flash memory: An improved method and apparatus for programming advanced nanometer flash memory cells is disclosed.... Agent: Silicon Storage Technology, Inc.

20140269099 - Method for driving semiconductor device and semiconductor device: To read multilevel data from a memory cell having a transistor using silicon and a transistor using an oxide semiconductor, without switching a signal for reading the multilevel data in accordance with the number of the levels of the multilevel data. The potential of the bit line is precharged, the... Agent: Semiconductor Energy Laboratory Co., Ltd.

20140269101 - Programming a memory cell to a voltage to indicate a data value and after a relaxation time programming the memory cell to a second voltage to indicate the data value: A memory cell is programmed to at least a first threshold voltage to indicate a particular data value. After waiting for a relaxation time, the memory cell is programmed to at least a second threshold voltage to indicate the particular data value. The second threshold voltage is greater than the... Agent: Micron Technology, Inc.

20140269100 - Shared bit line string architecture: Methods for programming and reading memory cells using a shared bit line string architecture are described. In some embodiments, memory cells and select devices may correspond with transistors including a charge storage layer. In some cases, the charge storage layer may be conductive (e.g., a polysilicon layer as used in... Agent: Sandisk Technologies Inc.

20140269102 - Eeprom memory cell with low voltage read path and high voltage erase/write path: An electrically erasable programmable read only memory (EEPROM) cell may include a substrate including at least one active region, a floating gate adjacent the substrate, a write/erase gate defining a write/erase path for performing high voltage write and erase operations, and a read gate defining a read path for performing... Agent: Microchip Technology Incorporated

20140269103 - Nonvolatile memory device and method of manufacturing the same: A nonvolatile memory device and method of manufacturing the same are provided. In the nonvolatile memory device, a blocking insulation layer is provided between a trap insulation layer and a gate electrode. A fixed charge layer spaced apart from the gate electrode is provided in the blocking insulation layer. Accordingly,... Agent: Samsung Electronics Co., Ltd.

20140269111 - Non-volatile memory (nvm) with block-size-aware program/erase: A memory includes a plurality of blocks in which each block includes a plurality of memory cells. The memory includes a set of charge pumps which apply voltages to the plurality of blocks. A method includes selecting a block of the plurality of memory blocks; determining an array size of... Agent:

20140269105 - Circuit for generating negative bitline voltage: An integrated circuit for generating a negative bitline voltage comprises a bitline connectable to a memory cell and a multitude of capacitors arranged in groups thereof connected to the bitline. A step signal generator can generate a consecutive sequence of step signals to be applied to a group of capacitors.... Agent: Synopsys, Inc.

20140269104 - Sense amplifier column redundancy: A memory includes a redundant sense amplifier and a plurality of sense amplifier pairs. Each sense amplifier pair includes a first sense amplifier and a second sense amplifier. Each sense amplifier pair drives a common load line. The memory is configured to implement column redundancy using a single redundant sense... Agent: Qualcomm Incorporated

20140269106 - Program cycle skip evaluation before write operations in non-volatile memory: A non-volatile memory system is disclosed that evaluates during a read before write operation whether to skip programming of portions of group of memory cells during a subsequent write operation. By evaluating skip information during a read before write operation, the write operation can be expedited. The additional overhead for... Agent: Sandisk 3d LLC

20140269108 - Semiconductor device: A device includes a semiconductor substrate, a first penetrating electrode penetrating through the semiconductor substrate, a first test pad, and a first tri-state buffer coupled between the first penetrating electrode and the first test pad. The first tri-state buffer receives a buffer control signal at a control terminal thereof. The... Agent: Ps4 Luxco S.a.r.l.

20140269107 - Semiconductor device, semiconductor memory device and method of controlling the same: A semiconductor memory device comprises an inner circuit, an output buffer circuit, an output buffer controlling circuit, and a chip operation temperature sensor. The output buffer circuit outputs data from the inner circuit via a data input/output pad. The output buffer controlling circuit controls a driving power of the output... Agent: Kabushiki Kaisha Toshiba

20140269109 - Method of operating memory device, memory device using the same, and memory system including the device: A memory device includes a control logic configured to control an overall operation of the memory device; a data storing unit configured to receive write data and write the write data according to control of the control logic and to output read data obtained by reading the write data; and... Agent:

20140269112 - Apparatus and method for writing data to memory array circuits: A write driver for a memory circuit includes a control circuit configured to: operate a first push-pull driver to generate a first drive signal in a first voltage domain at a first node based on an input signal in a second domain and in response to a mode select signal... Agent: Qualcomm Incorporated

20140269110 - Asymmetric sensing amplifier, memory device and designing method: A sensing amplifier for a memory device includes first and second nodes, an input device and an output device. The memory device includes first and second bit lines, and at least one memory cell coupled to the bit lines. The first and second nodes are coupled to the first and... Agent: Taiwan Semiconductor Manufacturing Company, Ltd.

20140269113 - Non-volatile semiconductor storage device capable of increasing operating speed: According to one embodiment, a non-volatile semiconductor storage device includes a memory cell array, a row decoder, a potential generating circuit, first plural potential selection circuits, a second potential selection circuit, a first discharge circuit, and a second discharge circuit. The first plural potential selection circuits select one of output... Agent:

20140269114 - Circuit for memory write data operation: A pulsed dynamic LCV circuit for improving write operations for SRAM. The pulsed dynamic LCV circuit includes voltage adjustment circuitry having a plurality of selectable reduced supply voltages and timing adjustment circuitry having a plurality of selectable logical state transition timings for adjustably controlling the voltage and timing of a... Agent:

20140269115 - Integrated write mux and driver systems and methods: An integrated driver system is disclosed. The driver system includes decoding logic and a driver portion. The decoding logic is configured to receive select signals and data signals. The driver portion is configured to generate driver signals according to the decoded signals.... Agent: Taiwan Semiconductor Manufacturing Co. Ltd.

20140269116 - Memory device: According to one embodiment, during a transition to and from a state assumed while a signal is being received from outside a memory device at the terminal, a first pre-driver outputs a first signal which transitions at a lower rate than that during a transition to and from a state... Agent:

20140269117 - Circuits and methods for dqs autogating: In one aspect, a method includes receiving a differential strobe signal including first and second components; buffering, by a first buffer, both the first and second components; and buffering, by a second buffer, the first component. The method includes receiving, by a control logic block, the output of the second... Agent:

20140269118 - Input buffer apparatuses and methods: Apparatuses and methods are disclosed, including an apparatus with a first differential amplifier to amplify an input signal into a first output signal, a second differential amplifier to amplify the input signal into a second output signal that is complementary to the first output signal, and a feedback resistance coupled... Agent:

20140269119 - Synchronous semiconductor memory device having delay locked loop circuit and method of controlling the delay locked loop circuit: An operating method of a delay locked loop (DLL) circuit for a semiconductor memory device is disclosed. The DLL circuit may include a plurality of sub-circuits. The method may include calculating an additive latency value based on predetermined parameters, and controlling a set of the plurality of sub-circuits of the... Agent: Samsung Electronics Co., Ltd.

20140269120 - Synchronous semiconductor memory device having dual delay locked loop circuit and method of managing dual delay locked loop circuit: A synchronous semiconductor memory device includes a first delay locked loop circuit and a second delay locked loop circuit. The first delay locked loop circuit has a first delay line and generates a first clock hat is delay-synchronized with a clock applied as a signal for a data output timing... Agent: Samsung Electronics Co., Ltd.

20140269121 - Apparatuses and methods for controlling data timing in a multi-memory system: Apparatuses, multi-memory systems, and methods for controlling data timing in a multi-memory system are disclosed. An example apparatus includes a plurality of memory units. In the example apparatus, a memory unit of the plurality of memory units includes a memory configured to provide associated read data to a data pipeline... Agent: Micron Technology, Inc.

20140269123 - Semiconductor memory device and refresh method thereof: A semiconductor memory device includes: a normal memory cell block including a first plurality of memory cells; a redundancy memory cell block including a second plurality of memory cells and configured for use in replacing memory cells of the normal memory cell block; a weak cell information storage configured to... Agent: Samsung Electronics Co., Ltd.

20140269122 - System and method for integrated circuit memory repair: Memory blocks in an integrated circuit (IC) chip can be repaired by employing automated test equipment external to the IC chip to aid in burning fuses on the IC chip by encoding the fuses with binary-encoded numbers. Each binary-encoded number represents a bit position of each “1” bit of a... Agent: Avago Technologies GeneralIP(singapore) Pte. Ltd .

20140269124 - Memory with bit line current injection: Embodiments of a memory are disclosed that may allow for the detection of weak data storage cells or may allow operation of data storage cells under conditions that may represent the effects of transistor ageing. The memory may include data storage cells, a column multiplexer, a sense amplifier, and a... Agent: Apple Inc.

20140269126 - Circuit arrangement and method for operating a circuit arrangement: A circuit arrangement is provided, including a storage circuit and an output circuit. The storage circuit is configured to provide a first output signal and a second output signal. The output circuit is configured to receive the first output signal and the second output signal and configured to provide an... Agent: Infineon Technologies Ag

20140269125 - Device and method for improving reading speed of memory: A memory device includes a plurality of sense amplifiers coupled with an array of memory cells, a plurality of output data lines receiving outputs of corresponding sense amplifiers, and a plurality of precharge circuits configured to apply a precharge voltage on the output data lines. A controller provides control signals... Agent: Macronix International Co., Ltd.

20140269127 - Memory operation latency control: An integrated circuit with memory can operate with reduced latency between consecutive operations such as read operations. At a first time, a first operation command is finished on a memory array on an integrated circuit. At a second time, a second operation command is begun on the memory array. A... Agent: Macronix International Co., Ltd.

20140269128 - Sense amplifier: A sense amplifier includes a cross latch, a first pass gate, a second pass gate, a first data line, a second data line, a first circuit, and a second circuit. The cross latch has a first input/output (I/O) node and a second I/O node. The first pass gate is coupled... Agent: Taiwan Semiconductor Manufacturing Company, Ltd.

20140269129 - Methods and apparatus for reducing programming time of a memory cell: A method is provided for programming a memory cell having a first terminal coupled to a word line and a second terminal coupled to a bit line. During a first predetermined time interval, the word line is switched from a first standby voltage to a first voltage, the bit line... Agent: Sandisk 3d LLC

20140269130 - Memory receiver circuit for use with memory of different characteristics: Embodiments include systems, methods, and apparatuses for reading a data signal from a memory, such as a dynamic random access memory (DRAM). In one embodiment, a memory receiver may include a differential amplifier to receive a data signal from the memory and pass a differential output signal based on a... Agent:

20140269131 - Memory with power savings for unnecessary reads: A memory device includes a plurality of sense amplifiers, an array of memory cells including a first subset of memory cells, and a plurality of word lines. Each word line is coupled to each memory cell in a respective row of the memory cells and each row of the memory... Agent:

20140269133 - Background auto-refresh apparatus and method for non-volatile memory array: A method for automatically refreshing a non-volatile memory array in the background without memory interruption includes selecting an unrefreshed segment of the memory, reading data from each row in the selected segment during memory dead time and storing the data read from each row in a local temporary storage memory... Agent: Microsemi Soc Corporation

20140269132 - Negative charge pump regulation: A negative charge pump is responsive to a pump enable signal. A voltage controlled current source provides a current. A resistor is coupled between a node from the voltage controlled current source and a negative charge output from the negative charge pump. A capacitor is placed in parallel with the... Agent: Freescale, Inc.

20140269134 - Memory device and method of controlling refresh operation in memory device: A method of controlling a refresh operation for a memory device is disclosed. The method includes storing a first row address corresponding to a first row of a memory cell array, storing one or more second row addresses corresponding to one or more second rows of the memory cell array,... Agent: Samsung Electronics Co., Ltd.

20140269135 - Circuit and system for concurrently programming multiple bits of otp memory devices: Circuits and systems for concurrently programming a plurality of OTP cells in an OTP memory are disclosed. Each OTP cell can have an electrical fuse element coupled a program selector having a control terminal. The control terminals of a plurality of OTP cells can be coupled to a plurality of... Agent:

20140269137 - Canary based sram adaptive voltage scaling (avs) architecture and canary cells for the same: A memory bank includes memory cells and an additional cell to determine an operating voltage of the memory bank. The additional cell has an operating margin that is less than a corresponding operating margin of the other memory cells in the memory bank.... Agent: Stmicroelectronics International N.v.

20140269136 - Power supply circuit and semiconductor device: An output transistor coupled between an input terminal where an input voltage is input and an output terminal where an output voltage is output; an error amplifier configured to generate a first error signal and a second error signal based on a voltage in accordance with the output voltage and... Agent: Fujitsu Semiconductor Limited

20140269138 - Semiconductor memory device for reducing standby current: A semiconductor memory device includes a standby voltage providing unit. The standby voltage providing unit is configured to receive an external voltage, primarily clamp and secondarily clamp a predetermined voltage, and provide the predetermined voltage as an internal voltage, during a standby mode.... Agent: Sk Hynix Inc.

20140269139 - Hidden refresh of weak memory storage cells in semiconductor memory: In an example, the present invention provides a computing system. The system has a memory interface device comprising a counter, a dynamic random access memory device coupled to the memory interface device. The device comprises a plurality of banks, each of the banks having a subarray, each subarray having a... Agent: Inphi Corporation

20140269140 - Non-volatile memory (nvm) with word line driver/decoder using a charge pump voltage: A word line driver that includes a pull up transistor for biasing a node of a stack of transistors that are located between a high supply voltage terminal and a low supply voltage terminal. The node is biased at a voltage that is between the high supply voltage and the... Agent:

20140269141 - Wordline doubler: A memory includes a clock generator for providing a first clock signal responsive to a second clock signal and a feedback signal. A feedback loop provides the feedback signal and includes a tracking wordline, a tracking bitline, a tracking bit cell, and a tracking wordline driver for driving the tracking... Agent:

  
09/11/2014 > 140 patent applications in 31 patent subcategories.

20140254231 - 3d non-volatile memory having low-current cells and methods: A 3D array of nonvolatile memory has each read/write element accessed at a crossing between a word line and a bit line. The read/write element forms a tubular electrode having an outside shell of R/W material enclosing an oxide core. In a rectangular form, one side of the electrode contacts... Agent: Sandisk 3d LLC

20140254232 - Integrated circuit devices having memory and methods of implementing memory in an integrated circuit device: An integrated circuit device having memory is disclosed. The integrated circuit device comprises programmable resources; programmable interconnect elements coupled to the programmable resources, the programmable interconnect elements enabling a communication of signals with the programmable resources; a plurality of memory blocks; and dedicated interconnect elements coupled to the plurality of... Agent: Xilinx, Inc.

20140254234 - Random fuse sensing: In accordance with some embodiments, the way in which the fuses are sensed and, particularly, their order may be made more random so that it is much more difficult to simply exercise the device and determine all the values of the storage elements within the fuse array. One result is... Agent:

20140254233 - Redundant fuse coding: In accordance with some embodiments, fuse information may be written into a fuse array in a way that provides sufficient redundancy, making it harder for malicious parties to attack the fuse array.... Agent:

20140254235 - Power supply brownout protection circuit and method for embedded fram: Corruption of data in a FRAM (2) is avoided by applying a regulated voltage (VLDO) to a conductive pin (5-1). A switch (SW1) is coupled between the conductive pin and a power terminal of the FRAM so a FRAM supply voltage (VFRAM) is equal to the regulated voltage when the... Agent: Texas Instruments Incorporated

20140254243 - Electronic device and method for fabricating the same: A semiconductor memory includes a substrate configured to include a plurality of active regions which are defined by isolation layers extending in a first direction and word lines extending in a second direction intersecting the first direction; source line contacts configured to be alternately disposed over the active regions arranged... Agent: Sk Hynix Inc.

20140254239 - Electronic device comprising a semiconductor memory unit: Devices and methods based on disclosed technology include, among others, an electronic device capable of improving a signal transfer characteristic and a method for fabricating the same. Specifically, an electronic device in one implementation includes a plurality of buried gates formed in a substrate, open parts formed in the substrate... Agent: Sk Hynix Inc.

20140254245 - Hybrid non-volatile memory device: A hybrid non-volatile memory device includes a non-volatile random access memory (NVRAM) having an array of magnetic memory elements, the NVRAM being bit-accessible. The hybrid non-volatile device further includes a non-volatile page-mode memory (PMM) made of resistive memory and organized into pages, the non-volatile PMM being page-accessible. Further included in... Agent: Avalanche Technology, Inc.

20140254236 - Memory state sensing based on cell capacitance: A memory cell and method for operating a memory cell including a bidirectional access device and memory element electrically coupled in series. The bidirectional access device includes a tunneling capacitance. The memory element programmable to a first and second state by application of a first and second write voltage opposite... Agent: International Business Machines Corporation

20140254237 - Method for operating rram memory: Methods for operating memory are disclosed. A method includes applying a select word line voltage to a word line node of a first resistive random access memory (RRAM) cell; applying a first programming voltage to a source line node of the first RRAM cell; and setting the first RRAM cell... Agent: Taiwan Semiconductor Manufacturing Company, Ltd.

20140254240 - Method of programming a non-volatile resistive memory: A method for pre-programming a matrix of resistive non-volatile memory cells, the cells including a dielectric material between two conducting electrodes and being initially in an original resistive state, the dielectric material being electrically modified to bring a cell from the original state to another resistive state wherein the resistance... Agent: Commissariat A L'energie Atomique Et Aux Ene Alt

20140254242 - Non-volatile storage system biasing conditions for standby and first read: Methods for reducing power consumption of a non-volatile storage system and reducing first read latency are described. The non-volatile storage system may include a cross-point memory array. In some embodiments, during a standby mode, the memory array may be biased such that both word lines and bit lines are set... Agent:

20140254244 - Resistive random access memory (reram) and conductive bridging random access memory (cbram) cross coupled fuse and read method and system: By arranging both a conductive and non-conductive resistive memory cell in a cross coupled arrangement to facilitate reading a data state the memory cells can have very small differences in their resistance values and still read correctly. This allows both of the memory cells' resistances to change over time and... Agent:

20140254241 - Semiconductor device and information reading method: A semiconductor device includes; a memory device configured to take a plurality of resistance states that are distinguishable from one another; a bias application section configured to apply, in a bias application period, a bias signal to the memory device; and a determination section configured to determine a resistance state... Agent: Sony Corporation

20140254238 - Sensing data in resistive switching memory devices: Structures and methods of operating a resistive switching memory device are disclosed herein. In one embodiment, a resistive switching memory device can include: (i) a plurality of resistive memory cells, where each of the resistive switching memory cells is configured to be programmed to a low resistance state by application... Agent: Adesto Technologies Corporation

20140254246 - Dual-port sram systems: Schematic circuit designs for a dual-port SRAM cell are disclosed, together with various layout schemes for the dual-port SRAM cell. The dual-port SRAM cell comprises a storage unit and a plurality of partial dummy transistors connected to the outputs of the storage unit. Various layout schemes for the dual-port SRAM... Agent: Taiwan Semiconductor Manufacturing Company, Ltd.

20140254248 - Stable sram cell: SRAM cells and SRAM cell arrays are described. In one embodiment, an SRAM cell includes a first inverter and a second inverter cross-coupled with the first inverter to form a first data storage node and a complimentary second data storage node for latching a value. The SRAM cell further includes... Agent: Taiwan Semiconductor Manufacturing Company, Ltd.

20140254247 - Writing to a memory cell: In a method, various operations are performed based on a voltage line coupled with a plurality of memory cells. Storage nodes of the plurality of memory cells are caused to change to a first logical value. Another first logical value is applied to a plurality of data lines. Each data... Agent: Taiwan Semiconductor Manufacturing Company, Ltd.

20140254249 - Stable sram cell: SRAM cells and SRAM cell arrays are described. In one embodiment, an SRAM cell includes a first inverter and a second inverter cross-coupled with the first inverter to form a first data storage node and a complimentary second data storage node for latching a value. The SRAM cell further includes... Agent: Taiwan Semiconductor Manufacturing Company, Ltd.

20140254251 - Magnetic automatic test equipment (ate) memory tester device and method employing temperature control: In a particular embodiment, a method includes controlling a temperature within a chamber while applying a magnetic field. A device including a memory array is located in the chamber. The method includes applying a magnetic field to the memory array and testing the memory array during application of the magnetic... Agent: Qualcomm Incorporated

20140254250 - Magnetic memory circuit with stress inducing layer: Memory circuit comprising an addressable magnetic tunnel junction (MTJ) stack, forming a magnetic storage element in the circuit. The MTJ stack comprises a tunnel oxide layer between a free layer and a fixed layer. A stress inducing layer is disposed adjacent to the free layer to provide tensile or compressive... Agent: Magsil Corporation

20140254252 - Magnetoresistive element: A STT-MRAM comprises apparatus, and method of operating a double-MTJ magnetoresistive memory and a plurality of magnetoresistive memory element having a first recording layer which has an interface interaction with an underneath dielectric functional layer and having a second recording layer which has no interface interaction with an underneath dielectric... Agent: T3memory, Inc.

20140254253 - Memory element and memory device: There is disclosed a memory element including a memory layer that has a magnetization and a magnetization direction thereof varies corresponding to information; a magnetization-fixed layer that has a magnetization; and an insulating layer that is provided between the memory layer and the magnetization-fixed layer, wherein an electron that is... Agent: Sony Corporation

20140254255 - Mram wtih metal gate write conductors: In one embodiment of the invention, there is provided a magnetic random access (MRAM) device. The device comprises a plurality of MRAM cells, wherein each MRAM cell comprises a magnetic bit, and write conductors defined by conductors patterned in a second metal layer above the magnetic bit; and a gate... Agent: Iii Holdings 1, LLC

20140254254 - Semiconductor storage device and driving method thereof: A memory includes a cell array including nonvolatile memory cells. A power generator generates a power supply voltage for driving the cell array. A receiver receives a command and an address. A controller controls an active state of the cell array, the power generator, and the receiver. In an activation... Agent: Kabushiki Kaisha Toshiba

20140254257 - Memory and memory managing method: A method for managing memory includes setting a state of a first memory cell to a first state representing a first data and setting a state of a second memory cell to a second state representing the first data. If the state of the second memory cell has changed to... Agent: Macronix International Co., Ltd.

20140254258 - Reference voltage generators and sensing circuits: Described examples include sensing circuits and reference voltage generators for providing a reference voltage to a sensing circuit. The sensing circuits may sense a state of a memory cell, which may be a PCM memory cell. The sensing circuits may include a cascode transistor. Examples of reference voltage generators may... Agent: Micron Technology, Inc.

20140254256 - Vertical type semiconductor device, fabrication method thereof and operation method thereof: A vertical type semiconductor device and a fabrication method thereof are provided. The vertical type semiconductor device includes a pillar structure having a stacking structure of a conductive layer and a data storage material and formed on a common source region, and a gate electrode formed to surround the data... Agent: Sk Hynix Inc.

20140254259 - Dual-port semiconductor memory and first in first out (fifo) memory having electrically floating body transistor: Multi-port semiconductor memory cells including a common floating body region configured to be charged to a level indicative of a memory state of the memory cell. The multi-port semiconductor memory cells include a plurality of gates and conductive regions interfacing with said floating body region. Arrays of memory cells and... Agent: Zeno Semiconductor, Inc.

20140254264 - Defect or program disturb detection with full data recovery capability: A programming operation for a set of non-volatile storage elements determines whether the storage elements have been programmed properly after a program-verify test is passed and a program status=pass is issued. Write data is reconstructed from sets of latches associated with the storage elements using logical operations optionally one or... Agent: Sandisk Technologies Inc.

20140254266 - Direct multi-level cell programming: A data storage device includes a controller coupled to a non-volatile memory having a three-dimensional (3D) configuration. The non-volatile memory includes a group of storage elements. Each storage element is configured to store multiple data bits. Data is sent from the controller to the non-volatile memory and first bits corresponding... Agent: Sandisk Technologies Inc.

20140254265 - Flash memory cells, nand cell units, methods of forming nand cell units, and methods of programming nand cell unit strings: Some embodiments include utilization of alternating first and second gate types along NAND strings, with the second gate types having floating gates thicker than floating gates of the first gate types, and capacitively coupled with control gates of the first gate types. The second gate types may be multilevel cell... Agent: Micron Technology, Inc.

20140254262 - Internal data load for non-volatile storage: Techniques are disclosed herein for performing an Internal Data Load (IDL) to sense non-volatile storage elements. Read pass voltages that are applied to the two neighbor word lines to a selected word line may be adjusted to result in a more accurate IDL. The read pass voltage for one neighbor... Agent: Sandisk Technologies Inc.

20140254263 - Write sequence providing write abort protection: In a multi-level cell (MLC) nonvolatile memory array, data is assigned sequentially to the lower and upper page of a word line, then both lower and upper pages are programmed together before programming a subsequent word line. Word lines of multiple planes are programmed together using latches to hold data... Agent: Sandisk Technologies Inc.

20140254268 - Hybrid non-volatile memory cells for shared bit line: A non-volatile storage system includes a plurality of groups of connected non-volatile storage elements. Each group comprises multiple connected data non-volatile storage elements and multiple select gates on a common side of the data non-volatile storage elements. The multiple select gates comprise a first select gate and a second select... Agent: Sandisk Technologies Inc.

20140254267 - Memory devices with different sized blocks of memory cells and methods: In an embodiment, each block of a plurality of blocks includes a respective plurality of strings of memory cells, where each of the plurality of strings of a block is coupled to a respective select transistor, and wherein each of the select transistors coupled to the plurality of strings of... Agent: Micron Technology, Inc.

20140254269 - Non-volatile storage with shared bit lines and flat memory cells: A non-volatile storage system is disclosed that includes pairs (or another number) of NAND strings (or other groupings of memory cells) in the same block being connected to and sharing a common bit line. By sharing bit lines, less bit lines are needed in the storage system. Using less bit... Agent: Sandisk Technologies Inc.

20140254271 - Nonvolatile memory device and read method thereof: A nonvolatile memory device has improved reliability by compensating a threshold voltage of a flash memory cell. A nonvolatile memory device includes a memory cell array and a voltage generator for supplying a select read voltage to a select word line and an unselect read voltage to unselected word lines... Agent:

20140254270 - Semiconductor memory device and data writing method of the same: A semiconductor memory device includes memory cells which are laminated on a semiconductor substrate and include charge storage layers and control gates, a plurality of word lines each of which is commonly connected to the control gates of a plurality of the memory cells, and a control unit which performs... Agent: Kabushiki Kaisha Toshiba

20140254273 - Method and system for minimizing number of programming pulses used to program rows of non-volatile memory cells: A flash memory device programs cells in each row in a manner that minimizes the number of programming pulses that must be applied to the cells during programming. The flash memory device includes a pseudo pass circuit that determines the number of data errors in each of a plurality of... Agent: Micron Technology, Inc.

20140254272 - Simultaneous sensing of multiple wordlines and detection of nand failures: Techniques for a post-write read are presented. In an exemplary embodiment, a combined simultaneous sensing of multiple word lines is used in order to identify a problem in one or more of these word lines. That is, sensing voltages are concurrently applied to the control gates of more than one... Agent: Sandisk Technologies Inc.

20140254277 - Method and apparatus for program and erase of select gate transistors: Techniques are provided for programming and erasing of select gate transistors in connection with the programming or erasing of a set of memory cells. In response to a program command to program memory cells, the select gate transistors are read to determine whether their Vth is below an acceptable range,... Agent: Sandisk Technologies Inc.

20140254276 - Nonvolatile semiconductor memory device: According to one embodiment, a nonvolatile semiconductor memory device comprises memory cells each which stores data with two or more levels. Each of the memory cells includes a semiconductor layer, a first insulating layer on the semiconductor layer, a charge storage layer on the first insulating layer, a second insulating... Agent:

20140254274 - Semiconductor memory device: According to one embodiment, a semiconductor memory device includes a memory cell and a control circuit. The memory cell is such that a ferroelectric film is provided as a gate dielectric film. When data is stored in the memory cell, the control circuit applies a first voltage to the gate... Agent: Kabushiki Kaisha Toshiba

20140254275 - Semiconductor memory device: According to one embodiment, a memory cell, a word line, and a peripheral circuit are provided. In the memory cell, a ferroelectric film is provided for a gate insulating film. The word line is connected to a control gate electrode of the memory cell. In the peripheral circuit, ferroelectric films... Agent:

20140254278 - Writing data to a thermally sensitive memory device: Writing data to a thermally sensitive memory device, including: receiving a physical layout of the thermally sensitive memory device; receiving the direction of airflow across the thermally sensitive memory device; selecting an address for writing data to the thermally sensitive memory device in dependence upon the physical layout of the... Agent: International Business Machines Corporation

20140254279 - Writing data to a thermally sensitive memory device: Writing data to a thermally sensitive memory device, including: receiving a physical layout of the thermally sensitive memory device; receiving the direction of airflow across the thermally sensitive memory device; selecting an address for writing data to the thermally sensitive memory device in dependence upon the physical layout of the... Agent: International Business Machines Corporation

20140254281 - 3d non-volatile memory device and method for operating and fabricating the same: A 3D non-volatile memory device includes a plate-type lower select line formed over a substrate, a lower select transistor formed in the lower select line, a plurality of memory cells stacked over the lower select transistor, an upper select transistor formed over the memory cells, and a line-type common source... Agent: Sk Hynix Inc.

20140254280 - Programming method for memory cell: A method for programming memory cells includes applying a programming voltage to a selected memory cell in a memory cell array and a neighboring passing voltage to a neighboring memory cell next to the selected memory cell, increasing the programming voltage for programming the selected memory cell, and increasing the... Agent: Macronix International Co., Ltd.

20140254261 - Nonvolatile semiconductor memory device and read method thereof: A nonvolatile semiconductor memory device includes a memory cell array and a control circuit. The memory cell array comprises a plurality of memory cells and stores initial setting data in the plurality of memory cells. The control circuit is configured to apply a first voltage to gates of the plurality... Agent: Kabushiki Kaisha Toshiba

20140254260 - Reducing coupling noise during read operation: A method is provided for sensing data in a memory device. The memory device includes a block of memory cells coupled to a plurality of bit lines. The method includes precharging the plurality of bit lines to a first level VPRE. The method includes enabling current flow through selected memory... Agent:

20140254282 - Non-volatile semiconductor storage device: For data erase from an electrically erasable and programmable non-volatile memory cell, the following operations are performed: an erase operation to apply an erase pulse voltage to a memory cell for data erase, an erase verify operation to verify whether data erase is completed, and a step-up operation to increase... Agent: Kabushiki Kaisha Toshiba

20140254283 - Programming select gate transistors and memory cells using dynamic verify level: Programming accuracy is increased for select gate transistors and memory cells by using a dynamic verify voltage which increases from an initial level to a final level during a programming operation. Faster-programming transistors are locked out from programming before slower-programming transistors, but experience program disturb which increases their threshold voltage... Agent: Sandisk Technologies Inc.

20140254284 - Word line driver circuit for selecting and deselecting word lines: A memory circuit includes word lines coupled to a memory array, including a first set of one or more word lines deselected in an erase operation, and a second set of one or more word lines selected in the erase operation. Control circuitry couples the first set of one or... Agent: Macronix International Co., Ltd.

20140254285 - Temperature-based adaptive erase or program parallelism: A method includes, in one implementation, performing a memory operation to place memory cells of a memory array to a first logic state using a voltage of a charge pump. A portion of the operation is performed on the memory cells using the voltage of the charge pump. A temperature... Agent:

20140254286 - Thermal anneal using word-line heating element: In response to detecting an event during operation of an integrated-circuit memory device containing charge-storing memory cells, an electric current is enabled to flow through a word line coupled to the charge-storing memory cells for a brief interval to heat the charge-storing memory cells to an annealing temperature range.... Agent: Rambus Inc.

20140254289 - Data circuit: A circuit includes a first plurality of memory cells coupled with a first data line and a first data transfer circuit coupled with the first data line and a second data line. In a first operation mode of the circuit, the first data line is left floating and is caused... Agent: Taiwan Semiconductor Manufacturing Company, Ltd.

20140254287 - Semiconductor integrated circuit capable of controlling read command: The semiconductor integrated circuit includes a command decoder, a shift register unit and a command address latch unit. The command decoder is responsive to an external command defining write and read modes and configured to provide a write command or a read command according to the external command using a... Agent: Sk Hynix Inc.

20140254288 - Pipelining in a memory: A system including a memory cell array including a plurality of memory cells, and a writing device to generate multiple back-to-back write pulses to write to target memory cells from among the plurality of memory cells, the multiple back-to-back write pulses overlapping during an overlap duration, the overlap duration being... Agent: Spansion LLC

20140254290 - Local evaluation circuit for static random-access memory: A local evaluation circuit for a memory array includes first and second NAND gates and first, second, third, and fourth switches. The first switch is configured to couple a first node of the second NAND gate to a first power supply node in response to a first read signal. The... Agent: International Business Machines Corporation

20140254291 - Memory state sensing based on cell capacitance: A memory cell and method for operating a memory cell including a bidirectional access device and memory element electrically coupled in series. The bidirectional access device includes a tunneling capacitance. The memory element programmable to a first and second state by application of a first and second write voltage opposite... Agent: International Business Machines Corporation

20140254292 - Overlapping interconnect signal lines for reducing capacitive coupling effects: Described herein are various principles for designing, manufacturing, and operating integrated circuits having functional components and one or more metal interconnect layers, where the dimensions of signal lines of the metal interconnect layers are larger than dimensions of the functional components. In some embodiments, a signal line may have a... Agent: Stmicroelectronics, Inc.

20140254293 - High-speed memory write driver circuit with voltage level shifting features: Various aspects of a fast, energy efficient write driver capable of efficient operation in a dual-voltage domain memory architecture are provided herein. Specifically, various aspects of the write driver described herein combine a high speed driver with voltage level shifting capabilities that may be implemented efficiently in reducing use of... Agent: Qualcomm Incorporated

20140254294 - Memory controller for strobe-based memory systems: An integrated circuit (IC) memory controller is disclosed. The memory controller includes a receiver to receive a strobe signal and provide an internal strobe signal. An adjustable delay circuit delays an enable signal to generate a delayed enable signal. A gate circuit generates a gated strobe signal using the delayed... Agent: Rambus Inc.

20140254295 - Memory device and method for driving the same: A memory device is provided. The memory device includes programming first bit data into a plurality of memory cells; identifying target memory cells which are in a first state and whose threshold voltages are equal to or greater than a first voltage from the memory cells programmed with the first... Agent: Samsung Electronics Co., Ltd.

20140254296 - Bit based fuse repair: In accordance with some embodiments, instead of providing replacement rows, an area within a fuse array may be reserved for storing addresses of bits that are defective. Then these bits can be readily repaired by simply reading the stored state of identified defective bit, and inverting the stored state of... Agent:

20140254297 - Method and apparatus for memory repair: An integrated circuit includes an array of memory cells that is arranged into rows, main columns, and redundant columns that perform repairs in the array. The main columns and the redundant columns are divided into row blocks. Bit lines couple the main columns to status memory indicating repair statuses of... Agent: Macronix International Co., Ltd.

20140254298 - Variable dynamic memory refresh: A system and method are provided for refreshing a dynamic memory. A first region of a memory is refreshed at a first refresh rate and a second region of the memory is refreshed at a second refresh rate that is different than the first refresh rate. A memory controller is... Agent: Nvidia Corporation

20140254299 - Robust memory start-up using clock counter: In accordance with at least one embodiment, a clock counter on a system (for example, a system-on-a-chip (SOC) or other system) is utilized to count a number of a clock edges of a memory clock within a predefined time based on a predetermined system clock frequency and, therefore, to determine... Agent:

20140254300 - Devices and system providing reduced quantity of interconnections: Methods, devices and systems for reducing the quantity of external interconnections of a memory device are disclosed. Implementation of one such method, device and system includes inputting over an address bus a first portion of an address of a next row of memory cells to be activated. The first portion... Agent: Micron Technology, Inc.

  
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