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Static information storage and retrieval

Below are recently published patent applications awaiting approval from the USPTO. Recent week's RSS XML file available below.
Listing for abstract view: USPTO application #, Title, Abstract excerpt,Patent Agent. Listing format for list view: USPTO National Class full category number, title of the patent application.
  
11/13/2014 > 28 patent applications in 20 patent subcategories.

20140334216 - General structure for computational random access memory (cram): A cell array includes a logic connection line, a plurality of bit selection lines, and a plurality of cells. Each cell includes a memory element connected to a respective bit selection line and a logic switching element that selectively connects the memory element to the logic connection line. When logic... Agent: Regents Of The University Of Minnesota

20140334217 - Nonvolatile semiconductor memory device: A nonvolatile semiconductor memory device includes: a memory cell array having a plurality of memory cells arranged in a matrix; a reference bit line; a reference source line; at least one reference cell including first and second transistors serially connected between these lines; a reference word line connected to the... Agent:

20140334218 - Semiconductor device: Provided is a memory device in which memory capacity per unit area is increased without making the manufacturing process complicated. The memory device includes a plurality of memory cells, a plurality of word lines, and a plurality of bit lines. Each of the plurality of memory cells includes a switching... Agent:

20140334219 - Apparatuses and methods including memory with top and bottom data lines: Some embodiments include apparatuses and methods having a first set of data lines, a second set of data lines, and memory cells located in different levels of the apparatus. In at least one of such embodiments, the memory cells can be arranged in memory cell strings between the first and... Agent:

20140334220 - Embedded non-volatile memory circuit for implementing logic functions across periods of power disruption: A circuit having an autonomous ferroelectric memory latch (AML) is disclosed. An AML characterized by an AML input, an AML output, a first AML power contact, a second AML power contact and an AML state, and a first switch in series with one of the AML input or the AML... Agent: Radiant Technologies, Inc.

20140334223 - Apparatuses and methods for determining stability of a memory cell: Examples described include apparatuses and methods for determining stability of memory cells. Resistance variable memory cells may be used. Once a memory cell is placed in a low or high resistance state responsive to set or reset pulses, the stability of the state may be determined, such as by providing... Agent:

20140334222 - Low read current architecture for memory: A low read current architecture for memory. Bit lines of a cross point memory array are allowed to be charged by a selected word line until a minimum voltage differential between a memory state and a reference level is assured.... Agent: Unity Semiconductor Corporation

20140334221 - Resistance change memory: According to one embodiment, a memory includes memory cells between first conductive lines and second conductive lines. A control circuit is configured to apply a first potential to a first end of a selected first conductive line connected to the selected memory cell among the first conductive lines and first... Agent: Kabushiki Kaisha Toshiba

20140334225 - Prioritizing refreshes in a memory device: A method and apparatus for refreshing a row of a memory device prior to a scheduled refresh. A memory array may include a plurality of memory cells. The memory array may be configured to be refreshed at a first refresh time interval. The memory device may also include an intermediate... Agent: International Business Machines Corporation

20140334224 - Reference voltage modification in a memory device: A method and apparatus for modifying a reference voltage between refreshes in a memory device are disclosed. The memory array may include a plurality of memory cells. The memory device may also include a sense amplifier. The sense amplifier may be configured to read data from the plurality of memory... Agent: International Business Machines Corporation

20140334226 - Circuit for reverse biasing inverters for reducing the power consumption of an sram memory: CMOS integrated circuits with very low consumption when idle, and notably the SRAM volatile memories, are provided. The inverters of the circuit are made up of an NMOS transistor and a PMOS transistor. A bias circuit applies a first rear bias voltage NBIAS to the wells of the NMOS transistors... Agent:

20140334227 - Memory circuit, method of driving the same, nonvolatile storage device using the same, and liquid crystal display device: The present invention provides a memory circuit including a memory element to which writing can be performed with a small current and a low voltage, i.e., low power consumption, and provides a non-volatile storage device that can easily reduce a chip size by using this memory circuit. A memory element... Agent:

20140334228 - Linearly related threshold voltage offsets: Threshold voltage offsets for threshold voltages are determined. The threshold voltage offsets may be linearly related by a non-zero slope. The threshold voltages are shifted using their respective threshold voltage offsets. The threshold voltages that are shifted by their respective threshold voltage offsets are used to read data from multi-level... Agent: Seagate Technology LLC

20140334229 - Semiconductor device with floating gate and electrically floating body: Techniques for providing floating body memory devices are disclosed. In one particular exemplary embodiment, the techniques may be realized as a semiconductor device comprising a floating gate, a control gate disposed over the floating gate, a body region that is electrically floating, wherein the body region is configured so that... Agent: Micron Technology, Inc.

20140334230 - Semiconductor memory device and system having the same: A semiconductor memory device includes a first dummy transistor coupled to a bit line, a first select transistor formed where a first selection line surrounds a vertical channel layer, a second dummy transistor coupled to a common source line, a second select transistor formed where a second selection line surrounds... Agent: Sk Hynix Inc.

20140334231 - Semiconductor memory device and system having the same: A control circuit is configured to set a drain-side select transistor and a source-side select transistor connected to a selected memory string to non-conductive states. The control circuit is configured to apply a first voltage to a non-selected word line connected to a gate of a non-selected memory cell in... Agent: Kabushiki Kaisha Toshiba

20140334232 - 3d flash memory device having different dummy word lines and data storage devices including same: A three-dimensional (3D) flash memory includes a first dummy word line disposed between a ground select line and a lowermost main word line, and a second dummy word line of different word line configuration disposed between a string select line and an upper most main word line.... Agent:

20140334233 - Method of reading memory cells with different threshold voltages without variation of word line voltage and nonvolatile memory device using the same: A soft-decision read method of a nonvolatile memory device includes receiving a soft-decision read command, applying a read voltage to a selected word line, pre-charging bit lines respectively connected to selected memory cells of the selected word line, continuously sensing states of the selected memory cells. The pre-charged voltages of... Agent: Samsung Electronics Co., Ltd.

20140334234 - Semiconductor device including memory cell having charge accumulation layer: A semiconductor device includes MOS transistors, capacitor elements, a voltage generating circuit, a contact plug, and a memory cell. The MOS transistor and the capacitor element are formed on a first one of the element regions and a second one of the element regions, respectively. In the voltage generating circuit,... Agent: Kabushiki Kaisha Toshiba

20140334237 - Apparatuses, devices and methods for sensing a snapback event in a circuit: Example subject matter disclosed herein relates to apparatuses and/or devices, and/or various methods for use therein, in which an application of an electric potential to a circuit may be initiated and subsequently changed in response to a determination that a snapback event has occurred in a circuit. For example, a... Agent:

20140334235 - Memory macro configuration and method: A memory macro comprises a plurality of memory array segments, each having a predetermined number of data inputs and outputs. A segment decoder circuit is configured to: receive a first value indicating a number of memory partitions among which the memory array segments are to be divided, and output a... Agent: Taiwan Semiconductor Manufacturing Co., Ltd.

20140334236 - Low-power source-synchronous signaling: A method of operating a memory controller is disclosed. The method includes transmitting data signals to a memory device over each one of at least two parallel data links. A timing signal is sent to the memory device on a first dedicated link. The timing signal has a fixed phase... Agent:

20140334238 - Low power memory device: A method of operation within a memory device is disclosed. The method comprises receiving address information and corresponding enable information in association with a memory access request. The address information includes a row address that specifies a row of storage cells within a storage array of the memory device, and... Agent: Rambus Inc.

20140334239 - I/o circuit with phase mixer for slew rate control: An apparatus includes a terminal, a first plurality of driver lines, and a first phase mixer. The driver lines drive the terminal to a first logic state responsive to a first enable signal. The first phase mixer is coupled to a first one of the first plurality of driver lines.... Agent:

20140334240 - Semiconductor integrated circuit device: An output signal characteristic of a differential amplifier circuit is improved. When an input data signal becomes ‘Low’, current flowing through a first transistor will decrease and potential at a connection (a node) between a first resistor and a second resistor will increase. This potential is input (negatively fed back)... Agent: Renesas Electronics Corporation

20140334241 - Circuits, apparatuses, and methods for oscillators: Circuits, apparatuses, and methods are disclosed for oscillators. In one such example oscillator circuit, a plurality of delay stages are coupled in series. A variable delay circuit stage is coupled to the plurality of delay stages and is configured to delay a signal through the variable delay circuit stage by... Agent:

20140334242 - Semiconductor memory apparatus and method of operating using the same: A semiconductor memory apparatus includes a reset pad configured to receive and transfer an external reset signal and an external control signal; a first input buffer configured to buffer the external reset signal in response to a buffer control signal and output an internal reset signal; a second input buffer... Agent:

20140334243 - Write level training using dual frequencies in a double data-rate memory device interface: A write leveling calibration system and method for double data-rate dynamic random access memory includes performing write leveling at two different frequencies to determine to which of two successive rising clock cycle edges each data strobe signal would be aligned as a result of applying the write leveling delay determined... Agent: Avago Technologies GeneralIP(singapore) Pte. Ltd

  
11/06/2014 > 32 patent applications in 19 patent subcategories.

20140328103 - Implementing computational memory from content-addressable memory: A content-addressable memory (CAM) with computational capability is described. The CAM includes an array of CAM cells arranged in rows and columns with a pair of search lines associated with each column of the array and a match line associated with each row of the array. The array of CAM... Agent: International Business Machines Corporation

20140328105 - Methods and apparatus for layout of three dimensional matrix array memory for reduced cost patterning: Apparatus, methods, and systems are provided for a memory layer layout for a three-dimensional memory. The memory layer includes a plurality of memory array blocks; a plurality of memory lines coupled thereto; and a plurality of zia contact areas for coupling the memory layer to other memory layers in a... Agent:

20140328104 - Semiconductor device: A logic chip and memory chip stacked over the logic chip, the logic chip having a first surface facing the memory chip and a second surface opposite to the first surface and including: first and second internal input/output circuit units for exchanging signals; first external input/output circuit unit for exchanging... Agent: Sk Hynix Inc.

20140328106 - Semiconductor memory device: The memory capacity of a DRAM is enhanced. A semiconductor memory device includes a driver circuit including part of a single crystal semiconductor substrate, a multilayer wiring layer provided over the driver circuit, and a memory cell array layer provided over the multilayer wiring layer. That is, the memory cell... Agent:

20140328107 - Non-volatile semiconductor memory device: A non-volatile semiconductor memory device includes a memory cell array including a first wire, a second wire crossing the first wire, and a memory cell connected to both the wires at a crossing portion of the first wire and the second wire, the memory cell including a variable resistance element... Agent: Kabushiki Kaisha Toshiba

20140328110 - Non-volatile semiconductor memory device: A non-volatile semiconductor memory device includes a cell array layer including a first wire, a memory cell, and a second wire, and a control circuit. When performing set operation for setting the memory cell to a low resistance state, until a resistance value of the memory cell becomes lower than... Agent: Kabushiki Kaisha Toshiba

20140328109 - Semiconductor memory device: A semiconductor memory device according to an embodiment comprises a memory cell array configured from a plurality of row lines and column lines that intersect one another, and from a plurality of memory cells disposed at each of intersections of the row lines and column lines and each including a... Agent: Kabushiki Kaisha Toshiba

20140328108 - Write and erase scheme for resistive memory device: A method for programming a two terminal resistive memory device, the method includes applying a bias voltage to a first electrode of a resistive memory cell of the device; measuring a current flowing through the cell; and stopping the applying of the bias voltage if the measured current is equal... Agent:

20140328111 - Signal processing circuit and method for driving the same: An object is to provide a signal processing circuit which can be manufactured without a complex manufacturing process and suppress power consumption. A storage element includes two logic elements (referred to as a first phase-inversion element and a second phase-inversion element) which invert a phase of an input signal and... Agent:

20140328112 - Memory cell supply voltage reduction prior to write cycle: An integrated circuit device includes a memory cell coupled to a supply voltage line to receive a supply voltage and a voltage control circuit operable to reduce a magnitude of the supply voltage prior to a write cycle to the memory cell. The voltage control circuit includes a first capacitor... Agent: Advanced Micro Devices, Inc.

20140328114 - Memory device and method of operating the same: A memory device includes a memory cell, a sensing circuit connected to sense data stored in a memory cell and to connect the memory cell by first and second paths separate from one another A sample and hold circuit connected between the memory cell and the sensing circuit may separate... Agent: Samsung Electronics Co., Ltd.

20140328113 - Pre-charging bitlines in a static random access memory (sram) prior to data access for reducing leakage power, and related systems and methods: Embodiments disclosed herein include methods and apparatuses for pre-charging bitlines in a static random access memory (SRAM) prior to data access for reducing leakage power. The memory access logic circuit receives a memory access request comprising a data entry address to be accessed in a first data access path of... Agent: Qualcomm Incorporated

20140328115 - Positive edge preset reset flip-flop with dual-port slave latch: In an embodiment of the invention, a flip-flop circuit contains a 2-input multiplexer, a master latch, a transfer gate and a slave latch. The scan enable control signals SE and SEN of the multiplexer determine whether data or scan data is input to the master latch. Clock signals CKT and... Agent: Texas Instruments Incorporated

20140328117 - Initialization method of a perpendicular magnetic random access memory (mram) device with a stable reference cell: A method of initializing a magnetic random access memory (MRAM) element that is configured to store a state when electric current flows therethrough is disclosed. The MRAM element includes a first magnetic tunnel junction (MTJ) for storing a data bit and a second MTJ for storing a reference bit. Each... Agent:

20140328116 - Magnetic memory devices: A STT-MRAM comprises apparatus and a method of manufacturing a plurality of magnetoresistive memory element having a dielectric thermal buffer layer between a thin top electrode of the MTJ element and a bit line, and a bit-line VIA electrically connecting the top electrode and the bit line having a vertical... Agent: T3memory, Inc.

20140328118 - Semiconductor storage device: A semiconductor storage device according to the present embodiment includes a plurality of bit lines, a plurality of word lines, and a plurality of memory cells corresponding to intersections between the bit lines and the word lines, respectively, and including magnetic tunnel junction elements capable of storing data. A plurality... Agent:

20140328119 - Storage element and memory: A storage element includes a magnetization fixed layer, and a magnetization free layer. The magnetization fixed layer includes a plurality of ferromagnetic layers laminated together with a coupling layer formed between each pair of adjacent ferromagnetic layers. The magnetization directions of the ferromagnetic layers are inclined with respect to a... Agent:

20140328121 - Immunity of phase change material to disturb in the amorphous phase: Disturb from the reset to the set state may be reduced by creating an amorphous phase that is substantially free of crystal nuclei when programming the reset state in a phase change memory. In some embodiments, this can be achieved by using a current or a voltage to program that... Agent:

20140328120 - Systems, and devices, and methods for programming a resistive memory cell: Embodiments disclosed herein may relate to programming a memory cell with a programming pulse that comprises a quenching period having different portions.... Agent:

20140328122 - Reduced stress high voltage word line driver: Exemplary embodiments of the present invention disclose a method and system for asserting a voltage transition from a low voltage to a high voltage with a voltage difference between the low and high voltages on a word line with a word line driver logic that is composed of thin-oxide MOS... Agent: International Business Machines Corporation

20140328123 - Minimal maximum-level programming: A method for writing data, the method may include evaluating current levels of multiple memory cells that belong to a certain set of memory cells or receiving an indication about the current levels of the multiple memory cells; encoding a new data unit to provide an encoded data unit to... Agent: Technion Research And Development Foundation Ltd.

20140328124 - Semiconductor device and driving method thereof: The storage device includes a volatile first memory circuit and a nonvolatile second memory circuit which includes a transistor whose channel is formed in an oxide semiconductor layer. In the case of high-frequency driving, during a period when source voltage is applied, a data signal is input to and output... Agent:

20140328125 - Methods of forming fine patterns in semiconductor devices: Methods of forming a semiconductor device may include providing a feature layer having a first region and a second region. The methods may also include forming a dual mask layer on the feature layer. The methods may further include forming a variable mask layer on the dual mask layer. The... Agent:

20140328126 - Flash memory having dual supply operation: A flash memory device may operate from two supply voltages, one being provided externally, and the other being generated within the flash memory device from the external supply voltage. The flash memory device may be provided with a selectable-level buffer for interfacing with either low supply voltage or high supply... Agent: Winbond Electronics Corporation

20140328127 - Method of managing non-volatile memory and non-volatile storage device using the same: A method of managing a non-volatile memory where the non-volatile memory comprises a plurality of memory blocks and each of the plurality of memory blocks includes a plurality of memory pages includes partitioning a memory page among the plurality of memory pages into a plurality of clusters; and writing data... Agent: Skymedi Corporation

20140328128 - Nand string utilizing floating body memory cell: NAND string configurations and semiconductor memory arrays that include such NAND string configurations are provided. Methods of making semiconductor memory cells used in NAND string configurations are also described.... Agent: Zeno Semiconductor, Inc.

20140328129 - Non-volatile semiconductor storage device: According to one embodiment, there is provided a non-volatile semiconductor storage device including a non-volatile memory, a monitoring section, a determining section, and a notification processing section. The non-volatile memory includes a plurality of memory cells driven by word lines and a voltage generating section that generates a read voltage... Agent: Kabushiki Kaisha Toshiba

20140328131 - Inter-word-line programming in arrays of analog memory cells: A method includes selecting a word line for programming in an array of analog memory cells that are arranged in rows associated with respective word lines and columns associated with respective bit lines. Word-line voltages, which program the memory cells in the selected word line, are applied to the respective... Agent:

20140328130 - Integrated circuit with bump connection scheme: An integrated circuit includes first and second bump pads spaced from each other with a first space, configured to receive differential signals for a normal operation, and at least one redundant bump pad spaced from the first bump pad with a second space smaller than the first space, configured to... Agent: Sk Hynix Inc.

20140328132 - Memory margin management: A method for testing and correcting a memory system is described. The method includes selecting a target memory unit of the memory system having a timing margin in response to a trigger to start a timing margin measurement. The stored data in the target memory unit is moved to a... Agent: International Business Machines Corporation

20140328133 - Semiconductor device, control method thereof and data processing system: Disclosed herein is a semiconductor device comprising a global bit line, a first local bit line coupled to normal memory cells, a second local bit line coupled to redundant memory cells first and second hierarchical switches, a precharge circuit precharging the global bit line, a redundancy determination circuit determining whether... Agent:

20140328134 - Sense amplifiers, memories, and apparatuses and methods for sensing a data state of a memory cell: Sense amplifiers, memories, and apparatuses and methods for sensing a data state of a memory cell are disclosed. An example apparatus includes a differential amplifier configured to amplify a voltage difference between voltages applied to first and second amplifier input nodes to provide an output. The example apparatus further includes... Agent:

  
10/30/2014 > 45 patent applications in 25 patent subcategories.

20140321185 - Four port memory with multiple cores: A memory cluster includes a first block, a second block, a third block, and a fourth block arranged to have a center hole, wherein the first, second, third, and fourth blocks are each have a first port, a second port, a third port, and a fourth port. A first core... Agent:

20140321187 - Semiconductor device: According to an embodiment, a semiconductor device includes a substrate, a connector, a volatile semiconductor memory element, multiple nonvolatile semiconductor memory elements, and a controller. A wiring pattern includes a signal line that is formed between the connector and the controller and that connects the connector to the controller. On... Agent: Kabushiki Kaisha Toshiba

20140321186 - Stacked memory with redundancy: A stacked memory is disclosed including a first integrated circuit memory chip having first storage locations and a second integrated circuit memory chip disposed in a stacked relationship with the first integrated circuit memory chip. The second integrated circuit memory chip has second storage locations. Redundant storage is provided including... Agent:

20140321188 - Memory devices having data lines included in top and bottom conductive lines: Some embodiments include apparatuses and methods having a first set of conductive lines, a second set of conductive lines, and memory cells located in different levels of the apparatuses and arranged in memory cell strings. At least a portion of the first set of conductive lines is configured as a... Agent:

20140321189 - Systems and methods for stacked semiconductor memory devices: Systems and methods are provided for stacked semiconductor memory devices. The stacked semiconductor memory devices can include a nonvolatile memory controller, a number of nonvolatile memory dies arranged in a stacked configuration, and a package substrate. The memory controller and the memory dies can be coupled to each other with... Agent:

20140321190 - Vertical switch three-dimensional memory array: A memory device includes a substrate, and, disposed thereover, an array of vertical memory switches. In some embodiments, each switch has at least three terminals and a cross-sectional area less than 6 F2.... Agent:

20140321193 - 3d variable resistance memory device and method of manufacturing the same: A variable resistance memory device includes a plurality of cell gate electrodes extending in a first direction, wherein the plurality of cell gate electrodes are stacked in a second direction that is substantially perpendicular to the first direction. A gate insulating layer surrounds each cell gate electrode of the plurality... Agent: Sk Hynix Inc.

20140321195 - Current generator for nonvolatile memory device and write and/or read currents calibrating method using the same: A write and/or read current generator for nonvolatile memory device, especially for Spin Transfer Torque Magnetoresistive Random Access Memory (STT-MRAM), may include a current supplying circuit which changes a level of a sample current, determines a resistance state change current of a sample bit cell based on a feedback signal... Agent:

20140321197 - Driving method of non-volatile memory element and non-volatile memory device: In a driving method of a non-volatile memory element, the polarity of a write voltage pulse applied to change a variable resistance layer from a high-resistance state to a low-resistance state is such that an input/output terminal which is more distant from the variable resistance element becomes a source terminal,... Agent:

20140321198 - Memory devices and related methods: A resistive memory device. Implementations may include an array of memory cells including resistive memory elements which are coupled to isolation transistors and which may include a magnetic tunnel junction. A decoder decodes input address information to select a row of the array. A binarizer coupled to the memory array... Agent:

20140321194 - Nonvolatile semiconductor memory device and control method thereof: This nonvolatile semiconductor memory device comprises a memory cell array including a plurality of bit lines, a plurality of word lines intersecting the plurality of bit lines, and memory cells provided at intersections of the plurality of bit lines and the plurality of word lines, and further comprises a control... Agent: Kabushiki Kaisha Toshiba

20140321191 - Resistance variable memory sensing: The present disclosure includes apparatuses and methods for sensing a resistance variable memory cell. A number of embodiments include programming a memory cell to an initial data state and determining a data state of the memory cell by applying a programming signal to the memory cell, the programming signal associated... Agent: Micron Technology, Inc.

20140321192 - Resistance variable memory sensing: The present disclosure includes apparatuses and methods for sensing a resistance variable memory cell. A number of embodiments include circuitry to apply a programming signal to a memory cell in the array, the programming signal associated with programming resistance variable memory cells to a particular data state, and detect a... Agent: Micron Technology, Inc.

20140321196 - Variable resistance nonvolatile memory device and method for writing into the same: In a method for writing into a variable resistance nonvolatile memory device according to one aspect of the present disclosure, a verify write operation of newly applying a voltage pulse for changing a resistance state is performed on a variable resistance element which does not satisfy a determination condition for... Agent: Panasonic Corporation

20140321199 - Nano multilayer film, field effect tube, sensor, random accessory memory and preparation method: Disclosed are nano multilayer film of electrical field modulation type, a field effect transistor of electrical field modulation type, an electrical field sensor of switch type, and a random access memory of electrical field drive type, for obtaining an electro-resistance effect in an electrical field modulation multilayer film at room... Agent: Institute Of Physics, Chinese Academy Of Sciences

20140321201 - Devices and methods to program a memory cell: Subject matter disclosed herein relates to memory devices and, more particularly, to programming a memory cell.... Agent:

20140321200 - Phase change memory with flexible time-based cell decoding: Methods and systems for time-based cell decoding for PCM memory. Generally, the higher the PCM element resistance, the longer it takes for a read output to change state. PCM memory output is determined using differentiated timings of read outputs changing state, rather than differentiated values of read outputs. In some... Agent: Being Advanced Memory Corporation

20140321202 - Defective block management: In a flash memory, erase blocks containing shorted or broken word lines may be used, at least in part, to store user data. Such blocks may use different parameters to those used by non-defective blocks, may be subject to different wear leveling, and may store data selected to reduce the... Agent: Sandisk Technologies, Inc.

20140321204 - Method and apparatus for optimizing reference voltages in a nonvolatile memory: A system including a divider module, a read module, a counting module, and a reference voltage setting module. The divider module is configured to select a voltage range in which to adjust a reference voltage used to read memory cells of nonvolatile memory, and to divide the voltage range into... Agent:

20140321203 - Method for performing memory access management, and associated memory device and controller thereof: A method for accessing a memory includes: utilizing a Flash memory to perform a plurality of sensing operations with a plurality of different sensing voltages respectively corresponding to the plurality of sensing operations; according to the plurality of sensing operations, generating a first digital value of a Flash cell of... Agent:

20140321205 - Memory device page buffer configuration and methods: Memory devices and methods are described that include communication circuitry between page buffers in a memory array. Examples include communication circuitry that provide status information of page buffers that are directly adjacent to a given page buffer. The exchanged information can be used to adjust a given page buffer to... Agent:

20140321206 - Reading memory cell history during program operation for adaptive programming: Subject matter disclosed herein relates to a memory device, and more particularly to write performance of a memory device.... Agent:

20140321208 - De-duplication in flash memory module: Data capacity efficiency is improved by de-duplicating data assigned with a code that is different for each data. A storage apparatus comprising a flash memory control device equipped with one or more flash memory modules, wherein the flash memory module comprises at least one flash memory chip for providing a... Agent: Hitachi, Ltd.

20140321207 - Determining soft data for combinations of memory cells: The present disclosure includes apparatuses and methods for determining soft data for combinations of memory cells. A number of embodiments include an array of memory cells, wherein the array includes a first memory cell and a second memory cell, wherein the first and second memory cells are each programmable to... Agent: Micron Technology, Inc.

20140321209 - Non-volatile memory device and related read method: A nonvolatile memory device comprises a memory cell array and a voltage generator. The memory cell array comprises a plurality of memory cells connected in series between a string selection transistor connected to a bit line and a ground selection transistor connected to a source line. The voltage generator provides... Agent:

20140321210 - Method for processing data, flash memory, and terminal: Embodiments of the present invention provide a flash memory which has high operating efficiency and a longer service life, and relate to the field of electronic technologies. The flash memory includes a control circuit and a plurality of memory cells, where the memory cell is a floating-gate MOS transistor which... Agent:

20140321211 - Non-volatile memory (nvm) with variable verify operations: A method of erasing a non-volatile memory (NVM) array includes determining a first number based on a temperature of the NVM array. Erase pulses of the first number are applied to the NVM array. A first verify of the NVM is performed for a first time after commencing the applying... Agent:

20140321212 - Non-volatile memory (nvm) with variable verify operations: A method of soft programming a non-volatile memory (NVM) array includes determining a first number based on a temperature of the NVM array and applying the first number of soft program pulses to a section of the NVM array. A first soft program verify of the section of the NVM... Agent: Freescale Semiconductor, Inc.

20140321213 - Biasing split gate memory cell during power-off mode: A non-volatile memory (NVM) system has a normal mode, a standby mode and an off mode that uses less power than the standby mode. The NVM system includes an NVM array that includes NVM cells and NVM peripheral circuitry. Each NVM cell includes a control gate. A controller is coupled... Agent:

20140321214 - Programming memory cells: Methods for programming memory cells. One such method for programming memory cells includes generating an encoded stream using a data stream and programming the memory cells using the encoded stream to represent the data stream. A particular bit position of the encoded stream has a first voltage level when the... Agent: Micron Technology, Inc.

20140321215 - Inhibiting pillars in 3d memory devices: Methods and controllers for programming a memory are provided. In one such method, a potential for pillars of the memory that are to be inhibited is lowered, and programming cells of the memory is accomplished while the pillars of the memory that are to be inhibited have the lower potential.... Agent: Micron Technology, Inc.

20140321216 - Random telegraph signal noise reduction scheme for semiconductor memories: Embodiments are provided that include a method including providing a first pulsed gate signal to a selected memory cell, wherein the pulsed gate signal alternates between a first voltage level and a second voltage level during a time period and sensing a data line response to determine data stored on... Agent:

20140321221 - Semiconductor integrated circuit with thick gate oxide word line driving circuit: A semiconductor integrated circuit according to one aspect of the present invention may includes a plurality of driving circuits to drive a respective plurality of word lines with either a first voltage supplied from a first power supply or a second voltage supplied from a second power supply in accordance... Agent:

20140321217 - Apparatus and method for reading data from multi-bank memory circuits: The disclosure relates to an apparatus for reading data from a memory circuit that includes at least two memory banks. The apparatus includes a first multiplexer configured to generate data at a first output from a first selected one of a first set of bit lines of a first memory... Agent:

20140321218 - Techniques for accessing memory cells: Techniques for accessing memory cells are disclosed. In one particular embodiment, the techniques may be realized as an apparatus providing voltage to a high impedance node of a memory cell. The apparatus may comprise a precharge switch coupled to a first voltage source node, a precharge capacitor coupled to the... Agent: Micron Technology, Inc.

20140321219 - Semiconductor device: A semiconductor device includes: a plurality of repair fuse circuits configured to each program a repair target address; and an enable signal generation circuit configured to generate at least one enable signal in response to a source signal and provide the enable signal to each of the repair fuse circuits... Agent: Sk Hynix Inc.

20140321220 - Semiconductor memory apparatus and method of controlling external voltage using the same: A semiconductor memory apparatus according to the embodiment includes: an external connection terminal configured to supply an external voltage; a fuse unit configured to perform a fuse rupture operation; and an interruption circuit unit configured to respond to a test signal to determine whether the external connection terminal is connected... Agent: Sk Hynix Inc.

20140321222 - Semiconductor memory of which defective cell is replaceable with redundant cell and manufacturing method of semiconductor memory: A semiconductor memory includes a memory cell array that includes data cells of x bits and redundant cells of y bits for each word; a position-data storage unit that stores, for each word, defective-cell position data of defective cells of the data cells and the redundant cells; and a read... Agent: Fujitsu Limited

20140321224 - Semiconductor device: There is provided a semiconductor device including a first logic circuit to operate based on a first power supply and a second power supply, and a second logic circuit to operate based on the first power supply and a third power supply boosted from the second power supply. The second... Agent:

20140321223 - Semiconductor device and method of manufacturing the same: A semiconductor device includes a controller chip, a plurality of semiconductor chips operatively connected to the controller chip, wherein at least one of the plurality of semiconductor chips is operatively supplied with a pulse signal from the controller chip, and operatively supplied identification information, wherein each of the plurality of... Agent:

20140321225 - Sense amplifier with dual gate precharge and decode transistors: The invention relates to a sense amplifier for sensing and amplifying data stored in a memory cell, the sense amplifier being connected between a bit line (BL) and a reference bit line complementary (/BL) to the first bit line and comprising: a sense circuit (SC) capable of providing an output... Agent: Soitec

20140321226 - Dynamic random access memory and boosted voltage producer therefor: A dynamic random access memory (DRAM) is selectively operable in a sleep mode and another mode. The DRAM has data storage cells that are refreshed in the refresh mode. A boosted voltage is provided for the operation of the DRAM. A boosted voltage provider includes a group of charge pump... Agent:

20140321227 - Frequency power manager: A method and an apparatus are provided. The apparatus is a hardware module that controls a power mode of a plurality of modules. The apparatus receives an indication of a desired operational frequency. Based on the received indication, the apparatus determines to switch from a first power mode associated with... Agent: Qualcomm Incorporated

20140321228 - Semiconductor device including plural chips stacked to each other: A method for accessing a plurality of DRAM devices each having a plurality of banks, includes determining an operating mode for the plurality of DRAM devices, providing a chip selection address and a bank address with an active command to activate a first bank in a first one of the... Agent:

20140321229 - System and method for per-bit de-skew for datamask in a double data-rate memory device interface: In a training mode, per-bit de-skew (PBDS) values for a datamask signal in a synchronous dynamic random access memory are iteratively adjusted in conjunction with writing test patterns to the memory and reading back test patterns from the memory until optimum datamask PBDS values are determined.... Agent:

  
10/23/2014 > 41 patent applications in 27 patent subcategories.

20140313807 - Content addressable memory device: A content addressable memory device capable of making simultaneous pursuit of low power consumption and speeding up is provided. A match amplifier A determines coincidence or non-coincidence of search data and data stored in a content addressable memory in an entry of a memory array A, according to a voltage... Agent:

20140313808 - Content addressable memory chip: A content addressable memory chip which can perform a high speed search with less error is provided. A match amplifier zone determines coincidence or non-coincidence of search data with data stored in the content addressable memory cells in an entry of a CAM cell array, according to the voltage of... Agent:

20140313809 - Semiconductor apparatus: A semiconductor device may include first conductive patterns coupled to a common source and selection lines of a memory block formed at a substrate, second conductive patterns configured to form a bit line coupled to the memory block, and third conductive patterns configured to transmit a block selection signal to... Agent: Sk Hynix Inc.

20140313811 - Semiconductor device: A semiconductor device with a memory unit of which the variations in the operation timing are reduced is provided. For example, the semiconductor device is provided with dummy bit lines which are arranged collaterally with a proper bit line, and column direction load circuits which are sequentially coupled to the... Agent:

20140313810 - Switchably coupled digit line segments in a memory device: A memory array includes segmented global and local digit lines in which the global digit line segments are switchably coupled to one of a plurality of local digit line segments at a time. A sense circuit coupled to a global digit line segment can be switched to sense memory cells... Agent: Micron Technology, Inc.

20140313814 - Performing forming processes on resistive memory: The present disclosure includes apparatuses and methods for performing forming processes on resistive memory. A number of embodiments include applying a formation signal to the storage element of a resistive memory cell, wherein the formation signal includes a first portion having a first polarity and a first amplitude, a second... Agent: Micron Technology, Inc.

20140313816 - Select device for cross point memory structures: The present disclosure provides a memory cell that includes a resistive memory element disposed between a first conductor and a second conductor, the first conductor and the second conductor configured to activate the resistive memory element. The memory cell also includes a backward diode disposed in series with the memory... Agent:

20140313812 - Semiconductor device, and microprocessor, processor, system, data storage system and memory system including the semiconductor device: A semiconductor device includes: a write current generator configured to generate a write current corresponding to a write reference voltage in a write mode and to have a negative feedback structure. The semiconductor device may further comprise a variable resistance device configured to have a resistance value that varies with... Agent: Sk Hynix Inc.

20140313813 - Semiconductor memory device and operation method thereof: This semiconductor memory device comprises: a memory cell array including plural bit lines, plural word lines intersecting the plurality of bit lines, and memory cells provided at intersections of the plural bit lines and the plural word lines; and a control unit operative to control a voltage applied to the... Agent: Kabushiki Kaisha Toshiba

20140313815 - Word line selection circuit and row decoder: A first exemplary aspect of the present invention is a word line selection circuit where address decode signals composed of a power supply voltage and a first voltage lower than a ground voltage are input, and that a word line selection signal composed of the first voltage and a second... Agent:

20140313818 - Metal-insulator phase transition flip-flop: A metal-insulator phase transition (MIT) flip-flop employs a selected one of a pair of bi-stable operating states to represent a logic state of the MIT flip-flop. The MIT flip-flop includes an MIT device having a current-controlled negative differential resistance (CC-NDR) to provide the pair of bi-stable operating states. A bi-stable... Agent:

20140313817 - Sram core cell design with write assist: A static random access memory (SRAM) cell is disclosed. The SRAM cell includes a storage unit configured to store a data bit in a storage node. The SRAM cell further includes an access unit coupled to the storage unit. The access unit is configured to transfer current to the storage... Agent: Nvidia Corporation

20140313819 - System on chip including dual power rail and voltage supply method thereof: A system on chip includes an SRAM. The SRAM includes at least one memory cell and a peripheral circuit accessing the at least memory cell. A first power circuit is configured to supply a first driving voltage to the at least one memory cell. A second power circuit is configured... Agent: Samsung Electronics Co., Ltd.

20140313820 - Field programming method for magnetic memory devices: In one embodiment of the invention, there is provided a method for operating a magnetic memory device. The method comprises selecting a subset of magnetic memory cells of the magnetic memory device; applying a first programming voltage to the selected subset of cells for a predetermined amount of time, wherein... Agent:

20140313821 - Fin-type device system and method: A fin-type device system and method is disclosed. In a particular embodiment, a transistor is disclosed and includes forming a gate of a transistor within a substrate having a surface and a buried oxide (BOX) layer within the substrate and adjacent to the gate at a first BOX layer face.... Agent:

20140313822 - Group classification method for solid state storage device: A group classification method includes the following steps. Firstly, a voltage shift parameter table is established. The voltage shift parameter table includes a first positional parameter table corresponding to a first neighboring cell. Then, MN ICI patterns are determined according to N neighboring cells having a significant ICI effect. If... Agent: Lite-on It Corporation

20140313824 - Data storage system having multi-bit memory device and operating method thereof: A data storage device includes a non-volatile memory device which includes a memory cell array; and a memory controller which includes a buffer memory. The operating method of the data storage device includes storing data in the buffer memory, and determining whether the data stored in the buffer memory is... Agent:

20140313825 - Drain select gate voltage management: Some embodiments include apparatus, systems, and methods that operate to apply a first value of a drain select gate voltage during a first portion of a programming time period associated with programming a plurality of memory cells, and to apply a second value of the drain select gate voltage different... Agent:

20140313823 - Nonvolatile memory device, system and programming method with dynamic verification mode selection: Nonvolatile memory devices, memory systems and related methods of operating nonvolatile memory devices are presented. During a programming operation, the nonvolatile memory device is capable of using bit line forcing, and is also capable of selecting a verification mode for use during a verification operation from a group of verification... Agent:

20140313826 - Off-die charge pump that supplies multiple flash devices: A system and method for storing data uses multiple flash memory dies. Each flash memory die includes multiple flash memory cells. A charge pump is adapted to supply charge at a predetermined voltage to each flash memory die of the flash memory dies, and an interface is adapted to receive... Agent:

20140313827 - Memory circuit: The present invention provides a memory circuit in which, while the power is not supplied, a data signal that has been held in a memory section corresponding to a volatile memory can be held in a capacitor in a memory section corresponding to a nonvolatile memory. In the nonvolatile memory... Agent:

20140313829 - Nonvolatile semiconductor memory device: A nonvolatile semiconductor memory device comprises a plurality of memory blocks, each including a plurality of cell units and each configured as a unit of execution of an erase operation. Each of the cell units comprises a memory string, a first transistor, a second transistor, and a diode. The first... Agent: Kabushiki Kaisha Toshiba

20140313828 - Sharing support circuitry in a memory: A memory device, system, and method for operation of a memory device are disclosed. In one such memory device, the memory device comprises a plurality of strings of memory cells. A plurality of drain select devices are coupled to each string of memory cells. An upper drain select device shares... Agent: Micron Technology, Inc.

20140313831 - Device selection schemes in multi chip package nand flash memory system: Device selection schemes in multi-chip package NAND flash memory systems are provided. A memory system is provided that has a memory controller, and a number of memory devices connected to the controller via a common bus with a multi-drop connection. The memory controller performs device selection by command. A corresponding... Agent:

20140313830 - Page buffer circuit: A page buffer circuit is coupled to a bit line of a memory array. The page buffer circuit includes a latch storing different data during different phases of a multi-phase program operation. A preparation phase is after the program phase and after the program verify phase of the present multi-phase... Agent: Macronix International Co., Ltd.

20140313832 - Enhanced data storage in 3-d memory using string-specific source-side biasing: A method includes storing data in a memory, which includes multiple strings of analog memory cells arranged in a three-dimensional (3-D) configuration having a first dimension associated with bit lines, a second dimension associated with word lines and a third dimension associated with sections, such that each string is associated... Agent: Apple Inc.

20140313833 - Memory devices with a connecting region having a band gap lower than a band gap of a body region: Memory devices are shown that include a body region and a connecting region that is formed from a semiconductor with a lower band gap than the body region. Connecting region configurations can provide increased gate induced drain leakage during an erase operation. Configurations shown can provide a reliable bias to... Agent:

20140313834 - Retention optimized memory device using predictive data inversion: A method for storing data. The method includes providing an addressable memory including a memory space, wherein the memory space includes a plurality of memory cells. The method includes configuring the addressable memory such that a majority of the plurality of memory cells in the memory space stores internal data... Agent: Invensas Corporation

20140313835 - Semiconductor memory device and data programming method thereof: A data programming method of a semiconductor memory device is provided which includes randomizing write data using a randomization method selected from among a plurality of randomization methods according to whether the write data is programmed in one of a plurality of nonvolatile memories; and programming the randomized write data... Agent:

20140313836 - High speed signaling techniques to improve performance of integrated circuits: Techniques are presented to improve the performance, accuracy and power consumption of on-chip voltage biasing and transmission for highly loaded RC networks (such as wordlines or bitlines in NAND or 3D memory arrays) that are otherwise limited by the physics of RC time constant. When transitioning the near-end voltage of... Agent:

20140313837 - Dynamic burst length output control in a memory: A memory, a system and a method for controlling dynamic burst length control data can generate clocks for both an upstream counter and a downstream counter by using substantially the same latency delayed received command indications. A downstream clock generation circuit generates a clock signal from a received command indication... Agent: Micron Technology, Inc.

20140313838 - Reconfigurable load-reduced memory buffer: A memory module can include a data buffer having a data bus interface and a dynamic random access memory (DRAM) coupled to the data buffer. The memory module may also include a switch connected in parallel with the data buffer, wherein the switch can selectively bypass the data buffer. In... Agent:

20140313839 - Sequential memory operation without deactivating access line signals: Some embodiments include apparatuses and methods for activating a signal associated with an access line coupled to different groups of memory cells during a memory operation of a device, and for sensing data lines of the device during different time intervals of the memory operation to determine the value of... Agent: Micron Technology, Inc.

20140313840 - Integrated circuit and memory device: An integrated circuit includes a programmable storage unit suitable for operating with a plurality of powers and outputting stored data in response to a boot-up signal, a register unit suitable for storing the data outputted from the programmable storage unit, a internal circuit suitable for operating by using the data... Agent: Sk Hynix Inc.

20140313841 - Integrated circuit with programmable storage cell array and boot-up operation method thereof: An integrated circuit may include a first programmable storage cell group suitable for storing program validity information, second to N-th programmable storage cell groups suitable for storing a plurality of data, wherein N is an integer equal to or more than 3, and a validity determination unit suitable for determining... Agent: Sk Hynix Inc.

20140313842 - E-fuse array circuit: An e-fuse array circuit includes: an e-fuse transistor of a vertical gate type configured to have a gate for receiving a voltage of a program gate line and have one between a drain terminal and a source terminal floating; and a selection transistor of a buried gate type configured to... Agent: Sk Hynix Inc.

20140313843 - Semiconductor integrated circuit and control method therefor: A semiconductor integrated circuit includes a plurality of first non-volatile registers including a retention circuit that retains volatile data and one or more non-volatile elements capable of retaining non-volatile data, and a second non-volatile register that retains a load enable bit that decides in which one of the plurality of... Agent: Nec Corporation

20140313844 - Flexible input/output transceiver: An I/O transceiver includes a driver with a feedback circuit having a mode select signal input, a serial data signal input, and a driver output signal input. The feedback circuit can provide a feedback control signal that is coupled to a pre-driver circuit. The pre-driver circuit can modify a data... Agent: Micron Technology, Inc

20140313845 - Semiconductor chip, semiconductor integrated circuit including the semiconductor chip, semiconductor system including the semiconductor integrated circuit and method of driving the semiconductor system: A semiconductor system including a semiconductor integrated circuit or a semiconductor chip, and a method of driving the semiconductor system are described. The semiconductor integrated circuit includes a plurality of semiconductor chips, at least one first chip through via suitable for penetrating through the plurality of semiconductor chips and interfacing... Agent: Sk Hynix Inc.

20140313846 - Driver and memory controller having the same: A memory controller includes a bus driver that allows the controller to support both a semiconductor memory device supporting a low power double data rate 3 (LPDDR3) transmission method and a semiconductor memory device supporting a low power double data rate 4 (LPDDR4) transmission method.... Agent:

20140313847 - Clock synchronization circuit and semiconductor memory device including clock synchronization circuit: A clock synchronization circuit includes a delay-locked loop (DLL) and a delay-locked control unit. The DLL is configured to generate an output clock signal by delaying an input clock signal by a delay time, and to execute a delay-locking operation in which the delay time is adjusted to a locked... Agent: Samsung Electronics Co., Ltd.

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