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Static information storage and retrievalBelow are recently published patent applications awaiting approval from the USPTO. Recent week's RSS XML file available below.
Listing for abstract view: USPTO application #, Title, Abstract excerpt,Patent Agent. Listing format for list view: USPTO National Class full category number, title of the patent application. 01/22/2015 > 38 patent applications in 28 patent subcategories.
20150023085 - Semiconductor storage device: A semiconductor storage device according to the present embodiment includes a plurality of bit lines, a plurality of word lines, and a plurality of memory cells each including a storage element and a switching element which are connected in series between adjacently paired ones of the bit lines. Gates of... Agent:
20150023086 - Multiport memory cell having improved density area: A mutltiport memory cell having improved density area is disclosed. The memory cell includes a data storing component, a first memory access component coupled to a first side of the data storing component, a second memory access component coupled to a second side of the data storing component, first and... Agent: Soft Machines, Inc.
20150023087 - Semiconductor memory: A semiconductor memory includes a memory cell array having a plurality of memory cells, a plurality of bit line pairs which are disposed corresponding to respective columns of the memory cell array, and a sense amplifiers which are disposed in plurality corresponding to the plurality of bit line pairs for... Agent:
20150023088 - Apparatuses and methods for sensing fuse states: Apparatuses and methods for sensing fuse states are disclosed herein. An apparatus may include an array having a plurality of sense lines. A plurality of cells may be coupled to a sense line of the plurality of sense lines. A fuse sense circuit may coupled to the sense line of... Agent:
20150023089 - Resistance variable element methods and apparatuses: Apparatus and methods are disclosed, including a method that performs a first operation on a first resistance variable element using a common source voltage, a first data line voltage and a first control gate voltage, and then performs a second operation on a second resistance variable element using the common... Agent: Micron Technology, Inc.
20150023090 - Semiconductor memory device: To increase a storage capacity of a memory module per unit area, and to provide a memory module with low power consumption, a transistor formed using an oxide semiconductor film, a silicon carbide film, a gallium nitride film, or the like, which is highly purified and has a wide band... Agent:
20150023091 - Semiconductor device having timing control for read-write memory access operations: A semiconductor device avoids the disturb problem and the collision between write and read operations in a DP-SRAM cell or a 2P-SRAM cell. The semiconductor device 1 includes a write word line WLA and a read word line WLB each coupled to memory cells 3. A read operation activates the... Agent: Renesas Electronics Corporation
20150023093 - Method of writing to a spin torque magnetic random access memory: Circuitry and a method provide an increased tunnel barrier endurance (lifetime) previously shortened by dielectric breakdown by providing a pulse of opposite polarity associated with a write pulse. The pulse of opposite polarity may comprise equal or less width and amplitude than that of the write pulse, may be applied... Agent: Everspin Technologies Inc.
20150023092 - Ring-shaped magnetoresistive memory device and writing method thereof: A ring-shaped magnetoresistive memory device includes a ring-shaped magnetoresistive memory cell, a first conductor, and a second conductor. The first conductor is positioned on a first surface of the ring-shaped magnetoresistive memory cell for generating a first magnetic field pulse. The second conductor is positioned on a second surface of... Agent: National Yunlin University Of Science And Technology
20150023095 - Apparatuses including current compliance circuits and methods: Apparatus, devices, systems, and methods are described that include variable state material data storage. Example devices include current compliance circuits that are configured to dynamically adjust a current passing through a variable resistance material during a memory operation. Some configurations utilize components within an array of memory cells to form... Agent:
20150023094 - Drift mitigation for multi-bits phase change memory: An RC-based sensing method and computer program product to effectively sense the cell resistance of a programmed Phase Change Material (PCM) memory cell. The sensing method ensures the same physical configuration of each cell (after programming): same amorphous volume, same trap density/distribution, etc. The sensing method is based on a... Agent:
20150023096 - Counterbalanced-switch mram: A magnetic memory cell is provided. The cell comprises first and second free layers; and an intermediate layer separating the first and second free layers, wherein the first and second free layers are magnetostatically coupled.... Agent: Magsil Corporation
20150023099 - Direct multi-level cell programming: A method is performed in a data storage device that includes a controller coupled to a non-volatile memory. The non-volatile memory includes a group of storage elements. Each storage element is configured to store multiple data bits. Data is sent from the controller to the non-volatile memory and first bits... Agent: Sandisk Technologies Inc.
20150023098 - Operation method of multi-level memory: An operation method of a multi-level memory is provided. A first read voltage lower than a standard read voltage is applied to a doped region in a substrate at one side of a control gate of the memory, so as to determine whether a first storage position and a second... Agent:
20150023097 - Partial reprogramming of solid-state non-volatile memory cells: Method and apparatus for managing data in a memory, such as a flash memory array. In accordance with some embodiments, data are written to a set of solid-state non-volatile memory cells so that each memory cell in the set is written to an associated initial programmed state. Drift in the... Agent: Seagate Technology LLC
20150023100 - Dynamic regulation of memory array source line: To maintain stability of memory array operations, a current source supplies a common source line of a memory. The magnitude of the regulation current from the source is dynamically determined based on the amount of current from the array itself through use of a feedback control signal provided by a... Agent:
20150023101 - Memory system and method of controlling memory system: According to one embodiment, a low power direction received from a host device is delayed for a first predetermined time and is output as a first signal, and an internal state is caused to transition to a low power consumption mode that corresponds to the low power direction when a... Agent: Kabushiki Kaisha Toshiba
20150023102 - Nonvolatile semiconductor memory device: In a writing operation, a control circuit raises the voltage of a writing-prohibited bit line among a plurality of bit lines to a first voltage, and thereafter brings the writing-prohibited bit line into a floating state. Then, the control circuit raises the voltage of a writing bit line other than... Agent: Kabushiki Kaisha Toshiba
20150023103 - Semiconductor device and method of operating the same: A semiconductor device includes first memory blocks arranged in a longitudinal direction, and including a plurality of strings, wherein the strings are formed along a vertical direction, and the strings adjacent to each other share bit lines or source lines with each other, each string including a drain selection transistor... Agent: Sk Hynix Inc.
20150023104 - Apparatuses and methods for measuring an electrical characteristic of a model signal line and providing measurement information: Apparatuses and methods for measuring an electrical characteristic of a model signal line and providing measurement information based at least in part on the measurement of the electrical characteristic. An example apparatus includes a signal line model including a model signal line configured to model electrical characteristics of a signal... Agent:
20150023105 - Memory cell comprising first and second transistors and methods of operating: Semiconductor memory cells, array and methods of operating are disclosed. In one instance, a memory cell includes a bi-stable floating body transistor and an access device; wherein the bi-stable floating body transistor and the access device are electrically connected in series.... Agent:
20150023106 - Adaptive erase recovery for non-volatile memory (nvm) systems: Methods and systems are disclosed for adaptive erase recovery of non-volatile memory (NVM) cells within NVM systems. The adaptive erase recovery embodiments adaptively adjust the erase recovery discharge rate and/or discharge time based upon the size of NVM block(s) being erased and operating temperature. In one example embodiment, the erase... Agent:
20150023107 - Nonvolatile semiconductor memory device: A first non-selected word line including a word line adjacent to a selected word line is applied with a first write pass voltage. Furthermore, a second non-selected word line which is a non-selected word line excluding the first non-selected word line is applied with a second write pass voltage smaller... Agent: Kabushiki Kaisha Toshiba
20150023108 - Nonvolatile memory device and related programming method: A nonvolatile memory device comprises a memory cell array comprising multiple memory cells disposed at intersections of corresponding word lines and bitlines, and multiple page buffers connected to the bitlines, respectively, and performing consecutive verify read operations on selected memory cells programmed in first to N-th logic states (N>2), wherein,... Agent: Samsung Electronics Co., Ltd.
20150023109 - Nonvolatile semiconductor memory device: A nonvolatile semiconductor memory device comprises a memory cell array, a staircase voltage generator, and a decode and level shift circuit. The memory cell array comprises a plurality of memory cells and a plurality of bit lines coupled to the plurality of memory cells. The staircase voltage generator generates a... Agent: Elite Semiconductor Memory Technology Inc.
20150023110 - Inferring threshold voltage distributions associated with memory cells via interpolation: The present disclosure includes apparatuses and methods for inferring threshold voltage distributions associated with memory cells via interpolation. A number of embodiments include determining soft data for a group of memory cells each programmed to one of a number of data states, wherein the soft data comprises a number of... Agent:
20150023111 - Nonvolatile semiconductor memory device: A nonvolatile semiconductor memory device of an embodiment includes a p-type semiconductor substrate, a first P-well formed in the semiconductor substrate, and on which a plurality of memory cells is formed, an first N-well surrounding the first P-well and electrically separating the first P-well from the semiconductor substrate, a first... Agent: Kabushiki Kaisha Toshiba
20150023115 - Compensation scheme for non-volatile memory: Methods for performing parallel voltage and current compensation during reading and/or writing of memory cells in a memory array are described. In some embodiments, the compensation may include adjusting a bit line voltage and/or bit line reference current applied to a memory cell based on a memory array zone, a... Agent:
20150023114 - Semiconductor device and method for driving the same: One of a source and a drain of a first oxide semiconductor (OS) transistor is connected to a gate of a second OS transistor and one electrode of a first capacitor. One of a source and a drain of the second OS transistor is connected to one electrode of a... Agent:
20150023112 - Integrated circuit and data input method: An integrated circuit includes a data input such as a data pad for receiving an external data signal input and an on-die termination (ODT) information input for receiving ODT information from an external device. An ODT circuit selectively couples a termination resistor to the data pad based on the ODT... Agent: Samsung Electronics Co., Ltd.
20150023113 - Compensation scheme for non-volatile memory: Methods for performing parallel voltage and current compensation during reading and/or writing of memory cells in a memory array are described. In some embodiments, the compensation may include adjusting a bit line voltage and/or bit line reference current applied to a memory cell based on a memory array zone, a... Agent:
20150023116 - Non-volatile memory and method with peak current control: A non-volatile memory with multiple memory dice manages simultaneous operations so as to not exceed a system power capacity. A load signal bus is pulled up with a strength proportional to the system power capacity. Each die has a driver to pull down the bus by an amount corresponding to... Agent:
20150023117 - Methods for sensing memory elements in semiconductor devices: A memory device that, in certain embodiments, includes a plurality of memory elements connected to a bit-line and a delta-sigma modulator with a digital output and an analog input, which may be connected to the bit-line. In some embodiments, the delta-sigma modulator includes a circuit with first and second inputs... Agent:
20150023118 - Reconfigurable memory system data strobes: In a reconfigurable data strobe-based memory system, data strobes may be re-tasked in different modes of operation. For example, in one mode of operation a differential data strobe may be used as a timing reference for a given set of data signals. In a second mode of operation, one of... Agent:
20150023120 - Memory device and read operation method thereof: A read operation for a memory device is provided. A selected word line, first and second global bit line groups and a selected first bit line group are precharged. A first cell current flowing through the selected word line, the first and the selected first bit line groups is generated.... Agent:
20150023119 - Semiconductor device and semiconductor system having the same: A semiconductor device includes a column command generation unit suitable for generating a column command delayed by a first delay time from a source command, in response to a first control signal and the source command, a bank address generation unit suitable for generating a bank address delayed by the... Agent: Sk Hynix Inc.
20150023121 - Memory refresh methods, memory section control circuits, and apparatuses: Apparatuses, memory section control circuits, and methods of refreshing memory are disclosed. An example apparatus includes a plurality of memory sections and a plurality of memory section control circuits. Each memory section control circuit is coupled to a respective one of the plurality of memory sections and includes a plurality... Agent:
20150023122 - Method and apparatus for memory power and/or area reduction: A method and apparatus for memory power and/or area reduction. An array of memory cells may be scanned to detect faulty memory cells, if any, in the array. A supply voltage Vmem applied to the array of memory cells may be controlled based on a result of the scan, and... Agent:01/15/2015 > 36 patent applications in 24 patent subcategories.
20150016172 - Query operations for stacked-die memory device: An integrated circuit (IC) package includes a stacked-die memory device. The stacked-die memory device includes a set of one or more stacked memory dies implementing memory cell circuitry. The stacked-die memory device further includes a set of one or more logic dies electrically coupled to the memory cell circuitry. The... Agent:
20150016173 - Rom chip manufacturing structures: An integrated circuit (IC) chip embodiment includes first and second ROM cells arranged in a same row of a ROM array. The first and second ROM cells include first portions of first and second gate structures, respectively. The IC chip further includes a strap cell disposed between the first and... Agent:
20150016174 - Integrated circuits with programmable electrical connections and methods for fabricating the same: Methods and apparatus are provided for an integrated circuit with a programmable electrical connection. The apparatus includes an inactive area with a memory line passing over the inactive area. The memory line includes a programmable layer. An interlayer dielectric is positioned over the memory line and the inactive area, and... Agent:
20150016175 - Cmos analog memories utilizing ferroelectric capacitors: A memory cell and memories constructed from that memory cell are disclosed. A memory according to the present invention includes a ferroelectric capacitor, a charge source and a read circuit. The charge source receives a data value to be stored in the ferroelectric capacitor. The charge source converts the data... Agent: Radiant Technologies, Inc.
20150016178 - All around electrode for novel 3d rram applications: A resistive switching memory device can include three or more electrodes interfacing a switching layer, including a top electrode, a bottom electrode, and a side electrode. The top and bottom electrodes can be used for forming conductive filaments and for reading the memory device. The side electrode can be used... Agent: Intermolecular Inc.
20150016176 - Memory storage circuit and method of driving memory storage circuit: A memory storage circuit includes a volatile memory portion, a control portion, and a non-volatile memory portion. The volatile memory portion includes a first node and a second node to store a pair of complementary logic data. The control portion includes a first transistor and a second transistor. Gate electrodes... Agent:
20150016177 - Nonvolatile semiconductor memory device: A nonvolatile semiconductor memory device according to an embodiment comprises: a memory cell array including a plurality of memory cells provided one at each of intersections of a plurality of first lines and a plurality of second lines and each storing data by a data storing state of a filament;... Agent: Kabushiki Kaisha Toshiba
20150016180 - Memory architectures having dense layouts: Some embodiments relate to a memory cell to store one or more bits of data. The memory cell includes a capacitor including first and second capacitor plates which are separated from one another by a dielectric. The first capacitor plate corresponds to a doped region disposed in a semiconductor substrate,... Agent:
20150016179 - Memory circuit: While the supply of power is stopped, a data signal that has been held in a volatile memory section can be held in a nonvolatile memory section. In the nonvolatile memory section, a transistor having an extremely low off-state current allows a data signal to be held in the capacitor... Agent:
20150016181 - Memory device and driving method of the memory device: A memory device which can reduce power consumption and a driving method thereof are disclosed. In a memory element including an inverter and the like, a capacitor for holding data and a capacitor switching element for controlling store and release of charge in the capacitor are provided. The capacitor switching... Agent:
20150016182 - Sram memory card and voltage monitoring circuit: An SRAM memory card includes a monitoring unit that monitors, via a contact, a power supply voltage generated by a battery, set an ON value in an alarm signal when electric potential at the contact is lower than a threshold and set an OFF value in the alarm signal when... Agent: Mitsubishi Electric Corporation
20150016183 - Sense amplifier with transistor threshold compensation: One embodiment provides, in a sense amplifier for an electronic memory array in which a selected memory cell drives a developing voltage differential according to a logic state of the memory cell, a method to store the logic state. The method includes poising source voltages of first and second transistors... Agent:
20150016184 - Magnetic field sensing using magnetoresistive random access memory (mram) cells: A magnetic field sensing system includes one or more magnetoresistive random access memory (MRAM) cells, and may be configured to determine one or more of a presence, a magnitude, and a polarity of an external magnetic field incident upon an MRAM cell. In some examples, a control module of the... Agent:
20150016185 - Electro-mechanical diode non-volatile memory cell for cross-point memory arrays: A non-volatile electro-mechanical diode memory cell is described for implementation of compact (4F2) cross-point memory arrays. The electro-mechanical diode memory cells operate with relatively low set/reset voltages and excellent retention characteristics, and are multi-time programmable. Due to its simplicity, this electro-mechanical diode memory cell is attractive for implementation of three-dimensional... Agent: The Regents Of The University Of California
20150016187 - Asymmetric log-likelihood ratio for flash channel: Disclosed is a system and method for reading a flash memory cell with an adjusted read level. A current read level is set to a new read level associated with increasing a first error rate to decrease a second error rate. The first error rate is associated with determining that... Agent:
20150016186 - Methods and apparatuses for determining threshold voltage shift: Apparatuses and methods for determining threshold voltage shift are described. A number of methods for determining threshold voltage shift in memory cells include determining changes in threshold voltage for memory cells at each data state of a first number of data states by searching threshold voltage data of memory cells... Agent:
20150016188 - Method for managing the operation of a memory device having a sram memory plane and a non volatile memory plane, and corresponding memory device: A method can be used for managing the operation of a memory cell that includes an SRAM elementary memory cell and a non-volatile elementary memory cell coupled to one another. A data bit is transferred between the SRAM elementary memory cell and the non-volatile elementary memory cell. A control datum... Agent:
20150016189 - Semiconductor memory device and method of operating the same: Disclosed are a semiconductor memory device and an operating method thereof. The semiconductor memory device includes a memory cell block including a plurality of memory cells, a voltage providing unit suitable for providing a pass voltage or a read voltage to word lines coupled with the memory cells and a... Agent: Sk Hynix Inc.
20150016190 - Nonvolatile semiconductor memory device: A nonvolatile semiconductor memory device comprises multiple memory strings each including a plurality of first and second groups of serially connected memory cells, and a back gate transistor serially connected between the first and second groups of memory cells, a plurality of word lines, each word line being connected to... Agent:
20150016191 - Data storage device and flash memory control method: An overclocking process for a data storage device using a flash memory. A controller for the flash memory tests the flash memory using test clocks with various frequencies to determine at least one clock signal suitable to the flash memory. The clock candidates suitable to the flash memory are selected... Agent:
20150016192 - Method of using non-volatile memories for on-dimm memory address list storage: An integrated circuit device. The device includes an address input(s) configured to receive address information from an address stream from an address command bus coupled to a host controller and an address output(s) configured to drive address information, and is coupled to a plurality of memory (DRAM) devices provided on... Agent:
20150016193 - Circuit configuration and operating method for same: A circuit configuration is described including a first input for inputting a first set of digital input data, an output for outputting digital output data, and a control input for receiving a control signal. At least two register units are provided and the circuit configuration is designed to write, as... Agent: Robert Bosch Gmbh
20150016195 - Compensation circuit for use with input buffer and method of operating the same: A compensation circuit for use with an input buffer includes an input buffer configured to amplify an input signal and output a compensated signal. A process detector includes a replica of the input buffer. The process detector is configured to output at least one comparison signal indicating a variation in... Agent:
20150016196 - Data input circuit: A data input circuit includes a clock sampling unit, a final clock generation unit, and a write latch signal generation unit. The sampling unit is configured to generate a shifting signal including a pulse generated after a write latency is elapsed, and generate a sampling clock by sampling an internal... Agent:
20150016194 - Semiconductor memory device and memory system including the same: A semiconductor memory device and a memory system including the same are provided. The semiconductor memory device includes a first memory unit and a plurality of second memory unit, each including a plurality of memory cells and page buffers corresponding to the memory cells, and a redundancy memory unit including... Agent: Sk Hynix Inc.
20150016198 - Multiple power domain circuit and related method: A method comprises providing a trigger signal, generating an input pulse according to the trigger signal, inverting the input pulse to generate an inverted input pulse and pulling down an output voltage using the inverted input pulse, wherein the inverted pulse is applied to a transistor of a high threshold... Agent:
20150016197 - Semiconductor memory device that does not require a sense amplifier: A semiconductor memory device that does not require a sense amplifier includes a memory cell group having at least one memory cell, a buffer unit, and a bias voltage unit. The buffer unit includes a tri-state buffer that has an input terminal coupled to the memory cell group, and an... Agent:
20150016199 - Bit line equalizing circuit: There is provided a bit line equalizing circuit including: an active region; a first bit line disposed on the active region in a first direction; a second bit line disposed on the active region in the first direction; a gate pattern including a first pattern disposed on the active region... Agent: Samsung Electronics Co., Ltd.
20150016200 - Memory device for masking read data and a method of testing the same: A memory device includes a memory array, a plurality of input/output pins, a mask signal generator, an input/output block. The memory array is configured to output read data including a plurality of data bits. The mask signal generator is configured to generate at least one data mask signal. The input/output... Agent:
20150016201 - Semiconductor device: A semiconductor device includes first and second bank groups coupled to first and second data lines which are electrically isolated from each other. The semiconductor device includes a register unit suitable for providing predetermined data to the second data line in a specific mode, a data transfer and output unit... Agent: Sk Hynix Inc.
20150016202 - Memory devices, systems and methods employing command/address calibration: During a command/address calibration mode, a memory controller may transmit multiple cycles of test patterns as signals to a memory device. Each cycle of test pattern signals may be transmitted at an adjusted relative phase with respect to a clock also transmitted to the memory device. The memory device may... Agent:
20150016203 - Dram sub-array level autonomic refresh memory controller optimization: A method of refreshing a dynamic random access memory (DRAM) includes detecting an open page of the DRAM at a row of a DRAM bank within an open sub-array of the DRAM bank. The method also includes delaying issuance of a refresh command to a target refresh row of the... Agent: Qualcomm Incorporated
20150016204 - Insertion-override counter to support multiple memory refresh rates: A memory refresh method includes determining positions at which to insert refresh operations of weak rows of a memory block among regularly scheduled refresh operations of normal rows of the memory block. The refresh operations occur at a substantially constant refresh rate. The positions at which to insert are based... Agent: Qualcomm Incorporated
20150016205 - Semiconductor circuit: A semiconductor circuit includes a first input section into which a first input signal is inputted, a second input section into which a second input signal is inputted, an output generation circuit which is connected to the first and second input sections and generates an output signal based on the... Agent: Kabushiki Kaisha Toshiba
20150016206 - Apparatus and method to measure energy capacity of a backup power supply without compromising power delivery: A device includes a backup power supply configured to provide power to an external system upon loss of primary system power. The backup power provided by at least one capacitor. While the capacitor is available as a backup power supply to the external system, a transient elevation of the capacitor's... Agent:
20150016207 - Systems and methods for reducing standby power in floating body memory devices: Methods, devices, arrays and systems for reducing standby power for a floating body memory array. One method includes counting bits of data before data enters the array, wherein the counting includes counting at least one of: a total number of bits at state 1 and a total number of all... Agent:01/08/2015 > 39 patent applications in 22 patent subcategories.
20150009736 - Approximate multi-level cell memory operations: The present technology relaxes the precision (or full data-correctness-guarantees) requirements in memory operations, such as writing or reading, of MLC memories so that an application may write and read a digital data value as an approximate value. Types of MLCs include Flash MLC and MLC Phase Change Memory (PCM) as... Agent:
20150009739 - Memory devices with serially connected signals for stacked arrangements: Disclosed are various embodiments related to stacked memory devices, such as DRAMs, SRAMs, EEPROMs, and CAMs. For example, stack position identifiers (SPIDs) are assigned or otherwise determined, and are used by each memory device to make a number of adjustments. In one embodiment, a self-refresh rate of a DRAM is... Agent:
20150009738 - Pad selection in memory devices configured for stacked arrangements: Disclosed are various embodiments related to stacked memory devices, such as DRAMs, SRAMs, EEPROMs, and CAMs. For example, stack position identifiers (SPIDs) are assigned or otherwise determined, and are used by each memory device to make a number of adjustments. In one embodiment, a self-refresh rate of a DRAM is... Agent:
20150009737 - Self-refresh adjustment in memory devices configured for stacked arrangements: Disclosed are various embodiments related to stacked memory devices, such as DRAMs, SRAMs, EEPROMs, and CAMs. For example, stack position identifiers (SPIDs) are assigned or otherwise determined, and are used by each memory device to make a number of adjustments. In one embodiment, a self-refresh rate of a DRAM is... Agent:
20150009740 - Latency adjustment based on stack position identifier in memory devices configured for stacked arrangements: Disclosed are various embodiments related to stacked memory devices, such as DRAMs, SRAMs, EEPROMs, ReRAMs, and CAMs. For example, stack position identifiers (SPIDs) are assigned or otherwise determined, and are used by each memory device to make a number of adjustments. In one embodiment, a self-refresh rate of a DRAM... Agent:
20150009741 - Valid command detection based on stack position identifiers in memory devices configured for stacked arrangements: Disclosed are various embodiments related to stacked memory devices, such as DRAMs, SRAMs, EEPROMs, ReRAMs, and CAMs. For example, stack position identifiers (SPIDs) are assigned or otherwise determined, and are used by each memory device to make a number of adjustments. In one embodiment, a self-refresh rate of a DRAM... Agent:
20150009743 - Low-pin-count non-volatile memory interface for 3d ic: A low-pin-count non-volatile (NVM) memory to be provided in an integrated circuit for a 3D IC to repair defects, trim devices, or adjust parameters is presented here. At least one die in a 3D IC can be built with at least one low-pin-count OTP memory. The low-pin-count OTP memory can... Agent:
20150009742 - Semiconductor memory device having improved fuse sensing reliability in slow power-up operation and method for reading fuse block thereby: Provided is a semiconductor memory device with improved fuse sensing reliability during a slow power-up operation. The semiconductor memory device may include a memory cell array including a normal memory cell array and a spare memory cell array; an anti-fuse circuit supplied with a first voltage and configured to store... Agent: Samsung Electronics Co., Ltd.
20150009745 - High operating speed resistive random access memory: Providing for resistive random access memory (RRAM) having high read speeds is described herein. By way of example, a RRAM memory can be powered at one terminal by a bitline, and connected at another terminal to a gate of a transistor having a low gate capacitance (relative to a capacitance... Agent:
20150009744 - Non-volatile memory device: The invention concerns a memory device comprising: a first memory cell comprising a first resistive non-volatile data storage element programmable to store a first bit of data; and a second memory cell comprising a second resistive non-volatile data storage element programmable to store a second bit of data; wherein said... Agent:
20150009746 - Solid-state quantum memory based on a nuclear spin coupled to an electronic spin: A system comprising a solid state lattice containing an electronic spin coupled to a nuclear spin; an optical excitation configuration which is arranged to generate first optical radiation to excite the electronic spin to emit output optical radiation without decoupling the electronic and nuclear spins; wherein the optical excitation configuration... Agent: President And Fellows Of Harvard College
20150009748 - Data output timing control circuit for semiconductor apparatus: A data output timing control circuit for a semiconductor apparatus includes a phase adjustment unit. The phase adjustment unit is configured to shift a phase of a read command as large as a code value of the delay control code in sequential synchronization with a plurality of delayed clocks obtained... Agent:
20150009747 - Phase switchable bistable memory device, a frequency divider and a radio frequency transceiver: A phase switchable bistable memory device comprising a bistable memory component and a phase switching component is described. The bistable memory component comprises a bistable memory stage arranged to receive an input signal and a state transition stage arranged to receive a state transition signal and to cause the bistable... Agent:
20150009750 - Device including a dual port static random access memory cell and method for the formation thereof: A device includes a substrate and a dual port static random access memory cell. The substrate includes an N-well region, a first P-well region and a second P-well region. The first and second P-well regions are arranged on opposite sides of the N-well region and spaced apart along a width... Agent:
20150009749 - Memory cell array: A memory cell array includes a bit line, a complementary bit line, a first operation voltage supply circuit, a second operation voltage supply circuit, a first memory cell and a second memory cell. The first operation voltage supply circuit is electrically coupled to the bit line and the complementary bit... Agent:
20150009751 - Methods and systems to selectively boost an operating voltage of, and controls to an 8t bit-cell array and/or other logic blocks: Methods and systems to provide a multi-Vcc environment, such as to selectively boost an operating voltage of a logic block and/or provide a level-shifted control to the logic block. A multi-Vcc environment may be implemented to isolate a Vmin-limiting logic block from a single-Vcc environment, such as to reduce Vmin... Agent:
20150009752 - Phase change memory device having multi-level and method of driving the same: A phase change memory device having a multi-level and a method of driving the same are presented. The disclosed phase change memory device includes variable resistors and shifting units. The variable resistors are interchanged into set and reset states in response to an applied current. The shifting units, which are... Agent:
20150009753 - Phase change memory device having multi-level and method of driving the same: A phase change memory device having a multi-level and a method of driving the same are presented. The disclosed phase change memory device includes variable resistors and shifting units. The variable resistors are interchanged into set and reset states in response to an applied current. The shifting units, which are... Agent:
20150009754 - Partial block erase architecture for flash memory: A method and system for increasing the lifespan of a flash memory device by selectively erasing sub-blocks of a memory block. Each physical memory block of the flash memory device is dividable into at least two logical sub-blocks, where each of the at least two logical sub-blocks is erasable. Therefore,... Agent:
20150009755 - Nonvolatile semiconductor memory device: When selectively erasing one sub-block, a control circuit applies, in a first sub-block, a first voltage to bit lines and a source line, and applies a second voltage smaller than the first voltage to the word lines. Then, the control circuit applies a third voltage lower than the first voltage... Agent: Kabushiki Kaisha Toshiba
20150009757 - Array arrangement including carrier source: A source of charge carriers in thin film transistor-based memory devices is provided for a memory. The source of charge carriers can include a diode having a first and second terminal. A NAND string coupled on a first end via a first switch to a bit line, is coupled on... Agent:
20150009758 - Semiconductor memory device and method of operating the same: A semiconductor memory device and a method of operating the same are provided. The semiconductor memory device includes memory cells stacked on a substrate. The method includes applying a reference voltage to an unselected drain select line, applying a drain selection voltage to a selected drain select line, and applying... Agent: Sk Hynix Inc.
20150009756 - Sensing operations in a memory device: Methods and apparatus for sensing operations in memory devices are disclosed. In at least one embodiment, a sensing operation to determine negative threshold voltages in memory cells by an elevated source potential applied to a string of memory cells and an elevated data line potential applied to the string of... Agent: Micron Technology, Inc.
20150009759 - Substrate connection of three dimensional nand for improving erase performance: A memory includes a doped substrate well, a substrate connector coupled to the doped substrate well, and a set of interlayer connectors insulated from the doped substrate well. A series arrangement including a plurality of memory cells is coupled on a first end by a first switch to a bit... Agent: Macronix International Co., Ltd.
20150009761 - Clock mode determination in a memory system: A clock mode configuration circuit for a memory device is described. A memory system includes any number of memory devices serially connected to each other, where each memory device receives a clock signal. The clock signal can be provided either in parallel to all the memory devices or serially from... Agent:
20150009762 - Switch and semiconductor device including the switch: A device for use with non-volatile memory, includes a first transistor of a first channel type coupled between first and second nodes, including a control gate supplied with a first control signal having a first phase, a second transistor of a second channel type different from the first channel type... Agent:
20150009760 - Three-dimensional nonvolatile memory and related read method designed to reduce read disturbance: A nonvolatile memory device performs a read operation comprising first and second intervals. In the first interval the device applies a turn-on voltage to string selection lines and ground selection lines connected to the string selection transistors and the ground selection transistors, respectively. In the second interval, the device applies... Agent:
20150009763 - Semiconductor storage device: A semiconductor storage device according to the present embodiment includes a memory cell array including a plurality of memory cells. A plurality of word lines are electrically connected to control gates of the memory cells. A plurality of bit lines are electrically connected to one end of a current path... Agent: Kabushiki Kaisha Toshiba
20150009764 - Output circuit and semiconductor storage device: According to one embodiment, there is provided an output circuit including a driver transistor and a pre-driver circuit. The driver transistor is connected to an output terminal. The pre-driver circuit is configured to turn ON/OFF the driver transistor. The pre-driver circuit includes a first transistor, a second transistor, a third... Agent: Kabushiki Kaisha Toshiba
20150009767 - Programmable lsi: A low-power programmable LSI that can perform configuration (dynamic configuration) at high speed and can quickly start is provided. The programmable LSI includes a plurality of logic elements and a memory element for storing configuration data to be input to the plurality of logic elements. The plurality of logic elements... Agent:
20150009766 - Apparatuses and methods for comparing a current representative of a number of failing memory cells: Apparatuses and methods for comparing a sense current representative of a number of failing memory cells of a group of memory cells and a reference current representative of a reference number of failing memory cells is provided. One such apparatus includes a comparator configured to receive the sense current and... Agent:
20150009765 - Latency control device and semiconductor device including the same: A latency control device and a semiconductor device including the same are disclosed. The latency control device includes: a code setting unit configured to output a plurality of coding signals by setting a code value having a specific delay amount in response to a code signal; a latch unit configured... Agent: Sk Hynix Inc.
20150009769 - Dram sub-array level refresh: A memory controller coupled to a memory chip having a number of sub-arrays of memory cells is configured to determine a configuration of the memory chip. The memory controller is configured to read the sub-array configuration of the memory chip and to detect sub-array level conflicts between external commands and... Agent: Qualcomm Incorporated
20150009768 - Semiconductor device, semiconductor memory device, and method for driving the same: A semiconductor device includes a command decoder configured to decode a command and generate a composite command; a first generation block configured to generate a first control signal for performing a first operation based on the composite command; a delay control block configured to delay the composite command by a... Agent: Sk Hynix Inc.
20150009770 - Semiconductor system and method for reparing the same: Provided is a semiconductor system and method for repairing the same that may improve repair capacity of the semiconductor system. The semiconductor system comprises a semiconductor circuit configured to output a remaining repair information and perform a repair operation in response to an external command, and a host configured to... Agent: Sk Hynix Inc.
20150009771 - Sense amplifier structure for a semiconductor integrated circuit device: A semiconductor integrated circuit device includes a first signal line and a second signal line, and a sense amplifier that includes a plurality of PMOS transistors and a plurality of NMOS transistors. The sense amplifier is configured to sense amplify a potential difference between the first signal line and the... Agent:
20150009772 - Memory having power saving mode: A memory has a normal mode and a power saving mode. The memory has bitline precharge circuitry which during the normal mode selectively couples a pair of bitlines to a precharge node to charge the bitlines to a given voltage level. During the power saving mode the bitlines are isolated... Agent: Arm Limited
20150009774 - Semiconductor devices and semiconductor systems including the same: The semiconductor device includes an internal command generator and an internal address generator. The internal command generator generates first and second command latch signals from first and second internal clock signals in response to an external control signal and latches a command signal in response to the first and second... Agent: Sk Hynix Inc.
20150009773 - Volume select for affecting a state of a non-selected memory volume: Apparatuses and methods of operating memory are described. One such method can include receiving a select command at a plurality of memory volumes of a memory device, the select command indicating a targeted memory volume of the plurality of memory volumes. In response to the select command, the method can... Agent:01/01/2015 > 46 patent applications in 29 patent subcategories.
20150003137 - Nonvolatile memory device using a resistance material and a driving method thereof: A nonvolatile memory device includes a buffer memory, a read circuit configured to read first data stored in the buffer memory in a first read operation, and a write circuit configured to write second data in the buffer memory in a first write operation, wherein the first write operation is... Agent:
20150003138 - Content addressable memory system: A priority encoder and row decoder portion shares a row address register including more than one row. Each row of the row address register corresponds to each entry of a TCAM array mat and retains each address. Each row of the row address register corresponds to each word line and... Agent: Renesas Electronics Corporation
20150003139 - Clock adjusting circuit, memory storage device, and memory control circuit unit: A memory storage device, a memory control circuit unit, and a clock adjusting circuit disposed on a plurality of layers are provided. The clock adjusting circuit includes a detection circuit, a control voltage generating circuit, and a voltage-controlled oscillator (VCO). The detection circuit detects a signal characteristic difference between an... Agent: Phison Electronics Corp.
20150003140 - Semiconductor device having multiport memory: A semiconductor device enabling expansion of a noise margin. For example, in a memory area in which each memory cell MC is coupled to a word line WLA for a first port and a word line WLB for a second port, and a plurality of memory cells MC are disposed... Agent:
20150003142 - Method and structure for reliable electrical fuse programming: A method of programming electrical fuses reliably is disclosed. If a programming current exceeds a critical current, disruptive mechanisms such as rupture, thermal runaway, decomposition, or melt, can be a dominant programming mechanism such that programming is not be very reliable. Advantageously, by controlled programming where programming current is maintained... Agent:
20150003143 - One-time programmable devices using junction diode as program selector for electrical fuses with extended area: Junction diodes fabricated in standard CMOS logic processes can be used as program selectors for One-Time Programmable (OTP) devices, such as electrical fuses. At least one portion of the electrical fuse can have at least one extended area to accelerate programming. An extended area is an extension of the fuse... Agent:
20150003141 - Semiconductor memory device and repair method thereof: A semiconductor memory device is provided which includes a memory cell group and a fuse cell group including at least one fuse cell to store a failed address corresponding to a defective memory cell in the memory cell group; a spare cell group including a spare memory cell configured to... Agent: Samsung Electronics Co., Ltd.
20150003145 - Data-masked analog and digital read for resistive memories: An analog read circuit measures the resistance of each of a plurality of bits in an array of resistive memory elements. Data stored within a latch determines whether to selectively enable the analog read circuit. In an alternate embodiment, a sense amplifier is coupled to the latch and the array,... Agent:
20150003144 - Resistive random-access memory cells: Improved random-access memory cells, complementary cells, and memory devices. RRAM cells are provided for storing information in a plurality of programmable cell states. An electrically-insulating matrix is located between first and second electrodes such that an electrically-conductive path, which extends in a direction between the electrodes, can be formed within... Agent:
20150003146 - Semiconductor memory device and sense amplifier control method thereof: A semiconductor memory device is provided. A cell array includes a DRAM cell connected to one of a pair of bit lines. A bit line sense amplifier is coupled to the pair of bit lines. The bit line sense amplifier discharges a low-level bit line of the pair of bit... Agent: Samsung Electronics Co., Ltd.
20150003148 - Methods and apparatus for designing and constructing dual write memory circuits with voltage assist: Static random access memory (SRAM) circuits are used in most digital integrated circuits to store representations of data bits. To handle multiple concurrent memory requests, an efficient dual-port six transistor (6T) SRAM bit cell is proposed. The dual-port 6T SRAM cell uses independent word lines and bit lines such that... Agent: Memoir Systems, Inc.
20150003147 - Sram restore tracking circuit and method: novel and useful SRAM restore tracking circuit adapted to improve the tracking of SRAM cell behavior for different PVT corners. The SRAM array access path is mainly influenced by two stages: (1) the wordline (WL) delay and (2) the SRAM cell delay. These two stages are usually the most sensitive... Agent:
20150003149 - Mixed mode programming for phase change memory: Subject matter disclosed herein relates to a memory device, and more particularly to write performance of a phase change memory.... Agent:
20150003151 - Novel nand array architecture for multiple simutaneous program and read: This invention discloses a HiNAND array scheme with multiple-level of bit lines (BLs) including metal3 global bit lines (GBLs), divided metal2 Segment bit lines (SBLs), and divided metal1 block bit lines (BBLs) laid out in parallel to each other respectively for a plurality of NAND Strings. All other source lines... Agent:
20150003150 - Semiconductor device and operation method thereof: A semiconductor device and a method of operating the same. The semiconductor device may include a plurality of memory blocks. Each of the plurality of memory blocks may include a plurality of cell strings extending substantially perpendicular to a semiconductor substrate, the plurality of cell strings sharing a plurality of... Agent: Sk Hynix Inc.
20150003153 - Flash memory device and method for handling power failure thereof: s
20150003154 - Flash memory device and method for handling power failure thereof: A flash memory device. In one embodiment, the flash memory device includes a flash memory, a diode, a controller, and a capacitor. The flash memory has a voltage source pin. The diode is coupled between a voltage source and the voltage source pin of the flash memory. The controller is... Agent:
20150003152 - Storage device and a write method thereof: A write method of a storage device includes determining whether to perform a coarse program operation based on information about memory cells of a memory device, in response to a determination that the coarse program operation is to be performed, programming data in the memory device by performing the coarse... Agent:
20150003155 - System and method for employing secure non-volatile storage devices in gaming machines: A write-protection system and method for use with a gaming machine. The system having a non-volatile data storage device, an interface device and an electrically conductive connector. The storage device having electronic data storage and a write-protection controller providing a write-protected state and a write-permitting state, the electronic data storage... Agent:
20150003156 - Nand flash word line management: Methods for improving NAND flash memory yields by identifying memory blocks with benign word line defects are described. Memory blocks including word line defects may be classified as incomplete memory blocks and may be used for storing data fragments. A data fragment may correspond with data written into memory cells... Agent:
20150003157 - Semiconductor memory device: A semiconductor memory device includes a memory array including memory blocks stacked in a plurality of layers over a substrate and an operation circuit suitable for performing a read operation and a program loop to memory cells included in the memory blocks, wherein word lines of the memory blocks are... Agent: Sk Hynix Inc.
20150003158 - Semiconductor memory device: A semiconductor memory device includes a memory array including memory blocks stacked in a plurality of layers on a substrate, first vertical lines suitable for coupling bit lines, and second vertical lines suitable for coupling word lines of the memory blocks vertically stacked, wherein the memory blocks include selection lines... Agent: Sk Hynix Inc.
20150003159 - Method of operating nonvolatile memory device controlled by controlling coupling resistance value between bit line and page buffer: A method of operating a nonvolatile memory device includes determining whether a program operation is performed on even memory cells coupled to even bit lines of a selected page, setting a coupling resistance value between odd bit lines of the selected page and page buffers depending on whether the program... Agent: Sk Hynix Inc.
20150003160 - Three-dimensional memory comprising discrete read/write-voltage generator die: The present invention discloses a discrete three-dimensional memory (3D-M). Its 3D-M arrays are located on at least one 3D-array die, while its read/write-voltage generator (VR/VW-generator) is located on a separate peripheral-circuit die. The VR/VW-generator generates at least a read and/or write voltage to the 3D-array die. A single VR/VW-generator die... Agent: Chengdu HaicunIPTechnology LLC
20150003164 - Content addressable memory: Content addressable memory (CAM) devices provide for high density, low cost CAM devices. CAM devices include a non-volatile memory array having a plurality of NAND memory cell strings, wherein a NAND memory cell string of the non-volatile memory array comprises a plurality of CAM memory cells, and wherein the CAM... Agent: Micron Technology, Inc.
20150003162 - Detecting programmed word lines based on nand string current: A number (Nwl) of programmed word lines in a block of NAND strings is determined by measuring a reference combined current (Iref) in the block when all of the memory cells are in a conductive state. Subsequently, to determine if a word line is a programmed word line, an additional... Agent:
20150003163 - Semiconductor memory device and programming method for flash memory: A programming method for suppressing deterioration of an insulating layer in a memory cell is provided. In the programming method for a flash memory of the invention, a cell unit including programming units that have been programmed is electrically isolated from a bit line; a cell unit not including programming... Agent: Winbond Electronics Corp.
20150003161 - System for maintaining back gate threshold voltage in three dimensional nand memory: In a nonvolatile memory array in which a NAND string includes a back gate that has a charge storage element, the threshold voltage of the back gate is monitored, and if the threshold voltage deviates from a desired threshold voltage range, charge is added to, or removed from the charge... Agent: Sandisk Technologies Inc.
20150003166 - Non-volatile memory device and a method of programming such device: A non-volatile memory device has a charge pump for providing a programming current and an array of non-volatile memory cells. Each memory cell of the array is programmed by the programming current from the charge pump. The array of non-volatile memory cells is partitioned into a plurality of units, with... Agent:
20150003165 - Semiconductor memory circuit and device: Provided is a semiconductor memory circuit including an oxide semiconductor insulated gate FET enabling advanced performance without being affected by a variation in threshold voltage. A semiconductor memory circuit MC includes a first transistor element T1 composed of an insulated gate FET having a gate electrode connected to a memory... Agent:
20150003167 - Nonvolatile memory device and related programming method: A method of programming a memory cell of a nonvolatile memory device by executing a plurality of program loops comprises detecting whether a loop count or a level of a program pulse to be applied to the memory cell is within a specific range, wherein the specific range is an... Agent: Samsung Electronics Co., Ltd.
20150003168 - Non-volatile memory device with improved reading circuit: A non-volatile memory device includes a sense amplifier for comparing a conduction current of a selected one of a plurality of memory cells with a reference current. The sense amplifier includes an amplification stage having a first input terminal for receiving a first comparison voltage, a second input terminal for... Agent:
20150003169 - Nonvolatile memory device, a memory system having the same, and a read method thereof: A method of reading a nonvolatile memory device including: applying a read voltage to a selected wordline of the nonvolatile memory device; applying a read pass voltage to unselected wordlines of the nonvolatile memory device; sensing a state of a memory cell connected to the selected wordline; and applying the... Agent:
20150003170 - Nonvolatile memory device and an erase method thereof: A nonvolatile memory device includes: a plurality of cell strings disposed on a substrate, wherein at least one of the plurality of cell strings comprises a plurality of cell transistors and at least one ground select transistor stacked in a direction substantially perpendicular to the substrate, and the substrate and... Agent:
20150003171 - Semiconductor device, semiconductor system including the same and test method thereof: A semiconductor device includes a memory region suitable for providing a plurality of read data in parallel at every read operation cycle, an output path suitable for outputting the plurality of read data at a set time in response to an internal clock and one or more internal control signals... Agent: Sk Hynix Inc.
20150003172 - Memory module including buffer chip controlling refresh operation of memory devices: Provided is a memory module including a buffer chip controlling refresh operations. The buffer chip issues a hidden refresh command controlling refresh operations for the memory chips, and outputs a wait signal indicating that the memory chips are in refresh.... Agent:
20150003173 - Finfet-based boosting supply voltage circuit and method: A memory circuit includes a voltage boosting circuit for generating a voltage that exceeds a voltage supply of the voltage boosting circuit. The voltage boosting circuit includes a first transistor having a first polarity type and a second transistor having a second polarity type opposite the first transistor. The first... Agent:
20150003174 - Finfet-based boosting supply voltage circuit and method: A memory circuit includes a voltage boosting circuit for generating a voltage that exceeds a voltage supply of the voltage boosting circuit. The voltage boosting circuit includes a first transistor having a first polarity type and a second transistor having a second polarity type opposite the first transistor. The first... Agent: International Business Machines Corporation
20150003175 - Hybrid memory device: Memory devices, controllers, and electronic devices comprising memory devices are described. In one embodiment, a memory device comprises a volatile memory, a nonvolatile memory, and a controller comprising a memory buffer, and logic to transfer data between the nonvolatile memory and the volatile memory via the memory buffer in response... Agent:
20150003176 - Master/slave control voltage buffering: In some embodiments, disclosed herein are approaches for facilitating voltage controlled slaved (or replica) clock circuits such as voltage controlled delay lines (VCDLs) off of a master clock generator. In such systems, one or more control (or bias) voltages are generated to control a master clock generator such as a... Agent:
20150003177 - Semiconductor device suppressing bti deterioration: Disclosed herein is a device includes a command generation circuit that activates first and second command signals, an internal circuit that includes a plurality of transistors that are brought into a first operation state when at least one of the first and second command signals is activated, and an output... Agent:
20150003178 - Semiconductor memory device: A semiconductor device comprises a first pair of signal lines and a first control circuit. The first control circuit precharges each of the first pair of signal lines to a first voltage in response to a precharge signal, and changes the voltage level of each of the first pair of... Agent:
20150003179 - Memory and memory system including the same: A memory includes a plurality of word lines each coupled with at least one memory cell, an address storing unit that may store at least one target address corresponding to at least one of the word lines, and a control unit that may sequentially activate the plurality of word lines... Agent: Sk Hynix Inc.
20150003180 - Semiconductor device and operation method thereof: A semiconductor device includes: a plurality of memory cell blocks, a counting unit suitable for counting the number of active operations on each of the memory cell blocks, based on an active command and a row address, and a refresh control unit suitable for determining a target memory cell block... Agent: Sk Hynix Inc.
20150003181 - Power management in multi-die assemblies: An apparatus such as heterogeneous device includes at least a first die and a second die. The apparatus further includes a first inductive element, a second inductive element, and switch control circuitry. The switch control circuitry is disposed in the first die. The switch control circuitry controls current through the... Agent:
20150003182 - Memory devices and methods for high random transaction rate: A memory device can include a memory array configured to store a first plurality of bits and a second plurality of bits. The memory device may include an address port configured to receive at least a portion of a first address associated with a first command during a first clock... Agent:Previous industry: Electric power conversion systems
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