|Static information storage and retrieval patents - Monitor Patents|
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Static information storage and retrievalBelow are recently published patent applications awaiting approval from the USPTO. Recent week's RSS XML file available below.
Listing for abstract view: USPTO application #, Title, Abstract excerpt,Patent Agent. Listing format for list view: USPTO National Class full category number, title of the patent application. 02/27/2014 > 47 patent applications in 30 patent subcategories.
20140056048 - Nonvolatile semiconductor memory device: This nonvolatile semiconductor memory device comprises a memory cell array configured having a plurality of memory mats arranged therein, each of the memory mats having a memory cell disposed therein at an intersection of a first line and a second line, the memory cell including a first variable resistance element.... Agent: Kabushiki Kaisha Toshiba
20140056049 - Memory devices having data lines included in top and bottom conductive lines: Some embodiments include apparatuses and methods having a first set of conductive lines, a second set of conductive lines, and memory cells located in different levels of the apparatuses and arranged in memory cell strings. At least a portion of the first set of conductive lines is configured as a... Agent:
20140056050 - Memory cell and memory: In various embodiments, a memory cell and a memory are provided. The memory cell comprises a Static Random Access Memory (SRAM) cell including a reset-set (RS) flip-flop and a Read Only Memory (ROM) cell being connected (or coupled) to the SRAM cell to set logic states of internal latch nodes... Agent:
20140056051 - One-bit memory cell for nonvolatile memory and associated controlling method: A one-bit memory cell for a nonvolatile memory includes a bit line and a plurality of serially-connected storage units. The bit line is connected to the serially-connected storage units. Each storage unit includes a first doped region, a second doped region and a third doped region, which are formed in... Agent: Ememory Technology Inc.
20140056052 - Resistive memory device performing selective refresh and method of refreshing resistive memory device: A method of operating a resistive memory device, includes; performing a data retention time test on a resistive memory cell array of a memory chip, determining a number of bad memory blocks of the resistive memory cell array on the basis of the data retention time test, determining on the... Agent:
20140056056 - Method for reading data from nonvolatile memory element, and nonvolatile memory device: A method for reading data from a nonvolatile memory element including a first electrode, a second electrode, and a variable resistance layer which includes a local region having a higher degree of oxygen deficiency than a surrounding region, the method including: applying a third voltage pulse between the first electrode... Agent: Panasonic Corporation
20140056054 - Resistive memory device and programming method thereof: A method for programming a resistive memory device includes: programming a resistive memory; generating a verification data based on comparison result of a voltage, which is generated from a current flowing through the resistive memory, and a verification reference voltage which is higher than a read reference voltage used for... Agent:
20140056053 - Unipolar memory devices: Electronic apparatus, systems, and methods can include a resistive memory cell having a dielectric structured as an operably variable resistance region between an oxygen source and an oxygen sink. The dielectric, oxygen source, and an oxygen sink can be structured as a field driven unipolar memory element with respect to... Agent:
20140056055 - Variable resistance nonvolatile memory device, and accessing method for variable resistance nonvolatile memory device: A variable resistance nonvolatile memory device includes: bit lines in layers; word lines in layers formed at intervals between the layers of the bit lines; a memory cell array including basic array planes and having memory cells formed at crosspoints of the bit lines in the layers and the word... Agent: Panasonic Corporation
20140056057 - Semiconductor memory device and method for controlling semiconductor memory device: A semiconductor memory device includes word lines, bit line pairs intersecting the word lines, and memory cells arranged where the word lines and the bit line pairs intersect. A word line driver arranged in correspondence with one of the word lines outputs a first voltage or a second voltage. A... Agent: Fujitsu Semiconductor Limited
20140056058 - Differential sensing method and system for stt mram: The invention relates to methods and systems for reading a memory cell and in particular, an STT MRAM. In accordance with one aspect of the invention, a system for reading a memory cell includes a read path and a precharge path. The reference current is provided through the read path... Agent: Infineon Technologies Ag
20140056060 - Method and system for providing a magnetic tunneling junction using spin-orbit interaction based switching and memories utilizing the magnetic tunneling junction: A magnetic memory is described. The magnetic memory includes magnetic junctions and at least one spin-orbit interaction (SO) active layer. Each of the magnetic junctions includes a data storage layer that is magnetic. The SO active layer(s) are adjacent to the data storage layer of the magnetic junction. The at... Agent:
20140056061 - Method and system for providing dual magnetic tunneling junctions using spin-orbit interaction-based switching and memories utilizing the dual magnetic tunneling junctions: A magnetic memory is described. The magnetic memory includes dual magnetic junctions and spin-orbit interaction (SO) active layer(s). Each dual magnetic junction includes first and second reference layers, first and second nonmagnetic spacer layers and a free layer. The free layer is magnetic and between the nonmagnetic spacer layers. The... Agent:
20140056059 - Symmetrical differential sensing method and system for stt mram: The invention relates to methods and systems for reading a memory cell and in particular, an STT MRAM. In one example, a system for reading a memory cell includes a sense path and an inverse path. A reference current is provided through the sense path and is sampled via a... Agent: Infineon Technologies Ag
20140056062 - Semiconductor storage apparatus or semiconductor memory module: A semiconductor storage apparatus provides a large capacity phase-change memory possessing high speed operation, low electrical current, and high-reliability. During the period that a read-out start signal is activated in the memory region control circuit and the block of pairs of sense-latch and write driver is performing the verify read... Agent: Hitachi, Ltd.
20140056063 - Semiconductor device having current change memory cell: A method includes performing a read operation on a memory cell of a device including a sensing line, a bit line coupled to the memory cell, a first transistor having a source-drain path coupled between the sensing line and the bit line, and a second transistor having a gate coupled... Agent: Elpida Memory, Inc.
20140056064 - Memory system and operating method thereof: Provided are a memory system and an operating method thereof. The operating method reads an observation memory cell at least one time with different read voltages to configure a first read data symbol, reads a plurality of interference memory cells adjacent to the observation memory cell at least one time... Agent: Samsung Electronics Co., Ltd.
20140056065 - Reducing weak-erase type read disturb in 3d non-volatile memory: A read process for a 3D stacked memory device provides an optimum level of channel boosting for unselected memory strings, to repress both normal and weak-erase types of read disturbs. The channel is boosted by controlling of voltages of bit lines (Vb1), drain-side select gates (Vsgd_unsel), source-side select gates (Vsgs_unsel),... Agent: Sandisk Technologies Inc.
20140056068 - Configuring storage cells: Apparatuses, systems, methods, and computer program products are disclosed for configuring storage cells. A method includes determining a usage history for a set of storage cells of a solid-state storage medium. A method includes adjusting a voltage threshold for a set of storage cells by an amount based at least... Agent: Fusion-io, Inc.
20140056066 - Read threshold estimation in analog memory cells using simultaneous multi-voltage sense: A method includes dividing a group of analog memory cells into multiple subsets. The memory cells in the group are sensed simultaneously by performing a single sense operation, while applying to the subsets of the memory cells respective different sets of read thresholds, so as to produce respective readout results.... Agent:
20140056067 - Threshold optimization for flash memory: Described embodiments provide enhanced read accuracy of a multi-level cell (MLC) flash memory. A read request for desired cells is received by a media controller of the memory. The media controller sets m thresholds to initial values, each threshold corresponding to a cell voltage level of the memory, and measures... Agent: Lsi Corporation
20140056069 - Nonvolatile memory device having near/far memory cell groupings and data processing method: A nonvolatile memory device includes; a memory cell array designating a first memory cell group including first memory cells connected with a word line and disposed less than a reference distance from a word line voltage source in a word line direction, and a second memory cell group including second... Agent:
20140056072 - 3d memory array with read bit line shielding: A memory device includes a block of memory cells having a plurality of levels. Each level includes strips of memory cells extending in a first direction between first and second ends of the block. A first bit line structure, at each level at the first end, is coupled to a... Agent: Macronix International Co., Ltd.
20140056070 - Apparatuses and methods involving accessing distributed sub-blocks of memory cells: Apparatuses and methods involving accessing distributed sub-blocks of memory cells are described. In one such method, distributed sub-blocks of memory cells in a memory array are enabled to be accessed at the same time. Additional embodiments are described.... Agent:
20140056071 - Semiconductor device: A semiconductor device includes a first memory block configured to include first active areas extended parallel in a first direction, a second memory block adjacent to the first memory block and configured to include second active areas extended parallel in the first direction, the second active areas being staggered from... Agent: Sk Hynix Inc.
20140056074 - Nonvolatile memory device and method for driving the same: A nonvolatile memory includes a memory cell array including a plurality of nonvolatile memory cells connected to bit lines and word lines crossing the bit lines, a voltage driver configured to provide a word line voltage to the word lines and provide a first voltage during a precharging operation and... Agent:
20140056073 - Nonvolatile memory device and nonvolatile memory system including the same: A nonvolatile memory device includes a cell array including a plurality of pages, a selection unit configured to select one of the pages in response to a page selection address, an operation control unit configured to read data of a given number of pages adjacent to the selected page and... Agent: Sk Hynix Inc.
20140056075 - Semiconductor memory device and method of operating the same: A semiconductor memory device and a method of operating the same are disclosed. The semiconductor memory device includes a memory cell array configured to include memory cells, a peripheral circuit configured to perform an erase operation and a soft program operation and a control circuit configured to control the peripheral... Agent: Sk Hynix Inc.
20140056076 - Very dense nonvolatile memory bitcell: An asymmetric non-volatile memory bitcell is described. The bitcell comprises source and drain regions comprising carriers of the same conductivity type. A floating gate rests on top of the well, and extends over a channel region, and at least a portion of the source and drain regions. The drain region... Agent: Synopsys, Inc.
20140056077 - Compensating for off-current in a memory: A memory cell is accessed by determining an off-current of a set of memory cells, accessing a memory cell of the set of memory cells during an access period, and compensating for the off-current of the set of memory cells.... Agent:
20140056078 - Method of programming non-volatile memory device and apparatuses for performing the method: A non-volatile memory device is provided. The non-volatile memory device includes a cell string including a plurality of non-volatile memory cells; and an operation control block configured to supply a program voltage to a word line connected to a selected non-volatile memory cell among the plurality of non-volatile memory cells... Agent: Samsung Electronics Co., Ltd.
20140056079 - Method and system for switchable erase or write operations in nonvolatile memory: Embodiments relate to systems and methods including a step of switching between two or more erase operations and/or two or more write operations for erasing of and/or writing to least one memory cell of a nonvolatile memory enabling to select a most suitable erase and/or write operation for a particular... Agent: Infineon Technologies Ag
20140056080 - Non-volatile memory device, method of operating the same and method of fabricating the same: A non-volatile memory device includes a semiconductor substrate having active regions formed of a p-type semiconductor, first and second vertical strings disposed on the active regions, channels extending vertical to the semiconductor substrate, and a plurality of memory cells stacked along the channels, wherein the active regions are directly connected... Agent: Sk Hynix Inc.
20140056081 - Semiconductor memory device and method of operating the same: A semiconductor memory device may include a cell string configured to include memory cells, a page buffer coupled to the cell string through a bit line, and configured to include a latch for storing data to be programmed in a memory cell or data read from the memory cell, a... Agent: Sk Hynix Inc.
20140056082 - Semiconductor devices including redundancy cells: Semiconductor devices including redundancy cells are provided. The semiconductor device includes a control signal generator and a comparator. The control signal generator generates a first control signal including a pulse generated in synchronization with a point of time that a row address enable signal is disabled, a second control signal... Agent: Sk Hynix Inc.
20140056083 - Semiconductor memory device: A semiconductor memory device is disclosed. The semiconductor memory device includes a current mirror configured to include a current mirror section for current of a first line to a second line and transistors coupled in parallel, a detector configured to control a voltage of the first line based on voltages... Agent: Sk Hynix Inc.
20140056084 - Integrated circuit and memory device: An integrated circuit includes a plurality of internal circuits, an e-fuse array circuit configured to store a data used by the internal circuits, and a fuse circuit configured to store a trimming data to set the e-fuse array circuit.... Agent:
20140056085 - Semiconductor chips and semiconductor systems including the same: Semiconductor chips are provided. The semiconductor chip includes a selection phase clock generator and a data input/output portion. The selection phase clock generator is configured to receive an external clock signal and an inversed external clock signal to generate phase clock signals, configured to receive a first external test clock... Agent: Sk Hynix Inc.
20140056086 - Semiconductor memory device, method of adjusting the same and information processing system including the same: A semiconductor device includes an interface chip including: an internal data terminal, and a timing data storage circuit configured to output a plurality of timing set signals, and a plurality of core chips stacked with one another, each of the core chips including a plurality of memory cells, an output... Agent: Elpida Memory, Inc.
20140056087 - Data input circuits: Data input circuits are provided. The data input circuit includes a drive clock signal generator, a data transmitter and a write driver. The drive clock signal generator is configured to shift and delay a final clock signal generated in response to a pulse of a sampled clock signal and configured... Agent: Sk Hynix Inc.
20140056088 - Method of identifying damaged bitline address in non-volatile memory device: A method of identifying a damaged bitline address in a non-volatile memory device is introduced. The non-volatile memory device includes a memory cell array and a plurality of bit lines crossing the memory cell array. Each bit line has a first end and a second end. The bit lines are... Agent: Eon Silicon Solution, Inc.
20140056089 - Sense amplifiers, memories, and apparatuses and methods for sensing a data state of a memory cell: Sense amplifiers, memories, and apparatuses and methods for sensing a data state of a memory cell are disclosed. An example apparatus includes a differential amplifier configured to amplify a voltage difference between voltages applied to first and second amplifier input nodes to provide an output. The example apparatus further includes... Agent: Micron Technology, Inc.
20140056090 - Techniques for reducing disturbance in a semiconductor memory device: Techniques for reducing disturbance in a semiconductor memory device are disclosed. In one particular exemplary embodiment, the techniques may be realized as a semiconductor memory device having reduced disturbance. The semiconductor memory device may comprise a plurality of memory cells arranged in arrays of rows and columns. The semiconductor memory... Agent: Micron Technology, Inc.
20140056091 - Semiconductor memory device and method of operating the same: A method of operating a semiconductor memory device, given the case where memory cells have an erase state less than a first reference voltage and a plurality of program states greater than the first reference voltage, includes performing an erase operation so that the memory cells have a soft erase... Agent: Sk Hynix Inc.
20140056092 - Semiconductor memory device and method of operating the same: A semiconductor memory device, comprising a memory cell block configured to include word lines disposed between a drain select line and a source select line, a voltage generation circuit configured to generate a compensation voltage when an erase operation is performed, and a row decoder configured to apply the compensation... Agent: Sk Hynix Inc.
20140056093 - Access methods and circuits for memory devices having multiple banks: A method can include storing bank addresses, if received, on at least rising and falling edges of a same clock cycle; and if addresses stored on the rising and falling edges of the same clock cycle correspond to different banks of a memory device, starting accesses to both banks after... Agent: Cypress Semiconductor Corporation
20140056094 - Word-line activation circuit, semiconductor memory device, and semiconductor integrated circuit: In a state where a signal (IN) is at “H” and an NMOS transistor (403) is on, when a signal (PCLK) changes to “H” and a PMOS transistor (401) turns off, an output node (N1) becomes coupled to a word-line activation signal (WACTCLK) via the NMOS transistor (403). When the... Agent: Panasonic Corporation02/20/2014 > 40 patent applications in 30 patent subcategories.
20140050002 - Ternary content addressable memory (tcam) storage system: A system for ternary content addressable memory (TCAM) storage may include a TCAM having multiple entries and a processor that is communicatively coupled to the TCAM. The processor may be operative to receive a first numerical range and determine a first ternary representation of a second numerical range that encompasses... Agent: Broadcom Corporation
20140050003 - Variable resistance nonvolatile memory device and driving method of variable resistance nonvolatile memory device: A stable operation is implemented by reducing an abnormal current. A variable resistance nonvolatile memory device includes: a memory cell array having memory cells each including a variable resistance element and a current steering element that are connected in series, each of the memory cells being located at a three-dimensional... Agent:
20140050004 - Semiconductor device having hierarchically structured bit lines: Disclosed herein is a device includes first and second memory mats. The first memory mat includes first and defective memory cells and first local bit lines coupled to a first global bit line. Each of the first local bit lines is coupled to associated ones of the first memory cells,... Agent: Elpida Memory, Inc.
20140050005 - Nonvolatile memory apparatus and method of operating the same: Nonvolatile memory apparatuses and methods of operating the same. A nonvolatile memory apparatus includes a nonvolatile memory cell array including a plurality of memory cells; an address decoder configured to receive computation data that indicates a computation from among a plurality of computations and an input data for computation, and... Agent: Samsung Electronics Co., Ltd.
20140050006 - Diode-less array for one-time programmable memory: A one-time programmable memory array includes a first row conductor extending in a first row direction and disposed at a first elevation, a second row conductor extending in a second row direction and disposed at a second elevation and a column conductor extending in a column direction and disposed adjacent... Agent: Macronix International Co., Ltd.
20140050007 - Finfet based one-time programmable device: According to one embodiment, a one-time programmable (OTP) device comprises a memory FinFET in parallel with a sensing FinFET. The memory FinFET and the sensing FinFET share a common source region, a common drain region, and a common channel region. The memory FinFET is programmed by having a ruptured gate... Agent: Broadcom Corporation
20140050008 - Electronic device and method for fram power supply management: The invention is an electronic device including a ferroelectric random access memory (FRAM), a first supply voltage domain, a second supply voltage domain and a low drop output voltage regulator (LDO) receive a first supply voltage of the first supply voltage domain and providing a second supply voltage of the... Agent: Texas Instruments Incorporated
20140050014 - Driving method of variable resistance element and non-volatile memory device: A method of driving a variable resistance element comprises: before a first write step is performed, applying an initial voltage pulse of a first polarity to change a resistance value of a metal oxide layer from a resistance value corresponding to an initial state of the metal oxide layer to... Agent: Panasonic Corporation
20140050009 - Multi-port magnetic random access memory (mram): A memory array is organized into rows and columns of resistive elements and is disclosed to include a resistive element to be read or to be written thereto. Further, a first access transistor is coupled to the resistive element and to a first source line and a second access transistor... Agent: Avalanche Technology, Inc.
20140050013 - Nonvolatile memory element and nonvolatile memory device: A nonvolatile memory element includes: a first electrode; a second electrode; and a variable resistance layer comprising a metal oxide positioned between the first electrode and the second electrode. The variable resistance layer includes: a first oxide layer having a resistivity ρx, on the first electrode; a second oxide layer... Agent: Panasonic Corporation
20140050015 - Nonvolatile storage device and method for writing into the same: The nonvolatile storage device includes a variable resistance element and a write circuit which writes data into the variable resistance element, wherein the variable resistance element has a property of changing from a first resistance state to a second resistance state when a pulse of a first voltage is applied... Agent: Panasonic Corporation
20140050012 - Programmable volatile/non-volatile memory cell: The invention concerns a memory device comprising at least one memory cell comprising: a first transistor (102) coupled between a first storage node (106) and a first supply line (GND, VDD); a second transistor (104) coupled between a second storage node and said first supply line (GND, VDD), control terminals... Agent: Centre National De La Recherche Scientifique
20140050010 - Semiconductor memory device and file memory system: According to an embodiment, a semiconductor memory device has: a memory cell array formed by stacking through insulation layers a plurality of memory mats which each have a plurality of first lines, a plurality of second lines and a plurality of resistance varying memory cells provided at intersection portions of... Agent: Kabushiki Kaisha Toshiba
20140050011 - Storage unit and driving method: There is provided a storage unit including: a storage device configured to store a resistance state, the resistance state being changeable between a first state and a second state; and a driving section, when setting the resistance state to the first state, applying a first pulse having a first polarity... Agent: Sony Corporation
20140050016 - Semiconductor memory devices: Semiconductor memory devices are described. The semiconductor memory device includes a cell capacitor having a first terminal electrically connected to a storage node and a second terminal electrically connected to an internal node, an internal voltage generator configured to generate an internal voltage signal applied to the internal node in... Agent: Sk Hynix Inc.
20140050017 - Device comprising a plurality of static random access memory cells and method of operation thereof: A method comprises writing data to one or more static random access memory (SRAM) cells. Writing data to the one or more SRAM cells comprises applying a first data signal to at least one bit line electrically connected to the one or more SRAM memory cells, electrically disconnecting at least... Agent: Globalfoundries Inc.
20140050018 - Semiconductor memory device: According to one embodiment, a semiconductor memory device includes a memory cell provided with a pair of storage nodes which store data in a complementary manner, a pair of bit lines that are driven in a complementary manner based on data written to the memory cell, a word line that... Agent: Kabushiki Kaisha Toshiba
20140050020 - Architecture of magneto-resistive memory device: Provided is a semiconductor memory device including a column decoder, a plurality of sub-cell blocks, and a bit line selection circuit. The column decoder is configured to decode column addresses and drive column selection signals. Each of the sub-cell blocks includes a plurality of bit lines, a plurality of word... Agent:
20140050019 - Multi-level memory cell using multiple magnetic tunnel junctions with varying mgo thickness: A Multi-Level Memory Cell (MLC) using multiple Magnetic Tunnel Junction (MTJ) structures having one or more layers with varying thickness is disclosed. The multiple MTJ structures, which are vertically stacked and arranged in series, may have substantially identical area dimensions to minimize fabrication costs because one mask can be used... Agent: Qualcomm Incorporated
20140050021 - Semiconductor apparatus: A semiconductor apparatus includes: a first bank group comprising a plurality of first banks; a second bank group comprising a plurality of second banks arranged adjacent to the first bank group; a write operation controller arranged between the first and second bank groups so as to be adjacent to the... Agent: Sk Hynix Inc.
20140050022 - Thyristor memory cell integrated circuit: A semiconductor memory device including an array of memory cells (MC) formed on a substrate each realized from a load element and thyristor that define a switchable current path whose state represents a volatile bit value stored by the MC. At least one word line corresponding to a respective row... Agent:
20140050024 - Data reading method, and circuit, rewritable non-volatile memory module and memory storage apparatus using the same: A data reading method for a rewritable non-volatile memory module, a memory controller using the method, and a memory storage apparatus using the method are provided. The method includes applying a bias for reading data to a target word line electrically connected to a target memory cell and applying a... Agent: Phison Electronics Corp.
20140050023 - Memory device having collaborative filtering to reduce noise: An apparatus is described that is configured to modify a signal to at least substantially remove a noise portion from the signal. In one or more implementations, the apparatus is a collaborative filtering module that is configured to communicatively couple to a memory array having a plurality of memory cell... Agent: Lsi Corporation
20140050025 - Low-voltage fast-write pmos nvsram cell: This invention discloses a low-voltage fast-write 12T or 14T PMOS NVSRAM cell structure which comprises a 6T LV SRAM cell and one pairs of two 3T or 4T HV PMOS Flash strings. Due to reverse threshold voltage definition of PMOS and NMOS flash cell, this PMOS NVSRAM cell has the... Agent: Aplus Flash Technology, Inc
20140050026 - Method of executing wear leveling in a flash memory device according to ambient temperature information and related flash memory device: A method of executing wear leveling in a flash memory device includes determining whether a current temperature is in a normal operating temperature range of the flash memory device, and reprogramming data associated with data blocks to another location in a flash memory array when the current temperature is in... Agent:
20140050027 - Nonvolatile semiconductor memory device: A nonvolatile semiconductor memory device includes a control circuit configured to control a soft program operation of setting nonvolatile memory cells to a first threshold voltage distribution state of the nonvolatile memory cells. When a characteristic of the nonvolatile memory cells is in a first state, the control circuit executes... Agent: Kabushiki Kaisha Toshiba
20140050028 - Semiconductor storage device: A memory includes memory cells and a sense amplifier including a sense node that transmits a voltage according to a current flowing in one of the memory cells and detects logic of data based on the voltage of the sense node. A write sequence of writing data in a selected... Agent: Kabushiki Kaisha Toshiba
20140050030 - Methods and apparatuses including a variable termination impedance ratio: Methods of changing a centerline voltage of a data signal are described, along with apparatuses to change the centerline voltage. In one such method, portions of a termination circuit coupled to an output pin are selectively activated to change an impedance of the termination circuit to change the centerline voltage... Agent: Micron Technology, Inc.
20140050029 - Split-gate memory cells having select-gate sidewall metal silicide regions and related manufacturing methods: Split-gate non-volatile memory (NVM) cells having select-gate sidewall metal silicide regions are disclosed along with related manufacturing methods. Spacer etch processing steps are used to expose sidewall portions of select gates. Metal silicide regions are then formed within these sidewall portions of the select gates. Further, metal silicide regions can... Agent:
20140050031 - Semiconductor memory device capable of reducing read time: According to one embodiment, a semiconductor memory device includes a semiconductor substrate of a first conductivity type, a first well region of a second conductivity type, a second well region of the first conductivity type, a memory string, a bit line, a source line and a first transistor. The bit... Agent:
20140050032 - Semiconductor memory device: A semiconductor memory device according to one embodiment of the present invention includes a dielectric film configured to store information depending on presence or absence of a conductive path therein, and a plurality of electrodes provided to contact a first surface of the dielectric film. The conductive path can be... Agent: Kabushiki Kaisha Toshiba
20140050036 - Graphene-based non-volatile memory: Embodiments relate to a method for representing data in a graphene-based memory device. The method includes applying a first voltage to a back gate of a graphene-based memory device and a second voltage to a first graphene layer of the graphene-based memory device. The graphene-based memory device includes the first... Agent: International Business Machines Corporation
20140050033 - Memory cell assembly including an avoid disturb cell: A memory array assembly and a method for performing a write operation without disturbing data stored in other SRAM cells are provided. The memory array assembly comprises a plurality of SRAM cells, a plurality of avoid-disturb cells, a plurality of sense amplifiers and a plurality of write drivers. The SRAM... Agent: Globalfoundries Inc.
20140050034 - Cas latency setting circuit and semiconductor memory apparatus including the same: A semiconductor memory apparatus includes a CAS latency setting circuit configured to change an initially-set CAS latency value in response to control signal pulses which are sequentially applied, during a test mode without changing settings of a mode register set during each test.... Agent: Sk Hynix Inc.
20140050035 - Semiconductor memory device and method of testing the same: A semiconductor memory device includes a write controller configured to transmit a first input data that is supplied through a first pad, to a first global I/O line and a second global I/O line when a write operation is executed in a test mode. The semiconductor memory device further includes... Agent: Sk Hynix Inc.
20140050037 - Semiconductor memory device: A semiconductor memory device includes, in part, a first data I/O block and a second data I/O block. During a write operation, the first data I/O block transmits input data supplied through a first pad to a first global I/O line, and further generates a write internal signal. The second... Agent: Sk Hynix Inc.
20140050038 - Memory device with bi-directional tracking of timing constraints: A memory device includes a DRAM, a first bi-directional tracking circuit and a second bi-directional tracking circuit. The DRAM includes a cell, a word line and a bit line. The first bi-directional tracking circuit is configured to track a first timing constraint associated with turning on or turning off the... Agent: Etron Technology, Inc.
20140050039 - Semiconductor memory devices: A semiconductor memory device includes a memory bank having a first cell block including a plurality of memory cells coupled to a first word line which can be activated in response to a row address signal, a second cell block including a plurality of memory cells coupled to a second... Agent: Sk Hynix Inc.
20140050040 - Bit line sense amplifier and layout method therefor: A bit line sense amplifier and a layout method therefor which can reduce coupling capacitance. The bit line sense amplifier is disposed between a first memory cell block and a second memory cell block adjacent to the first memory cell block and configured to include first and third switching elements... Agent: Sk Hynix Inc.
20140050041 - Data storage device and control method for non-volatile memory: A data storage device having a non-volatile memory and a controller and a control method for the non-volatile memory are disclosed. The non-volatile memory has a plurality of blocks for data storage and each block provides a plurality of sectors. The controller allocates erase marker bits in each of the... Agent: Winbond Electronics Corp.02/13/2014 > 47 patent applications in 28 patent subcategories.
20140043883 - Three dimensional structure memory: A Three-Dimensional Structure (3DS) Memory allows for physical separation of the memory circuits and the control logic circuit onto different layers such that each layer may be separately optimized. One control logic circuit suffices for several memory circuits, reducing cost. Fabrication of 3DS memory involves thinning of the memory circuit... Agent:
20140043884 - Semiconductor apparatus: A semiconductor apparatus includes a memory chip which includes: a memory area; a data input/output block configured to communicate with the memory area; and a data transmission/reception block configured to connect one of a plurality of channels and a pad to the data input/output block, wherein the plurality of channels... Agent: Sk Hynix Inc.
20140043885 - Semiconductor device: In a semiconductor device of a stacked structure type having a control chip and a plurality of controlled chips, wherein the control chip allocates different I/O sets to the respective controlled chips and processes the I/O sets within the same access cycle, the controlled chip close to the control chip... Agent: Elpida Memory, Inc.
20140043886 - Sensing memory element logic states from bit line discharge rate that varies with resistance: A digital memory element has a sense circuit latch to read the value stored in a bit cell. Before addressing a word line, the bit lines are precharged. During the read operation, a bit line is coupled to a supply voltage through a bit cell memory element that has different... Agent: Taiwan Semiconductor Manufacturing Co., Ltd.
20140043887 - Write driver circuit, semiconductor apparatus using the same, and memory system: A write driver circuit includes a write control unit and a write driver. The write control unit is configured to generate a write control current according to data to be stored. The write driver is configured to generate a write current for writing the data into a memory cell, in... Agent: Sk Hynix Inc.
20140043888 - Method of operating psram and related memory device: The latency of a PSRAM is set according to its current state when receiving an external command. If the PSRAM is not executing a specific operation or has completed the specific operation while meeting corresponding timing parameters, the PSRAM is configured to execute the external command with a first latency.... Agent: Etron Technology, Inc.
20140043889 - Time processing method and circuit for synchronous sram: A timing processing method and a circuit for a synchronous SRAM are provided. The method includes: directly inputting an address signal to a wordline decoder for logic decoding; generating various signals by setting various devices in terms of timing; and performing sensitive amplification on data that is input by a... Agent: Huawei Technologies Co., Ltd.
20140043890 - Monolithic multi-channel adaptable stt-mram: A monolithic multi-channel resistive memory includes at least one first bank associated with a first channel and tuned according to first device attributes and/or first circuit attributes. The memory also includes at least one second bank associated with a second channel and tuned according to second device attributes and/or second... Agent: Qualcomm Incorporated
20140043891 - Nonvolatile corruption resistent magnetic memory and method thereof: A method and system for storing information in a nonvolatile memory comprising: a substrate comprising magnetic material operatively associated therewith, the magnetic material having at least one first portion of low permeability and at least one second portion of high permeability; a reader comprising a sensor for reading information by... Agent: U.s. Army Research Laboratory Attn: Rdrl-loc-i
20140043892 - Semiconductor memory device having variable resistance memory and operating method: A semiconductor memory device includes a memory cell array of nonvolatile memory cells having a variable resistance element, and a conductor line array capable of generating a compensation magnetic field for the nonvolatile memory cells. A current driver selectively supplies current to conductive lines, a magnetic field sensor senses an... Agent:
20140043894 - Memory cells having a plurality of resistance variable materials: Resistance variable memory cells having a plurality of resistance variable materials and methods of operating and forming the same are described herein. As an example, a resistance variable memory cell can include a plurality of resistance variable materials located between a plug material and an electrode material. The resistance variable... Agent: Micron Technology, Inc.
20140043893 - Methods, devices and processes for multi-state phase change devices: Devices include multiple phase change materials connected in parallel between electrodes. Memory cells with multiple parallel phase change materials can be programmed to transition among more than two states representing multiple bits of information. Methods for manufacture and use are also disclosed... Agent: Micron Technology, Inc.
20140043895 - Device consisting of various thin films and use of such a device: A device comprising: an assembly consisting of two, respectively upper and lower thin layers each forming a ferromagnetic element and separated by a thin layer forming a non magnetic element, said assembly being made up so that the layers forming the ferromagnetic elements are magnetically coupled through the layer forming... Agent: Thales
20140043896 - Method of preventing program-disturbances for a non-volatile semiconductor memory device: A method of preventing program-disturbances for a non-volatile semiconductor memory device having a plurality of memory cells of which each includes a selection transistor and a memory transistor coupled in series between a bit-line and a common source-line is provided. First non-selected memory cells that share a first selection-line with... Agent:
20140043897 - Aggregating data latches for program level determination: In a nonvolatile memory array that stores randomized data, the program level—the number of states per cell stored in a population of memory cells—may be determined from the aggregated results of a single read step. A circuit for aggregating binary results of a read step includes parallel transistors with control... Agent:
20140043898 - Common line current for program level determination in flash memory: In a nonvolatile memory array that stores randomized data, the program level—the number of states per cell stored in a population of memory cells—is determined from the total current passing through the population of memory cells under read conditions, as observed on a common line, for example a source line... Agent:
20140043903 - Memory device having variable read voltage and related methods of operation: A method of determining a read voltage of a memory device comprises performing a plurality of read operations with respective different read voltages on a first group of storage regions of the memory device using a first error correction rate, wherein the plurality of read operations are performed to distinguish... Agent: Samsung Electronics Co., Ltd.
20140043904 - Memory system comprising nonvolatile memory device and related method of operation: A memory system performs a first sensing operation to sense whether multi-level cells assume an on-cell state or an off-cell state in response to a first read voltage applied to a selected word line. It then supplies a pre-charge voltage to bit lines corresponding to multi-level cells that have been... Agent:
20140043899 - Mosfet having memory characteristics: A method for performing a programming operation to a first memory bit and a second memory bit of a device is described. The method includes applying a pulse train voltage to a metal gate of the device and grounding a substrate of the device. By floating/grounding a drain of the... Agent: Taiwan Semiconductor Manufacturing Company, Ltd., ("tsmc")
20140043901 - Nonvolatile memory device and operating method with variable memory cell state definitions: A method operating a nonvolatile memory device includes successively programming a memory cell without physically erasing the memory cell. Each successive programming of the memory cell uses a different erase state region to indicate an erase state for the memory cell.... Agent:
20140043902 - Semiconductor storage device: According to one embodiment, a storage unit with multiple memory cells that store data, and a bit-line switch circuit. The bit-line switch circuit is connected to a word line that is connected to the bit line, the source line, and the control gate of the memory cell, which is connected... Agent: Kabushiki Kaisha Toshiba
20140043900 - Storage device and control method of nonvolatile memory: According to one embodiment, a storage device includes a nonvolatile memory including physical sectors each of which comprises memory cells commonly connected to a word line, each of the memory cells being capable of storing data of not less than 2 bits, each of the physical sectors including pages corresponding... Agent:
20140043907 - Nonvolatile memory device and method for voltage trimming thereof: A non-volatile semiconductor storage device includes memory blocks that each includes multiple memory strings. A bit line connects to an end of each string in the memory blocks and to a sense amplifier circuit which includes a first transistor. The device includes first and second discharge transistors for discharging the... Agent: Kabushiki Kaisha Toshiba
20140043905 - Semiconductor memory device and method of manufacturing the same: A semiconductor memory device includes a memory cell block formed over a first memory cell region and a second memory cell region defined on a semiconductor substrate, and a voltage supply circuit configured to apply an operating voltage to gate lines of a plurality of memory cells included in the... Agent:
20140043906 - Semiconductor memory devices: A flash memory capable of writing or deleting a split block is provided. A flash memory includes a memory array comprising a plurality of blocks, and a word line selection circuit, wherein each of the plurality of blocks is formed by a plurality of cell units in a well. The... Agent: Winbond Electronics Corp.
20140043908 - Semiconductor memory device and methods of operating the same: A semiconductor memory device comprises a memory cell array including a plurality of memory blocks each including a plurality of pages, wherein each of the plurality of pages includes at least one flag cell indicating whether data is in a corresponding page, and a peripheral circuit configured to read data... Agent: Sk Hynix Inc.
20140043909 - Writing method of nonvolatile semiconductor memory device: According to one embodiment, there is provided a writing method. The method includes setting potentials of a plurality of word lines to a first potential. The first potential is a potential to allow memory cells corresponding to a selective bit line to be in on state. The method also includes... Agent: Kabushiki Kaisha Toshiba
20140043911 - Method for non-volatile memory having 3d array of read/write elements with efficient decoding of vertical bit lines and word lines: A three-dimensional array of memory elements is formed across multiple layers of planes positioned at different distances above a semiconductor substrate. The memory elements reversibly change a level of electrical conductance in response to a voltage difference being applied across them. The three-dimensional array includes a two-dimensional array of pillar... Agent: Sandisk 3d LLC
20140043910 - Semiconductor memory device and operating method thereof: A semiconductor memory device and a method of operating same includes reading a number of program/erase operations stored in a program/erase number storage unit, setting a pulse width of a program voltage based on the read number of program/erase operations, and performing a program operation on memory cells using the... Agent: Sk Hynix Inc.
20140043912 - Method for kink compensation in a memory: This disclosure concerns memory kink compensation. One method embodiment includes applying a number of sequentially incrementing programming pulses to a memory cell, with the sequential programming pulses incrementing by a first programming pulse step voltage magnitude. A seeding voltage is applied after applying the number of sequentially incrementing programming pulses.... Agent: Micron Technology, Inc.
20140043913 - Non-volatile semiconductor device: A non-volatile semiconductor device includes first and second selecting transistors; multiple memory cells that are stacked above the substrate; multiple word lines that are connected to control gates of the multiple memory cells; selecting gate lines that are each connected to a gate of one of the selecting transistors; a... Agent: Kabushiki Kaisha Toshiba
20140043914 - Semiconductor memory device and method of operating the same: The semiconductor memory device includes a memory cell block including a plurality of memory cells, a peripheral circuit section configured to perform an erase loop including a supply operation supplying an erase voltage and an erase verification operation to erase data stored in the memory cells, a fail bit counter... Agent:
20140043916 - Erase for 3d non-volatile memory with sequential selection of word lines: An erase operation for a 3D stacked memory device adjusts a start time of an erase period and/or a duration of the erase period for each storage element based on a position of the storage element. A voltage is applied to one or both drive ends of a NAND string... Agent: Sandisk Technologies Inc.
20140043915 - Semiconductor memory device: A semiconductor memory device includes memory strings each of which includes a drain select transistor, memory cells, and a source select transistor, a first bit line coupled to drain select transistors of first group memory strings among the memory strings, a second bit line coupled to drain select transistors of... Agent: Sk Hynix Inc.
20140043917 - Non-volatile semiconductor storage device: According to one embodiment, there is provided a non-volatile semiconductor storage device including a memory cell and a control unit. The memory cell has a gate electrode including a control gate and a charge storage region on a semiconductor substrate and has a channel region under the gate electrode in... Agent: Kabushiki Kaisha Toshiba Corporation
20140043918 - Automated control of opening and closing of synchronous dynamic random access memory rows: An apparatus including a protocol engine and a built-in self test (BIST) engine. The built-in self test (BIST) engine is coupled to the protocol engine. The built-in self test (BIST) engine may be configured to directly control when to open and close rows of a synchronous dynamic random access memory... Agent:
20140043919 - Apparatus and method for hidden-refresh modification: A system and method for modifying a hidden-refresh rate for dynamic memory cells includes monitoring a control signal from a processor and performing a hidden-refresh of dynamic data at a first refresh rate when the control signal is asserted. The dynamic data is refreshed at a second refresh rate when... Agent: Micron Technology, Inc.
20140043920 - Memory device and memory system including the same: A memory device includes a memory cell array and a data input/output circuit. The memory cell array includes a plurality of memory cells connected to a plurality of bit lines and a plurality of word lines. The data input/output circuit is configured to receive data from external data pins of... Agent: Samsung Electronics Co., Ltd.
20140043921 - Method of memory with regulated ground nodes: A method of reading data from an accessed memory cell of an accessed column of an accessed section of a memory array includes, in the accessed section, electrically coupling a first voltage source of at least three voltage sources to a corresponding column internal ground node of the accessed column;... Agent: Taiwan Semiconductor Manufacturing Company, Ltd.
20140043923 - Memory programming methods and memory programming devices: Memory programming devices include a print head that moves across a substrate to deposit memory material on the substrate to form an array of memory cells and programming circuitry coupled to the print head so that the programming circuitry moves across the substrate along with the print head and that,... Agent: Intellipaper LLC
20140043922 - Method of providing write recovery protection in psram and related device: A method of operating a PSRAM includes selecting a bit on a word line of the PSRAM, keeping the word line on for a first predetermined duration after selecting the bit, writing a data into the bit in response to a write command, and keeping the word line on for... Agent:
20140043924 - Configurable memory array: Embodiments disclosed include a memory array having a plurality of bit lines and a plurality of source lines disposed in columns. A plurality of word lines is disposed in rows. A plurality of storage elements have a first subset of storage elements electrically decoupled from the memory array and a... Agent: Qualcomm Incorporated
20140043925 - Ddr psram and data writing and reading methods thereof: A double data rate pseudo SRAM (DDR PSRAM) is provided. The DDR PSRAM includes a data receiver, a memory and an address decoder. The data receiver receives a first single data rate data from a controller via a common bus according to a clock. The address decoder decodes the first... Agent: Mediatek Inc.
20140043926 - Data output circuit of semiconductor device: A data output circuit of a semiconductor device includes: a pattern data generation unit configured to generate pattern data in response to a bank selection signal, a variable delay unit configured to delay a source signal, which is generated in response to the bank selection signal, by a delay time... Agent: Sk Hynix Inc.
20140043927 - Method for optimizing refresh rate for dram: A method for determining an optimized refresh rate involves testing a refresh rate on rows of cells, determining an error rate of the rows, evaluating the error rate of the rows; and repeating these steps for a decreased refresh rate until the error rate is greater than a constraint, at... Agent: International Business Machines Corporation
20140043928 - Sense amplifier circuit for nonvolatile memory: A sense amplifier circuit for a nonvolatile memory that includes a first amplifier to perform a switching operation to output a first signal on a sense amplifier based logic (SABL) node depending on the state of a sensing enable signal, a second amplifier to perform a switching operation to output... Agent:
20140043929 - Address decoder, semiconductor memory device including the same, method of operating the same: A semiconductor memory device and method of operating the same is disclosed. The semiconductor memory device includes an address decoder including pass transistor groups, a memory block selector coupled in common to the pass transistor groups, and a block decoding section configured to deliver an enable signal through the block... Agent: Sk Hynix Inc.02/06/2014 > 50 patent applications in 31 patent subcategories.
20140036564 - Non-volatile memory device with clustered memory cells: An embodiment of a non-volatile memory device includes: a memory array, having a plurality of non-volatile logic memory cells arranged in at least one logic row, the logic row including a first row and a second row sharing a common control line; and a plurality of bit lines. Each logic... Agent: Stmicroelectronics S.r.l.
20140036566 - Discrete three-dimensional memory comprising dice with different beol structures: The present invention discloses a discrete three-dimensional memory (3D-M). It comprises at least a 3D-array die and at least a peripheral-circuit die. At least a peripheral-circuit component of the 3D-M is located on the peripheral-circuit die instead of the 3D-array die. The 3D-array die and the peripheral-circuit die have substantially... Agent: Chengdu HaicunIPTechnology LLC
20140036565 - Memory device and method of manufacturing memory structure: An exemplary memory device includes a substrate and two word lines extending on the substrate. The substrate includes an active area. The two word lines are formed on the active area. Each word line includes a recessed portion corresponding to the active area. The recessed portion is defined by a... Agent: Nanya Technology Corporation
20140036567 - Semiconductor device and method for manufacturing same: According to an embodiment, a method of manufacturing a semiconductor device including a memory array provided on a substrate, and a control circuit provided on a surface of the substrate between the substrate and the memory array, includes steps of forming, in an insulating layer covering a p-type semiconductor region... Agent: Kabushiki Kaisha Toshiba
20140036576 - Electronic devices containing switchably conductive silicon oxides as a switching element and methods for production and use thereof: In various embodiments, electronic devices containing switchably conductive silicon oxide as a switching element are described herein. The electronic devices are two-terminal devices containing a first electrical contact and a second electrical contact in which at least one of the first electrical contact or the second electrical contact is deposed... Agent: William Marsh Rice University
20140036572 - Method for driving nonvolatile storage element, and nonvolatile storage device: Provided is a method for driving a variable resistance nonvolatile storage element that can improve the information holding capability. The method includes: determining whether or not a current that flows through the nonvolatile storage element is larger than or equal to a first verify level IRL (Verify); determining whether or... Agent: Panasonic Corporation
20140036574 - Method for nondestructively reading resistive memory elements: A method for reading out a memory element comprises a series connection. of at least two memory cells A and B each have a stable state A0 or B0 having higher resistance and a stable state A1 or B1 having lower electrical resistance. An electrical variable of the series circuit... Agent: Forschungszentrum Juelich Gmbh
20140036570 - Operating method for memory device and memory array and operating method for the same: An operating method for a memory device and a memory array and an operating method for the same are provided. The operating method for the memory device comprises following steps. A memory device is made being in a set state. A method for making the memory device being in the... Agent: Macronix International Co., Ltd.
20140036568 - Reram device structure: A resistive random access memory (ReRAM) device can comprise a first metal layer and a first metal-oxide layer on the first metal layer. The first metal-oxide layer comprises the first metal. A second metal layer can comprise a second metal over and in physical contact with the first metal-oxide layer.... Agent:
20140036569 - Resistive memory device: A resistive memory device includes a first cell array configured to store data, a second cell array configured to share column lines of the first cell array, a first error correction cell array configured to store an error correction code that corresponds to the data to be stored in the... Agent:
20140036573 - Semiconductor memory device: A semiconductor memory device includes a memory cell array having a plurality of memory cells arranged in a matrix, each memory cell being configured such that a variable resistance element and a selection transistor are connected in series. A set operation for a memory cell (an operation of converting the... Agent: Sharp Kabushiki Kaisha
20140036571 - Semiconductor memory device and operation method thereof: A semiconductor memory device according to an embodiment includes a control circuit configured to apply a first voltage to a selected first line, apply a second voltage to a selected second line, and apply a third voltage and a fourth voltage to a non-selected first line and a non-selected second... Agent: Kabushiki Kaisha Toshiba
20140036575 - Variable resistance memory device and related method of operation: A variable resistance memory device comprises a variable resistance memory cell, a switch that selectively passes a write voltage to an input terminal of the variable resistance memory cell, and a trigger circuit that controls the switch to cut off the write voltage from the input terminal upon determining that... Agent:
20140036577 - Dual-port semiconductor memory and first in first out (fifo) memory having electrically floating body transistor: Multi-port semiconductor memory cells including a common floating body region configured to be charged to a level indicative of a memory state of the memory cell. The multi-port semiconductor memory cells include a plurality of gates and conductive regions interfacing with said floating body region. Arrays of memory cells and... Agent:
20140036579 - Sense amplifier: Embodiments of the invention provide a sense amplifier, a SRAM chip comprising the sense amplifier and a method of performing read operation on the SRAM chip. The sense amplifier according to embodiments of the invention comprises an additional driving assist portion, which further takes a global data bus as input,... Agent: International Business Machines Corporation
20140036578 - Sram read preferred bit cell with write assist circuit: Methods and apparatuses for static memory cells. A static memory cell may include a first pass gate transistor including a first back gate node and a second pass gate transistor including a second back gate node. The static memory cell may include a first pull down transistor including a third... Agent: Qualcomm Incorporated
20140036580 - Memory circuit: A memory circuit is provided. The memory circuit includes a memory array having a bit line (BL), and a memory cell coupled to the BL; a sense amplifier (SA) coupled to the BL; a tracking bit line (TRKBL); and a comparator coupled to the TRKBL and configured to receive a... Agent: Taiwan Semiconductor Manufacturing Company, Ltd.
20140036581 - Sense amplifier for static random access memory: A sense amplifier for a static random access memory (SRAM) is described. In one embodiment, a first pass gate transistor is driven by a bit line true associated with an SRAM cell. A second pass gate transistor is driven by a bit line complement associated with the SRAM cell. A... Agent: International Business Machines Corporation
20140036582 - Nonvolatile memory device: A nonvolatile memory device comprises a memory cell configured to store or output data in a magneto-resistance device in response to a write current applied to a bit line and a source line. A voltage detector is configured to sense potentials loaded in the bit line and the source line.... Agent: Sk Hynix Inc.
20140036583 - Phase change memory device: A phase change memory device with memory cells (2) formed by a phase change memory element (3) and a selection switch (4). A reference cell (2a) formed by an own phase change memory element (3) and an own selection switch (4) is associated to a group (7) of memory cells... Agent: Micron Technology, Inc.
20140036584 - Capacitor-less memory cell, device, system and method of making same: A capacitor-less memory cell, memory device, system and process of forming the capacitor-less memory cell includes forming the memory cell in an active area of a substantially physically isolated portion of the bulk semiconductor substrate. A pass transistor is formed on the active area for coupling with a word line.... Agent: Micron Technology, Inc.
20140036585 - Nonvolatile memory device using a threshold voltage switching material and method for manufacturing same: The present invention relates to a nonvolatile memory device and to a method for manufacturing same. According to the present invention, the blocking insulation layer of a nonvolatile memory device having a typical SONOS structure is replaced with a threshold voltage switching material, which changes to a low resistance state... Agent: Korea University Research And Business Foundation
20140036586 - Memory device having a different source line coupled to each of a plurality of layers of memory cell arrays: In an embodiment, a memory device may have a plurality of layers of memory cell arrays. Each layer may have a plurality of strings of memory cells and a different source line coupled to each layer of the plurality of layers.... Agent: Micron Technology, Inc.
20140036588 - Method of programming a multi-level memory device: Embodiments of the present disclosure provide methods and apparatuses related to programming multilevel memory cells of a memory device. Other embodiments may be described and claimed.... Agent: Micron Technology, Inc.
20140036587 - Structure and method for narrowing voltage threshold distribution in non-volatile memories: Embodiments of the present invention provide a memory array of macro cells. Each macro cell comprises a storage element and a calibration element. The storage element and its corresponding calibration element are part of a common memory array within an integrated circuit, and therefore, are in close proximity to each... Agent: International Business Machines Corporation
20140036589 - Memory cell state in a valley between adjacent data states: The present disclosure includes apparatuses and methods related to memory cell state in a valley between adjacent data states. A number of methods can include determining whether a state of a memory cell is in a valley between adjacent distributions of states associated with respective data states. The method can... Agent: Micron Technology, Inc.
20140036590 - Partial block memory operations: Methods and apparatuses are disclosed, such as those including a block of memory cells that includes strings of charge storage devices. Each of the strings may comprise a plurality of charge storage devices formed in a plurality of tiers. The apparatus may comprise a plurality of access lines shared by... Agent: Micron Technology, Inc.
20140036591 - Memory device: A memory device includes a memory cell array including a plurality of memory cells, a common source line to which sources of the plurality of memory cells are commonly connected, and a second electrical connection path further connecting the common source line to a ground voltage using erase-mode memory cells... Agent: Renesas Electronics Corporation
20140036592 - Semiconductor storage device: A semiconductor storage device has a memory cell array including memory cells and a plurality of redundancy regions arranged in a first direction including flag cells, plural word lines extending in the first direction, and plural bit lines extending in a second direction crossing the first direction, and a controller... Agent: Kabushiki Kaisha Toshiba
20140036594 - Nonvolatile memory device and related method of operation: A flash memory device comprises alternately arranged odd and even memory cells. The odd and even memory cells are connected to corresponding odd and even bitlines, which are connected to corresponding odd and even page buffers. In a read operation of the flash memory device, data is sensed at two... Agent: Samsung Electronics Co., Ltd.
20140036593 - Nonvolatile memory devices, memory systems and methods of performing read operations: Within a non-volatile memory device, a read operation directed to a nonvolatile memory cell having a positive threshold voltage applies a positive read voltage to a selected word line and a first control signal to a page buffer connected to a selected bit line, but if the memory cell has... Agent:
20140036595 - Bitline voltage regulation in non-volatile memory: Systems and methods are provided to minimize write disturb conditions in an untargeted memory cell of a non-volatile memory array. Bitline driver circuits are provided to control a ramped voltage applied both to a bitline of a target memory cell and a neighboring bitline of an untargeted memory cell. Various... Agent: Spansion
20140036597 - Non-volatile semiconductor memory device and reading-out method therefore: In a non-volatile semiconductor memory device outputting a data value determined according to a majority rule by reading-out data from each memory cell for an odd number of times, an odd number of latch circuits, each of which comprises a capacitor for selectively holding a voltage of each of the... Agent: Powerchip Technology Corporation
20140036596 - Sense amplifier for flash memory: A sense amplifier has a reference cell current branch in which a reference cell determines a reference cell current, a column load converts the reference cell current to a reference voltage, and a feedback circuit to maintain the reference cell drain voltage. The sense amplifier also has a main cell... Agent: Winbond Electronics Corporation
20140036600 - Nonvolatile semiconductor memory device: In writing, a first write operation to a first memory cell is executed; and a second write operation for providing a first threshold-voltage distribution to a second memory cell adjacent to the first one, is executed. The first threshold voltage distribution is a lowest threshold-voltage distribution among the positive threshold... Agent: Kabushiki Kaisha Toshiba
20140036599 - Semiconductor memory device and method of operating the same: The semiconductor memory device includes a memory cell array including a plurality of cell transistors, and a page buffer configured to perform an verification operation for verifying a program state of a selected cell transistor by sensing a voltage of a sense node connected to a selected bit line of... Agent:
20140036598 - Semiconductor memory device and operating method thereof: A semiconductor memory device and a method of operating the same are disclosed. The semiconductor memory device includes a select transistor, memory cells connected in serial and dummy memory cells disposed between the select transistor and the memory cells. A higher voltage is applied to a corresponding dummy memory cell... Agent: Sk Hynix Inc.
20140036601 - Temperature based compensation during verify operations for non-volatile storage: A non-volatile storage system that performs programming and reading processes. The programming process includes coarse/fine programming and verify operations. Programming is verified by testing for two different threshold voltage levels while applying the same voltage level to the control gate of a memory cell by testing for current levels through... Agent: Sandisk Technologies Inc.
20140036602 - Memory device: A memory device that accurately tracks memory operations includes a vertical loopback for tracking a sense clock signal to a row address decoder, and read and write reference bit lines in a reference column that include loopbacks for vertically tracking a selected bit line during read and write operations. Preferably... Agent: Freescale Semiconductor, Inc
20140036603 - Storage medium and transmittal system utilizing the same: A storage medium including a processing module and a cell array. The processing module receives test data according to a write command. The cell array stores the test data. The processing module receives verify data according to a comparison command, reads the test data stored in the cell array to... Agent:
20140036604 - Nonvolatile memory device and operating method thereof: A nonvolatile memory device including a memory cell arranged at a region where a word line and a bit line cross each other; a control signal generator configured to be enabled while the nonvolatile memory device operates in a test mode, and generate control signals which are not provided from... Agent: Sk Hynix Inc.
20140036605 - Resistive switching for non volatile memory device using an integrated breakdown element: A method of suppressing propagation of leakage current in an array of switching devices. The method includes providing a dielectric breakdown element integrally and serially connected to a switching element within each of the switching device. A read voltage (for example) is applied to a selected cell. The propagation of... Agent:
20140036606 - Semiconductor device and data processing system including the same: To provide a write amplifier that is connected to bit lines, a read amplifier that is connected to the bit lines via a first switch, and a relief memory element that includes a write port that is connected to the bit lines via a second switch, and a read port... Agent: Elpida Memory, Inc.
20140036607 - Semiconductor memory device and read wait time adjustment method thereof, memory system, and semiconductor device: A system including a controller and a memory device interconnected to the controller; the controller includes a set of first terminals that is connected to the memory device through a set of first signal lines, and a control circuit configured to generate and output onto the set of first terminals... Agent: Elpida Memory, Inc.
20140036608 - Tracking signals in memory write or read operation: A signal generating circuit includes a first circuit, a tracking circuit, and a delay circuit coupled with the first circuit and the tracking circuit. The first circuit is configured to receive a first clock signal and an output signal from an output of the delay circuit and to generate a... Agent: Taiwan Semiconductor Manufacturing Company, Ltd.
20140036609 - Testing retention mode of an sram array: An embodiment of the invention discloses a method for testing the retention mode of an array of SRAM cells. A data pattern is written to the array. After the data pattern is written, a retention circuit is enabled for a period of time that drops the voltage on a supply... Agent: Texas Instruments Incorporated
20140036610 - Devices and methods for controlling memory cell pre-charge operations: A memory having a memory array having bit cells coupled to bit lines. The memory further includes a precharge circuit that precharges bit lines. The memory also includes a control circuit coupled to the precharge circuit that enables the precharge circuit at a beginning portion of a read cycle, keeps... Agent:
20140036611 - Voltage generating system and memory device using the same: A voltage generating system and a memory device using the same are disclosed. The voltage generating system includes an internal voltage regulator, configured to supply a current to pull an internal supply voltage to a regulated level and maintain at the regulated level; and a substrate-bias controlled selector, configured to... Agent: Nanya Technology Corporation
20140036612 - Bti-independent source biasing of memory arrays: A memory device having an array of memory cells and BTI-independent bias circuitry for controlling the bias voltage level of a source node of the array. The bias circuitry has an n-type transistor and a p-type transistor connected in parallel between ground and the source node. The bias circuitry also... Agent: Lsi Corporation
20140036613 - Semiconductor integrated circuit: There are included first and second dynamic circuits and first and second transistors. The first dynamic circuit keeps a first dynamic node at a first level when a plurality of input signals is in a first state, and switches the first dynamic node between the first level and a second... Agent: Panasonic CorporationPrevious industry: Electric power conversion systems
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