Static information storage and retrieval inventions

20090279340 - N-way mode content addressable memory array: A disclosed embodiment is an N-way mode CAM (content addressable memory) array comprising M rows that each contain N subwords. Each of the N subwords has a respective mode cell. Additionally, a mode input bus is coupled to each mode cell of each of the N subwords, and a data... Agent: Farjami & Farjami LLP

20090279341 - Proximity optical memory module: A memory module is formed of multiple memory chips and an optical interface chip fixed on a substrate. The chips are interconnected by proximity communication (PxC) in which each chip includes transmitting and receiving elements, such as electrical pads which form capacitively coupled links when the chips are placed together... Agent: Pvf -- Sun Microsystems Inc. C/o Park, Vaughan & Fleming LLP

20090279342 - Method to improve ferroelectric memory performance and reliability: One embodiment of the present invention relates to a method by which the imprint of a ferroelectric random access memory (FRAM) array is reduced. The method begins when an event that will cause imprint to the memory array is anticipated by an external agent to the device comprising the chip.... Agent: Texas Instruments Incorporated

20090279343 - Operating method of electrical pulse voltage for rram application: Metal-oxide based memory devices and methods for operating and manufacturing such devices are described herein. A method for manufacturing a memory device as described herein comprises forming a metal-oxide memory element, and applying an activating energy to the metal-oxide memory element. In embodiments the activating energy can be applied by... Agent: Macronix C/o Haynes Beffel & Wolfeld LLP

20090279344 - Resistance change memory device: A resistance change memory device includes: a memory cell formed of a variable resistance element and a diode connected in series, the state of the variable resistance element being reversibly changed in accordance with applied voltage or current; and a stabilizing circuit so coupled in series to the current path... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, L.L.P.

20090279345 - Resistive memory element sensing using averaging: A system for determining the logic state of a resistive memory cell element, for example an MRAM resistive cell element. The system includes a controlled voltage supply, an electronic charge reservoir, a current source, and a pulse counter. The controlled voltage supply is connected to the resistive memory cell element... Agent: Dickstein Shapiro LLP

20090279346 - Fault tolerant asynchronous circuits: New and improved methods and circuit designs for asynchronous circuits that are tolerant to transient faults, for example of the type introduced through radiation or, more broadly, single-event effects. SEE-tolerant configurations are shown and described for combinational logic circuits, state-holding logic circuits and SRAM memory circuits.... Agent: Schwegman, Lundberg & Woessner, P.A.

20090279347 - Semiconductor memory device: A semiconductor memory device having a memory cell including a flip-flop; and a memory cell power supply circuit for supplying a low voltage cell power supply voltage to the memory cell. The memory cell power supply circuit supplies a cell power supply voltage in a first period and a different... Agent: Mcdermott Will & Emery LLP

20090279348 - Semiconductor memory device: A semiconductor memory device comprises a memory cell array, which includes a plurality of read word lines, a plurality of first and second read bit lines, and a plurality of memory cells arranged in array. The memory cell includes a first and a second cell node in complementary pair, a... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, L.L.P.

20090279350 - Bipolar switching of phase change device: Memory devices and methods for operating such devices are described herein. A method as described herein includes applying a reset bias arrangement to a memory cell to change the resistance state from the lower resistance state to the higher resistance state. The reset bias arrangement comprises a first voltage pulse.... Agent: Macronix C/o Haynes Beffel & Wolfeld LLP

20090279349 - Phase change device having two or more substantial amorphous regions in high resistance state: Memory devices are described herein along with method for operating the memory device. A memory cell as described herein includes a first electrode and a second electrode. The memory cell also comprises phase change material having first and second active regions arranged in series along an inter-electrode current path between... Agent: Macronix C/o Haynes Beffel & Wolfeld LLP

20090279351 - Semiconductor memory devices and methods having core structures for multi-writing: A semiconductor memory device having an efficient core structure for multi-writing includes a data input/output line, a plurality of memory banks each comprising a plurality of memory cells, a first global bit line and a second global bit line which are shared by the plurality of memory banks, and a... Agent: Myers Bigel Sibley & Sajovec

20090279352 - Storage nodes, phase change memories including a doped phase change layer, and methods of operating and fabricating the same: Example embodiments may provide a doped phase change layer and a method of operating and fabricating a phase change memory with the example embodiment doped phase change layer. The phase change memory may include a storage node having a phase change layer and a switching device, wherein the phase change... Agent: Harness, Dickey & Pierce, P.L.C

20090279353 - Magnetic tunnel junction transistor: A magnetic tunnel junction transistor and method of operating the same. In a particular embodiment, the magnetic tunnel junction transistor includes electrically conductive source, drain and gate electrodes. An electrically insulating material having a non-magnetoelectric region and a magnetoelectric region is positioned such that the non-magnetoelectric region is, at least... Agent: Law Office Of Ido Tuchman (yor)

20090279354 - Stacked magnetic devices: Techniques for improving magnetic device performance are provided. In one aspect, a magnetic device, e.g., a magnetic random access memory device, is provided which comprises a plurality of current carrying lines; and two or more adjacent stacked magnetic toggling devices sharing at least one of the plurality of current carrying... Agent: Ryan, Mason & Lewis, LLP

20090279355 - Low power floating body memory cell based on low bandgap material quantum well: Embodiments of the invention relate to apparatus, system and method for use of a memory cell having improved power consumption characteristics, using a low-bandgap material quantum well structure together with a floating body cell.... Agent: Titash Rakshit

20090279356 - Nonvolatile semiconductor memory device: A memory includes first selective transistors connected between one end of cell strings and bit lines; second selective transistors connected between the other end of the cell strings and a cell source line; a dummy cell string; a first dummy selective transistor connected between one end of the dummy cell... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, L.L.P.

20090279357 - Nonvolatile semiconductor storage device and method of testing the same: A nonvolatile semiconductor storage device includes a memory cell array including a plurality of memory cells arranged at intersection positions of word lines and bit lines in a matrix form, and a row decoder including a row sub-decoder to which a lower address for selecting a word line is input,... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, L.L.P.

20090279358 - Semiconductor device and control method of the same: A semiconductor device includes: a first sector (12) having data that are all to be erased and having flash memory cells; a second sector (14) having data that are all to be retained and having flash memory cells; a sector select circuit (16) selecting a pair of sectors from among... Agent: Spansion LLC C/o Murabito , Hao & Barnes LLP

20090279360 - Nand based nmos nor flash memory cell, a nand based nmos nor flash memory array, and a method of forming a nand based nmos nor flash memory array: A NOR flash nonvolatile memory device provides the memory cell size and a low current program process of a NAND flash nonvolatile memory device and the fast, asynchronous random access of a NOR flash nonvolatile memory device. The NOR flash nonvolatile memory device has an array of NOR flash nonvolatile... Agent: Saile Ackerman LLC

20090279359 - Nand with back biased operation: Methods of programming, reading and erasing memory cells are disclosed. In at least one embodiment, program, sense, and erase operations in a memory are performed with back biased operation, such as to improve high voltage device isolation and cutoff in string drivers and bit line drivers, and no nodes of... Agent: Leffert Jay & Polglaze, P.A. Attn: Daniel J. Polglaze

20090279361 - Addressable memory array: This document discloses non-volatile memory cells and methods of manufacturing the same. The memory arrays are byte, word, and/or page addressable without using a byte select transistor. The byte select transistor is eliminated by using the well, memory transistor control gates, and select transistor gates to selectively program a byte,... Agent: Fish & Richardson P.C.

20090279362 - Partial scrambling to reduce correlation: Decorrelation is provided between data stored in respective pairs of adjacent memory cells in a plurality of bit lines of a flash memory. Each of the pairs of adjacent memory cells is located along a respective one of the bitlines and common to two adjacent wordlines. The decorrelation is achieved... Agent: Zagorin O'brien Graham LLP (023)

20090279363 - Method and system for minimizing number of programming pulses used to program rows of non-volatile memory cells: A flash memory device programs cells in each row in a manner that minimizes the number of programming pulses that must be applied to the cells during programming. The flash memory device includes a pseudo pass circuit that determines the number of data errors in each of a plurality of... Agent: Dorsey & Whitney LLP Intellectual Property Department

20090279364 - Method of programming in a flash memory device: A method of programming a flash memory device includes programming a first memory cell coupled to an even bit line by applying a first program voltage to a word line, and verifying whether the first memory cell is programmed through a first verifying voltage. The first program voltage that is... Agent: Townsend And Townsend And Crew, LLP

20090279365 - Non-volatile semiconductor memory system: A non-volatile semiconductor memory system includes a first memory block group including a plurality of memory blocks each including a plurality of erasable and programmable non-volatile semiconductor memory cells and a second memory block group including a plurality of memory blocks each including a plurality of erasable and programmable non-volatile... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, L.L.P.

20090279367 - Power saving sensing scheme for solid state memory: Methods and apparatus are disclosed, such as those involving a solid state memory device. One such method includes selecting a plurality of memory cells in a memory array. States of a plurality of data bits stored in the selected plurality of memory cells are determined. In determining the states of... Agent: Knobbe Martens Olson & Bear LLP

20090279368 - Circuit and method for generating pumping voltage in semiconductor memory apparatus and semiconductor memory apparatus using the same: A circuit for generating a pumping voltage in a semiconductor memory apparatus includes a control signal generation block configured to generate a first control signal obtained by level-shifting a voltage level of a test signal to a first driving voltage level, a voltage application section configured to supply an external... Agent: Baker & Mckenzie LLP Patent Department

20090279369 - Data output apparatus and method for outputting data thereof: A data output apparatus includes a driver driving unit configured to generate driving signals by using input data when a data output enable signal is enabled, a data driver unit configured to drive an output terminal to a level corresponding to the input data in response to the driving signals... Agent: Baker & Mckenzie LLP Patent Department

20090279366 - Hybrid solid-state memory system having volatile and non-volatile memory: A hybrid solid-state memory system is provided for storing data. The solid-state memory system comprises a volatile solid-state memory, a non-volatile solid-state memory, and a memory controller. Further, a method is provided for storing data in the solid-state memory system. The method comprises the following steps. A write command is... Agent: Eaton Peabody Patent Group, LLC

20090279370 - Memory circuit and method of sensing a memory element: The memory circuit comprises at least one memory element (T1), a sense amplifier (SA) for sensing a state of the memory element (T1), a switching device (T2) for selectively coupling the sense amplifier (SA) to the memory element (T1), The sense amplifier (SA) comprises a first module (M1) and a... Agent: Nxp, B.v. Nxp Intellectual Property & Licensing

20090279371 - Hybrid sense amplifier and method, and memory device using same: Sense circuits, devices and methods are disclosed, including a sense amplifier circuit that has first and second complementary data lines and a sensing circuit. One of the data lines can be coupled to a memory cell for data sensing and the other data line can be used as reference. The... Agent: Edward W. Bulchis, Esq. Dorsey & Whitney LLP

20090279372 - Semiconductor memory device and sense amplifier: In a sense amplifier circuit having a plurality of sense amplifier portions arranged in order, each of the sense amplifier portions includes a transistor that supplies a bit line potential to a bit line pair in a corresponding column of a memory cell array and a gate electrode for supplying... Agent: Young & Thompson

20090279373 - Auto-refresh operation control circuit for reducing current consumption of semiconductor memory apparatus: An auto-refresh operation control circuit for a semiconductor memory apparatus is activated according to a bank active signal for executing a refresh operation and terminates the refresh operation by receiving a precharge signal. The auto-refresh operation control circuit is configured to prevent an over-driving operation during an auto-refresh operation and... Agent: Ladas & Parry LLP

20090279376 - Method and system for selectively limiting peak power consumption during programming or erase of non-volatile memory devices: A power supply circuit is used to supply power having a limited peak magnitude to an array of non-volatile memory cells during programming or erasing of the memory cells. The power supply circuit includes a reference current source supplying a reference current having a predetermined magnitude. The reference current source... Agent: Dorsey & Whitney LLP Intellectual Property Department

20090279374 - System and method for mitigating reverse bias leakage: The present disclosure includes devices, methods, and systems for programming memory, such as resistance variable memory. One embodiment can include an array of resistance variable memory cells, wherein the resistance variable memory cells are coupled to one or more data lines, a row decoder connected to a first side of... Agent: Brooks, Cameron & Huebsch , PLLC

20090279375 - Voltage down converter for high speed memory: A voltage down converter (VDC) applicable to high-speed memory devices. The VDC includes a steady driver and active driver along with at least one additional transistor. The steady driver and active driver are coupled by a transistor switch during device start-up to provide fast ramp-up to operating voltage and current.... Agent: Borden Ladner Gervais LLP Anne Kinsman

20090279377 - Semiconductor memory device: A semiconductor memory device comprises a memory cell array including a plurality of mutually intersecting word lines and bit lines, and a plurality of memory cells connected at intersections thereof and each having a read port and a write port provided independently; and a plurality of word line drivers operative... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, L.L.P.

20090279378 - Semiconductor memory device: A semiconductor memory device including a clock input for receiving a source clock and supplying a generated clock to a plurality of clock transmission lines; a plurality of clock amplifiers, each amplifying a respective generated clock loaded on one of the plurality of clock transmission lines in response to a... Agent: Mannava & Kang, P.C.

20090273961 - Semiconductor device: A technique for increasing rewriting current without increasing a power supply voltage and also reducing location dependency inside a memory array of a resistive state after the rewriting is provided in a resistance change memory in which the resistance value of a memory cell changes between logical values “1” and... Agent: Miles & Stockbridge PC

20090273960 - System for providing on-die termination of a control signal bus: A system for providing on-die termination (ODT) of a control signal bus. The system includes a memory device that includes a plurality of data bus connectors, one or both of a load signal connector and a reset signal connector, a control bus connector, an ODT, and a mechanism. The ODT... Agent: Cantor Colburn LLP-ibm Poughkeepsie

20090273962 - Four-terminal multiple-time programmable memory bitcell and array architecture: Embodiments disclosed herein relate to a non-volatile memory bitcell and arrays thereof, methods of detecting whether the bitcell is in a programmed state, methods of detecting whether the bitcell is in an erased state, methods of setting the bitcell in a programmed state and methods of setting the bitcell in... Agent: Patterson & Sheridan, L.L.P.

20090273963 - Semiconductor storage device, semiconductor storage device manufacturing method and package resin forming method: A ferroelectric capacitor comprising a transistor layer superimposed on a semiconductor substrate, a ferroelectric capacitor layer provided superior to the transistor layer, a wiring layer provided superior to the ferroelectric capacitor layer, and a passivation film. Further, at least one layer of barrier film capable of inhibiting penetration of moisture... Agent: Westerman, Hattori, Daniels & Adrian, LLP

20090273964 - Nonvolatile semiconductor memory device: A nonvolatile semiconductor memory device comprises: a two terminal structured variable resistive element, wherein resistive characteristics defined by current-voltage characteristics at both ends transit between low and high resistance states stably by applying a voltage satisfying predetermined conditions to the both ends, a transition from the low resistance state to... Agent: Birch Stewart Kolasch & Birch

20090273966 - Integrated circuit, memory cell array, memory module, and method of operating an integrated circuit: According to one embodiment of the present invention, an integrated circuit includes a plurality of thermal selectable memory cells, each memory cell being connected to a conductive line, the conductive line having a first portion for applying a heating current, and a second portion for applying a programming current. The... Agent: Slater & Matsil, L.L.P.

20090273967 - Method and integrated circuit for determining the state of a resistivity changing memory cell: A method and an integrated circuit for determining the state of a resistivity changing memory cell. In one embodiment the method includes detecting a first resistance of the resistivity changing memory cell, determining whether the first resistance value is smaller than a predetermined threshold value thereby determining a first result... Agent: Dicke, Billig & Czaja

20090273965 - Nonvolatile memory device: Ferromagnetic layers (18, 22) have magnetizations oriented to such directions as to cancel each other, so that the net magnetization of the ferromagnetic layers (18, 22) is substantially zero. That is, the ferromagnetic layers (18, 22) are exchange-coupled with a nonmagnetic layer (20) interposed therebetween, thereby forming an SAF structure.... Agent: Mcdermott Will & Emery LLP

20090273969 - Capacitive divider sensing of memory cells: The present disclosure includes devices and methods for sensing resistance variable memory cells. One device embodiment includes at least one resistance variable memory cell, and a capacitive divider configured to generate multiple reference levels in association with the at least one resistance variable memory cell.... Agent: Brooks, Cameron & Huebsch , PLLC

20090273970 - Memory device including a programmable resistance element: Disclosed are a phase change memory with improved retention characteristic of a phase change device, and a method for refreshing the phase change memory. The fact that a memory is a DRAM interface compatible memory is exploited. There are provided dummy cells stressed in accordance with the number of times... Agent: Sughrue Mion, PLLC

20090273968 - Method and apparatus for implementing self-referencing read operation for pcram devices: A method of implementing a self-referencing read operation for a PCRAM array includes applying a stimulus to a bit line associated with a selected phase change element (PCE) to be read; comparing a first voltage on a node of the bit line with a second voltage on a delay node,... Agent: Cantor Colburn LLP-ibm Burlington

20090273971 - Continuously driving non-volatile memory element: Embodiments discussed herein generally relate to utilizing non-volatile memory elements to continuously drive other circuitry. There are many advantages to utilizing non-volatile memory to continuously drive other circuitry. For example, back end of the line (BEOL) compatible process may be used to fabricate the non-volatile memory elements that does not... Agent: Patterson & Sheridan, L.L.P.

20090273972 - Magnetic logic element with toroidal multiple magnetic films and a method of logic treatment using the same: A magnetic logic element with toroidal magnetic multilayers (5,6,8,9). The magnetic logic element comprises a toroidal closed section which is fabricated by etching a unit of magnetic multilayers (5,6,8,9) deposited on a substrate. Optionally, the magnetic logic element may also comprise a metal core (10) in the closed toroidal section.... Agent: Connolly Bove Lodge & Hutz, LLP

20090273973 - Multi-level cell access buffer with dual function: An access buffer, such as page buffer, for writing to non-volatile memory, such as Flash, using a two-stage MLC (multi-level cell) operation is provided. The access buffer has a first latch for temporarily storing the data to be written. A second latch is provided for reading data from the memory... Agent: Smart & Biggar P.o. Box 2999, Station D

20090273975 - Non-volatile multilevel memory cells with data read of reference cells: Embodiments of the present disclosure provide methods, devices, modules, and systems for non-volatile multilevel memory cell data retrieval with data read of reference cells. One method includes programming at least one data cell of a number of data cells coupled to a selected word line to a target data threshold... Agent: Brooks, Cameron & Huebsch , PLLC

20090273974 - Nonvolatile memory, verify method therefor, and semiconductor device using the nonvolatile memory: Provided is a nonvolatile memory that realizes a high-speed verify operation. During verify writing/erasing, the writing/erasing and reading are performed at the same time. As to a circuit that performs a verify operation, for instance, there is obtained a construction where the output from a sense amplifier (102) that performs... Agent: Cook Alex Ltd

20090273976 - Semiconductor memory device which includes memory cell having charge accumulation layer and control gate: A semiconductor memory device includes memory cells, a source line, a word line, a bit line, and a driver circuit. The memory cells are formed on a semiconductor layer and have a charge accumulation layer and a control gate on the charge accumulation layer. The word line is connected to... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, L.L.P.

20090273977 - Multilayered nonvolatile memory with adaptive control: A method and device for adaptive control of multilayered nonvolatile semiconductor memory are provided, the device including memory cells organized into groups and a control circuit having a look-up matrix for providing control parameters for each of the groups, where characteristics of each group are stored in the look-up matrix,... Agent: F. Chau & Associates, LLC

20090273980 - Nand architecture memory with voltage sensing: A NAND architecture non-volatile memory voltage sensing data read/verify process and sense amplifier has been described that senses data in floating gate or floating node field effect transistor memory cells using a voltage sensing data read/verify process. The voltage sensing process utilized a reference NAND string and reference memory cell... Agent: Leffert Jay & Polglaze, P.A.

20090273978 - Nand flash memory: A NAND flash memory has a control circuit. The control circuit applies a writing voltage between a control gate and a well by applying a first voltage to the well and a positive second voltage higher than the first voltage to the control gate during the writing operation, and then... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, L.L.P.

20090273979 - Programming method to reduce word line to word line breakdown for nand flash: A NAND architecture non-volatile memory device and programming process programs the various cells of strings of non-volatile memory cells by the application of differing word line pass voltages (Vpass) to the unselected word lines adjacent to the selected word line and memory cell being programmed in order to reduce voltage... Agent: Leffert Jay & Polglaze, P.A.

20090273981 - Methods and apparatuses for programming flash memory using modulated pulses: Methods and apparatuses for programming non-volatile semiconductor memory devices by using modulated pulses are disclosed. Embodiments generally comprise a pulse generator, to create a sequence of pulses and set a threshold voltage of a non-volatile memory cell, and a pulse coupler. Alternative embodiments may include a threshold verifier capable of... Agent: Schubert, Osterrieder & Nickelson, PLLC C/o Cpa Global

20090273982 - Semiconductor memory device, semiconductor device, and data write method: A semiconductor memory device includes an output buffer which outputs an enable signal which makes an external memory device operable, an address buffer which generates an address at which data is held in the external memory device, an input buffer which receives the data held at the address from the... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, L.L.P.

20090273983 - Nonvolatile memory device and programming method: Disclosed is a programming method for a nonvolatile memory device. The method includes; charging word-line signal lines to a pass voltage during a pass voltage charge operation, simultaneously executing an initial precharge operation for strings including program-inhibited cells during the pass voltage charge operation, and applying the pass voltage to... Agent: Volentine & Whitt PLLC

20090273984 - Biasing system and method: Embodiments are provided that include a memory system that includes a memory system, having an access device coupled between a global line and a local line and a voltage source coupled to the global line and configured to output a bias voltage on the global line when the memory system... Agent: Fletcher Yoder (micron Technology, Inc.)

20090273987 - Data output circuit of semiconductor memory apparatus: A data output circuit of a semiconductor memory apparatus includes: a control unit that outputs a first standby instruction signal, a second standby instruction signal, a first output instruction signal, and a second output instruction signal in response to an input of a standby instruction signal, an output instruction signal,... Agent: Venable LLP

20090273986 - Non-volatile memory with redundancy data buffered in remote buffer circuits: A memory has defective locations in its user portion replaceable by redundant locations in a redundant portion. Data latches in column circuits of user and redundant portions allow data sensed from or to be written to a memory to be exchanged with a data bus. A remote redundancy scheme has... Agent: Davis Wright Tremaine LLP - Sandisk Corporation

20090273985 - Semiconductor device having multiple i/o modes: Semiconductor device having multiple I/O modes. The device includes a data buffer configured to receive data; a strobe input buffer configured to receive a data strobe signal, a phase controller configured to shift a phase of the data strobe signal by different numbers of degrees, including 0 degrees, according to... Agent: Mannava & Kang, P.C.

20090273988 - Circuit and methods to improve the operation of soi devices: According to the present invention, a circuit and methods for enhancing the operation of SOI fabricated devices are disclosed. In a preferred embodiment of the present invention, a pulse discharge circuit is provided. Here, a circuit is designed to provide a pulse that will discharge the accumulated electrical charge on... Agent: Connolly Bove Lodge & Hutz LLP

20090273989 - Synchronous command base write recovery time auto precharge control: Methods of operating a memory device and memory devices are provided. For example, a method of operating a memory array is provided that includes a synchronous path and an asynchronous path. A Write-with-Autoprecharge signal is provided to the synchronous path, and various bank address signals are provided to the asynchronous... Agent: Fletcher Yoder (micron Technology, Inc.)

20090273990 - Semiconductor device: There is provided a semiconductor memory device, including: a plurality of bank groups each comprising a plurality of banks; a plurality of data pads grouped by a predetermined number for receiving data for the bank groups, wherein the data pads are divided into a plurality of first pad groups receiving... Agent: Mannava & Kang, P.C.

20090273991 - Semiconductor memory device, operating method thereof, and compression test method thereof: A semiconductor memory device including a plurality of banks, each including a plurality of memory cells, a pattern signal generator configured to generate pattern signals having combinations in response to an input signal applied through an arbitrary pad in a compression test mode. Input paths are configured to transfer the... Agent: Mannava & Kang, P.C.

20090273992 - Semiconductor device and operating method thereof: A semiconductor device includes a pad configured to receive a data strobe signal, and a path selector configured to output the data strobe signal through a corresponding input path during a normal operation, and to output the data strobe signal through a plurality of input paths in response to a... Agent: Mannava & Kang, P.C.

20090273993 - Semiconductor memory device and operation method thereof: A semiconductor memory device that generates a data strobe reset signal for preventing ring-back of a data strobe signal, and an operation method thereof. The semiconductor memory device includes a pulse signal generating unit for generating first and second pulse signals by synchronizing a write instruction with first and second... Agent: Mannava & Kang, P.C.

20090273994 - Dual mode accessing signal control apparatus and dual mode timing signal generating apparatus: A dual mode accessing signal control apparatus for being used in a dummy cells set of a memory, and a dual mode timing signal generating apparatus comprising a dual mode accessing signal control apparatus are provided. The dual mode accessing signal control apparatus respectively generates a write delay signal and... Agent: Holland & Knight LLP

20090273995 - Apparatus for removing crosstalk in semiconductor memory device: An apparatus for removing crosstalk in a semiconductor memory device includes pads for receiving externally provided signals, transmission lines for delivering the signals received by each of the pads to corresponding elements in the apparatus, and capacitors, coupled between adjacent ones of the lines, for adjusting the transmission delay of... Agent: Mannava & Kang, P.C.

20090273996 - Memory testing system and memory module thereof: A testing system with data compressing function includes a third data end, a first encoder, and a second encoder. The testing system receives testing data and testing address for testing if any memory cell fails in a memory. The memory includes a first data end, a second end, and an... Agent: North America Intellectual Property Corporation

20090273997 - Controlling apparatus and controlling method for controlling a pre-charge activity on a sram array: A controlling apparatus and a controlling method for controlling a pre-charge activity on a SRAM array are provided. The controlling apparatus comprises: a detecting module, a controlling module and a pre-charge module. The detecting module is to detect whether the row address of the SRAM array in operation is changed... Agent: Thomas, Kayden, Horstemeyer & Risley, LLP

20090273998 - Bitcell current sense device and method thereof: A memory device includes a sense amplifier to sense the state of a bitcell. The sense amplifier includes two input terminals connected via a switch. One of the input terminals is connected to a node, whereby a current through the node represents a difference in current drawn by a bitcell... Agent: Larson Newman & Abel, LLP

20090273999 - Sense amplifier and data sensing method thereof: A data sensing method for sensing data stored in first and second memory cells includes the steps of: setting a first voltage according to a bit-line voltage corresponding to the first memory cell in response to an enabled level of a first clock signal; providing the first voltage as a... Agent: Thomas, Kayden, Horstemeyer & Risley, LLP

20090274000 - System and method of command based and current limit controlled memory device power up: Devices and systems for powering up a memory device, for example, are disclosed. One such memory device includes power up circuitry configured to receive an external power supply and to provide an internal power supply to the memory device upon receipt of a command. The power up circuitry may be... Agent: Fletcher Yoder (micron Technology, Inc.)

20090274001 - Semiconductor memory device and method for operating the same: Semiconductor memory device and method for operating the same includes a data output unit configured to output data in synchronization with a data output clock and a clock control unit configured to selectively transfer the data output clock to the data output unit under the control of a read command.... Agent: Mannava & Kang, P.C.

20090274002 - Semiconductor integrated circuit and method of processing address and command signals thereof: A semiconductor integrated circuit device includes an input unit configured to receive address and command signals, an internal address generator configured to output an internal address signal by adjusting a timing of the input address signal to correspond to a predetermined internal signal processing timing margin, and an internal command... Agent: Baker & Mckenzie LLP Patent Department

20090262564 - Circuit wiring layout in semiconductor memory device and layout method: An improved circuit wiring layout provides smooth circuit wiring in a peripheral circuit region adjacent to a memory cell region of a semiconductor memory device, and eliminates a write-speed limiting factor. Forming a metal (instead of a metal silicided polysilicon) wiring layer to be connected to a gate layer, to... Agent: F. Chau & Associates, LLC

20090262563 - Memory device capable of one-time data writing and repeated data reproduction, and method and display apparatus for operating the memory device: Provided are a memory device where data may be recorded one time and/or reproduced repeatedly, and a method and display apparatus for operating the memory device. The memory device may include a program area having a plurality of memory cells and a spare area having a plurality of memory cells.... Agent: Harness, Dickey & Pierce, P.L.C

20090262565 - Method for programming nonvolatile memory device: Disclosed is a method for programming a nonvolatile memory device including one time programmable unit cells. The method for programming a nonvolatile memory device including one time programmable (OTP) unit cells, the method comprising applying a pulse type program voltage having a plurality of cycles. The present invention relates to... Agent: Morgan Lewis & Bockius LLP

20090262566 - Mask programmable anti-fuse architecture: A memory array having both mask programmable and one-time programmable memory cells connected to the wordlines and the bitlines. All memory cells of the memory array are configured as one-time programmable memory cells. Any number of these one-time programmable memory cells are convertible into mask programmable memory cells through mask... Agent: Borden Ladner Gervais LLP Anne Kinsman

20090262567 - Nonvolatile memory device: A nonvolatile memory device including one-time programmable (OTP) unit cell is provided. The nonvolatile memory device includes: a unit cell; a detecting unit configured to detect data from the unit cell; and a read voltage varying unit configured to vary an input voltage and supply a varied read voltage to... Agent: Morgan Lewis & Bockius LLP

20090262568 - Semiconductor memory device: A resistance variable memory reduces the nonuniformity of resistance values after programming, so that a rewrite operation can be performed on a memory cell at high speed. A reference resistor is connected in series with the resistance variable memory cell, and a sensor amplifier detects whether the potential at an... Agent: Miles & Stockbridge PC

20090262569 - Semiconductor memory device with stacked memory cell structure: A semiconductor device including: a first memory cell including a non-volatile first variable resistance element that stores data by varying a resistance value and a selection transistor that selects the first variable resistance element; a first memory layer provided with more than one such first memory cell arranged in a... Agent: Spansion LLC C/o Murabito , Hao & Barnes LLP

20090262570 - Giant magnetoresistance (gmr) memory device: The present magnetic memory device includes a pinned ferromagnetic layer, and a switchable ferromagnetic layer, the memory device being programmable to have a first programmed state wherein the resistance of the device is at a first level, a second programmed state wherein the resistance of the device is at a... Agent: Hamilton & Terrile, LLP - Amd

20090262571 - Magnetic random access memory and operating method of magnetic random access memory: A magnetic random access memory includes: a first and second wirings, a plurality of third wirings, a plurality of memory cells and a terminating unit. The first and second wirings extend in a Y direction. The plurality of third wirings extends in an X direction. The memory cell is provided... Agent: Sughrue Mion, PLLC

20090262572 - Multilayer storage class memory using externally heated phase change material: A multi-layer, phase change material (PCM) memory apparatus includes a plurality of semiconductor layers sequentially formed over a base substrate, wherein each layer comprises an array of memory cells formed therein, each memory cell further including a PCM element, a first diode serving as a heater diode in thermal proximity... Agent: Cantor Colburn LLP-ibm Yorktown

20090262573 - Multilevel nonvolatile memory device using variable resistance: A multilevel nonvolatile memory device using a resistance material is provided. The multilevel nonvolatile memory device includes at least one multilevel memory cell and a read circuit. The at least one multilevel memory cell has a level of resistance that varies according to data stored therein. The read circuit first... Agent: Volentine & Whitt PLLC

20090262574 - Semiconductor device: A highly reliable large capacity phase change memory module is realized. A semiconductor device according to the present invention includes a memory array having a structure in which a storage layer using a chalcogenide material and a memory cell constituted of a diode are stacked, and an initialization condition and... Agent: Miles & Stockbridge PC

20090262575 - Thin film magnetic memory device capable of conducting stable data read and write operations: A tunnel magnetic resistive element forming a magnetic memory cell includes a fixed magnetic layer having a fixed magnetic field of a fixed direction, a free magnetic layer magnetized by an applied magnetic field, and a tunnel barrier that is an insulator film provided between the fixed and free magnetic... Agent: Mcdermott Will & Emery LLP

20090262577 - Multi-level cell flash memory: Most drivers of flash memories used for embedded systems are often designed to use power from batteries, but not from a commercial power supply, and therefore are required to be protected against power failures. In addition, if a power failure occurs in the middle of programming a cell, the driver... Agent: Ditthavong Mori & Steiner, P.C.

20090262578 - Use of data latches in cache operations of non-volatile memories: Methods and circuitry are present for improving performance in non-volatile memory devices by allowing the inter-phase pipelining of operations with the same memory, allowing, for example, a read operation to be interleaved between the pulse and verify phases of a write operation. In the exemplary embodiment, the two operations share... Agent: Davis Wright Tremaine LLP - Sandisk Corporation

20090262580 - Flash memory device adapted to prevent read failures due to dummy strings: In a NAND flash memory device, a dummy NAND string is arranged between a plurality of normal NAND strings. A dummy bit line connected to the dummy NAND string is formed and/or controlled such that when program voltages are applied to the normal NAND strings, memory cells within the dummy... Agent: Volentine & Whitt PLLC

20090262579 - Non-volatile semiconductor memory device and method of writing data in non-volatile semiconductor memory devices: The device has a data write mode to boost a first boost channel region that contains a non-write selected memory cell and non-selected memory cells located closer to the first selection gate transistor, and a second boost channel region that contains non-selected memory cells located closer to the second selection... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, L.L.P.

20090262581 - Non volatile memory: An electrically programmable and erasable non-volatile semiconductor memory such as a flash memory is designed into a configuration in which, when a cutoff of the power supply occurs in the course of a write or erase operation carried out on a memory cell employed in the non-volatile semiconductor memory, the... Agent: Miles & Stockbridge PC

20090262582 - Method of programming flash memory device: Flash memory devices include a memory array having a plurality of NAND strings of EEPROM cells therein. A word line driver is provided to improve programming efficiency. The word line driver is electrically coupled to the memory array by a plurality of word lines. The word line driver includes a... Agent: Myers Bigel Sibley & Sajovec

20090262576 - Flash memory device and operating method of flash memory device: Disclosed is an operating method of a flash memory device, which includes normal memory cells and dummy memory cells. The operating method includes programming the normal memory cells and programming the dummy memory cells. A dummy pass voltage used for programming the dummy memory cells is different from a normal... Agent: Volentine & Whitt PLLC

20090262583 - Floating gate memory device with interpoly charge trapping structure: A charge trapping floating gate is described with asymmetric tunneling barriers. The memory cell includes a source region and a drain region separated by a channel region. A first tunneling barrier structure is disposed above the channel region. A floating gate is disposed above the first tunneling barrier structure covering... Agent: Macronix C/o Haynes Beffel & Wolfeld LLP

20090262584 - Nonvolatile memory cell and data latch incorporating nonvolatile memory cell: A nonvolatile memory cell, comprising: a first NMOS transistor having a floating gate; a second NMOS transistor and a third NMOS transistor connected to a drain side and a source side of the first NMOS transistor; and a first PMOS transistor and a second PMOS transistor each having the floating... Agent: The Webb Law Firm, P.C.

20090262589 - Semiconductor memory device and method for operating the same: A semiconductor memory device and a method for operating the same can improve a refresh characteristic of the semiconductor memory device by physically writing only logic low data in memory cells, irrespective of logic level of input data, either high or low. The semiconductor memory device includes a positive word... Agent: Mannava & Kang, P.C.

20090262585 - Input buffer and method with ac positive feedback, and a memory device and computer system using same: An input buffer having a comparator that receives an input signal, a reference signal and a positive feedback. The comparator compares the input signal relative to the reference signal and generates an output signal transitioning between a first logic state and a second logic state responsive to the magnitude of... Agent: Dorsey & Whitney LLP Intellectual Property Department

20090262586 - Semiconductor memory device voltage generating circuit for avoiding leakage currents of parasitic diodes: A voltage generating circuit for semiconductor memory devices for use in avoiding the occurrence of leakage currents associated with parasitic diodes is presented. The circuit controls and stabilizes the generation of a fedback negative voltage to prevent parasitic diode malfunctions by a in a wordline driver. The voltage generating circuit... Agent: Ladas & Parry LLP

20090262587 - Semiconductor memory device: A semiconductor memory device includes a plurality of memory cell array blocks connected to word lines, source lines, and bit lines, each memory cell array including memory cells each having a transistor with a floating body, a reference voltage generator configured to have a reference memory cell and generate a... Agent: Lee & Morse, P.C.

20090262588 - Power savings with a level-shifting boundary isolation flip-flop (lsiff) and a clock controlled data retention scheme: An apparatus for providing active mode power reduction for circuits having data retention includes a master slave flip flop (MSFF) for latching a data input. An output level shifter (OLS), coupled to the MSFF, retains the data input in response to the MSFF being operable in an active power saving... Agent: Texas Instruments Incorporated

20090262590 - Semiconductor memory device: A semiconductor memory device has a command decoder responsive to a plurality of commands to set the semiconductor memory device to a normal mode, for generating control signals corresponding to the commands, respectively, and a row address prelatch circuit for holding a row address except for a bank address input... Agent: Katten Muchin Rosenman LLP

20090262591 - Nand system with a data write frequency greater than a command-and-address-load frequency: The invention provides methods and apparatus. A NAND flash memory device receives command and address signals at a first frequency and a data signal at a second frequency that is greater than the first frequency.... Agent: Leffert Jay & Polglaze, P.A.

20090262592 - Method and apparatus for synchronization of row and column access operations: A circuit for synchronizing row and column access operations in a semiconductor memory having an array of bit line pairs, word lines, memory cells, sense amplifiers, and a sense amplifier power supply circuit for powering the sense amplifiers, the circuit comprising, a first delay circuit for delaying a word line... Agent: Borden Ladner Gervais LLP Anne Kinsman

20090262593 - Circuit and method for retrieving data stored in semiconductor memory cells: A circuit comprises at least one memory cell adapted to store data in terms of values of an electrical characteristic thereof, which exhibits a variability with temperature according to a first variation law; a voltage generator is provided for generating a voltage to be supplied to the at least one... Agent: Gerbera/bstz Blakely Sokoloff Taylor & Zafman LLP

20090262594 - Memory cells with power switch circuit for improved low voltage operation: Static random access memory (SRAM) cells and methods of operation are provided which may be used to provide improved writeability and stability to support low voltage operation of memory devices. For example, in one implementation, by temporarily interrupting the connection between portions of an SRAM cell and a power source... Agent: Osha Liang L.L.P./sun

20090262596 - Address decoder and/or access line driver and method for memory devices: Address decoders and access line drivers are provided. One such row decoder and access line driver receives power supply voltages in a manner that prevents CHC damage and avoids GIDL currents in transistors in the decoder and driver. The row decoder and a latch in the driver are powered by... Agent: Edward W. Bulchis, Esq. Dorsey & Whitney LLP

20090262595 - Method and apparatus for operating maskable memory cells: A plurality of masked memory cells organized in at least two groups, each group using an individual mask signal, is operated by providing a logically valid mask signal only for a selected group comprising the memory cell to be accessed while a logically invalid mask signal are used for all... Agent: Dickstein Shapiro LLP