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Static information storage and retrieval

Below are recently published patent applications awaiting approval from the USPTO. Recent week's RSS XML file available below.
Listing for abstract view: USPTO application #, Title, Abstract excerpt,Patent Agent. Listing format for list view: USPTO National Class full category number, title of the patent application.
  
12/04/2014 > 47 patent applications in 26 patent subcategories.

20140355326 - Non-volatile memory device: According to one embodiment, a non-volatile memory device includes: a plurality of first interconnects, and each of the first interconnects extending in a first direction; a plurality of second interconnects, and each of the second interconnects extending in a second direction intersecting with the first direction; a memory cell connected... Agent: Kabushiki Kaisha Toshiba

20140355325 - Packaging of high performance system topology for nand memory systems: A topology for memory circuits of a non-volatile memory system reduces capacitive loading. For a given channel, a single memory chip can be connected to the controller, but is in turn connected to multiple other memory devices that fan out in a tree-like structure, which can also fan back in... Agent: Sandisk Technologies Inc.

20140355327 - Memory module and memory system having the same: A memory system includes a controller, a first memory module, and a second memory module. The first memory module includes a first number of memory packages and a second number of memory packages. The second memory module includes a third number of memory packages and a fourth number of memory... Agent: Samsung Electronics Co., Ltd.

20140355328 - Ferroelectric memory cell for an integrated circuit: An integrated circuit includes a ferroelectric memory cell. In one embodiment, the ferroelectric memory cell includes a first oxide storage layer, a second oxide storage layer, and an amorphous layer disposed between the first and second oxide storage layers. Each of the first and second oxide storage layers includes a... Agent:

20140355330 - Integrated circuit:

20140355329 - Method and apparatus for common source line charge transfer: A method and apparatus for charge transfer comprising a resistive random access memory (ReRAM) cell, coupled to a common source voltage line (CSL) for controlling state of the ReRAM cell, and a charge transfer circuit, coupled to the memory cell through the CSL and a charge consumption circuit, for transferring... Agent: Sony Corporation

20140355331 - Multi-level memory cell with continuously tunable switching: The present disclosure provides a data storage device that includes multi-level memory cells. The data storage device may include circuitry configured to write data to the multi-level memory cell. The write circuitry may include compliance circuitry configured to implement continuously tunable switching. The write circuitry may be configured to select... Agent: Hewlett-packard Development Company, L.p.

20140355333 - Semiconductor memory device and driving method thereof: A semiconductor device which stores data by using a transistor whose leakage current between source and drain in an off state is small as a writing transistor. In a matrix including a plurality of memory cells in which a drain of the writing transistor is connected to a gate of... Agent:

20140355332 - Volatile memory device and refresh method thereof: Provided is a refresh method of a volatile memory device. The method includes: detecting a number of disturbances that affect a second memory area as the number of accesses to a first memory area is increased; outputting an alert signal from the volatile memory device to an outside of the... Agent: Samsung Electronics Co., Ltd.

20140355334 - Handshaking sense amplifier: Handshaking sense amplifier. In accordance with a first embodiment, an electronic circuit includes a sense amplifier configured to differentially sense contents of a memory cell. The circuit also includes a self-timing circuit configured to detect a completion of evaluation by the sense amplifier; and to initiate a subsequent memory operation... Agent:

20140355335 - Static random access memory system and operation method thereof: A static random access memory system includes a static random access memory, a multiplexer, an input buffer, an output buffer, and a shifter. The input buffer writes write data stored in the input buffer to addresses of the static random access memory corresponding to a write address signal according to... Agent: Etron Technology, Inc.

20140355337 - Method of pinning domain walls in a nanowire magnetic memory device: There is provided a method of pinning domain walls in a magnetic memory device (10) comprising using an antiferromagnetic material to create domain wall pinning sites. Junctions (22) where arrays of ferromagnetic nanowires (16) and antiferromagnetic nanowires (20) cross exhibit a permanent exchange bias interaction between the ferromagnetic material and... Agent: University Of York

20140355336 - Semiconductor memory device: According to one embodiment, the semiconductor memory device includes a first memory cell, first, second, third and fourth interconnect lines and first, second and third write circuits. The first memory cell includes a first magnetic tunnel junction (MTJ) element. The first interconnect line is connected to one end of the... Agent:

20140355338 - Non-volatile phase-change resistive memory: A method for implementing a system containing at least one memory device including a plurality of non-volatile memory cells each including a phase-change material configured to change state reversibly between at least an amorphous state and a crystalline state having different electrical resistances. The method includes steps of manufacturing the... Agent: Commissariat A L'energie Atomique Et Aux Ene Alt

20140355339 - Driving method of semiconductor device: In a memory cell including first to third transistors, the potential of a bit line is set to VDD or GND when data is written through the first transistor. In a standby period, the potential of the bit line is set to GND. In reading operation, the bit line is... Agent: Semiconductor Energy Laboratory Co., Ltd.

20140355342 - Dynamically configurable mlc state assignment: Memory devices facilitating a data conditioning scheme for multilevel memory cells. For example, one such memory device is capable of inverting the lower page bit values of a complete page of MLC memory cells when a count of the lower page data values is equal to or greater than a... Agent: Micron Technology, Inc.

20140355341 - Read threshold estimation in analog memory cells using simultaneous multi-voltage sense: A method includes dividing a group of analog memory cells into multiple subsets. The memory cells in the group are sensed simultaneously by performing a single sense operation, while applying to the subsets of the memory cells respective different sets of read thresholds, so as to produce respective readout results.... Agent:

20140355340 - Updating read voltages: A data storage device includes a memory and a controller. Read voltages are updated based on adjusting a first read voltage without adjusting a second read voltage to generate multiple sets of read voltages, and the multiple sets of read voltages are used to generate multiple representations of data. A... Agent: Sandisk Technologies Inc.

20140355343 - Semiconductor memory having both volatile and non-volatile functionality and method of operating: Semiconductor memory having both volatile and non-volatile modes and methods of operation. A semiconductor storage device includes a plurality of memory cells each having a floating body for storing, reading and writing data as volatile memory. The device includes a floating gate or trapping layer for storing data as non-volatile... Agent:

20140355344 - Adaptive operation of three dimensional memory: When data from a portion of a three dimensional NAND memory array is determined to be uncorrectable by Error Correction Code (ECC), a determination is made as to whether data is uncorrectable by ECC throughout some unit that is larger than the portion. If modified read conditions provide ECC correctable... Agent:

20140355345 - Adaptive operation of three dimensional memory: When data from a portion of a three dimensional NAND memory array is determined to be uncorrectable by Error Correction Code (ECC), a determination is made as to whether data is uncorrectable by ECC throughout some unit that is larger than the portion. If modified read conditions provide ECC correctable... Agent: Sandisk Technologies Inc.

20140355348 - Flash memory system and word line interleaving method thereof: Provided are a flash memory system and a word line interleaving method thereof. The flash memory system includes a memory cell array, and a word line interleaving logic. The memory cell array is connected to a plurality of word lines. The word line (WL) interleaving logic performs an interleaving operation... Agent:

20140355347 - Mitigating reliability degradation of analog memory cells during long static and erased state retention: A method in a non-volatile memory, which includes multiple memory cells that store data using a predefined set of programming levels including an erased level, includes receiving a storage operation indicating a group of the memory cells that are to be retained without programming for a long time period. The... Agent: Apple Inc.

20140355346 - Nonvolatile memory device: A nonvolatile memory device includes first to N-th memory blocks, wherein N is an integer and N≧3. Each memory block, of the first to N-th memory blocks comprises first to (M−1)-th strings, wherein each string, of the first to (M−1)-th strings, includes drain-side memory cells, source-side memory cells, and a... Agent: Sk Hynix Inc.

20140355349 - Semiconductor memory device: According to one embodiment, a semiconductor memory device includes a memory cells, a selection transistor, a memory string, a block, and a transfer circuit. The memory cells are stacked on a semiconductor substrate. In the memory string, the memory cells and the selection transistor are connected in series. The block... Agent: Kabushiki Kaisha Toshiba

20140355350 - Three dimensional stacked nonvolatile semiconductor memory: A three dimensional stacked nonvolatile semiconductor memory according to an example of the present invention includes a memory cell array comprised of first and second blocks disposed side by side in a first direction, and a driver disposed on one end of the memory cell array in a second direction... Agent: Kabushiki Kaisha Toshiba

20140355351 - Controller: A controller for a memory device having a bit line, a source line, and a plurality of strings of memory cell transistors connected between the bit line and the source line, is configured to update first and second values for each string when read and write operations are carried out... Agent: Kabushiki Kaisha Toshiba

20140355352 - Memory array with power-efficient read architecture: Various embodiments comprise apparatuses and methods including a three-dimensional memory apparatus having upper strings and lower strings. The upper strings can include a first string of memory cells and a second string of memory cells arranged substantially parallel and adjacent to one another. The lower strings can include a third... Agent:

20140355353 - Current sensing amplifier and sensing method thereof: A sensing method of a current sensing amplifier is provided used for determining a storing state of a cell of a non-volatile memory device during a read cycle. After a sensing node and a reference node are adjusted to a constant voltage, the sensing node and the reference node are... Agent:

20140355354 - Integrated circuit and operation method thereof: An integrated circuit includes a mirroring/amplifying unit suitable for mirroring and amplifying a sensing current that flows on a signal transmission line coupled to an internal circuit, and outputting an amplified current; a reference current generating unit suitable for generating a reference current; and a state determination unit suitable for... Agent: Sk Hynix Inc.

20140355355 - Methods, devices, and systems for adjusting sensing voltages in devices: The present disclosure includes methods, devices, and systems for adjusting sensing voltages in devices. One or more embodiments include memory cells, and a controller configured to perform a sense operation on the memory cells using a sensing voltage to determine a quantity of the memory cells having a threshold voltage... Agent:

20140355356 - Data transfer circuit and memory including the same: A data transfer circuit includes a plurality of first lines, a second line suitable for receiving data from a first line selected among the first lines, a third line suitable for transferring data to the first line selected among the first lines, a plurality of driving units, each suitable for... Agent: Sk Hynix Inc.

20140355357 - Method for writing in an eeprom-type memory including a memory cell refresh: The present disclosure relates to a method for writing in an EEPROM memory, the method comprising steps of: storing the bits of a word to be written in first memory units, erasing a word to be modified, formed by first memory cells connected to a word line and first bit... Agent: Stmicroelectronics (rousset) Sas

20140355361 - Circuit in dynamic random access memory devices: A circuit in dynamic random access memory devices includes a command extension circuit. The command extension circuit is configured to generate at least one multiple-cycle command signal by lengthening a single-cycle clock command signal from a command decoding circuit. Control logic extends and reduces the multiple-cycle command signal to provide... Agent: Nanya Technology Corporation

20140355358 - Circuits and methods for efficient execution of a read or a write operation: A system for efficient execution of a read or a write is described. The system includes a memory array including a way. The system further includes a read and compare circuit. The read and compare circuit compares data stored within lower address memory cells of the way with information received... Agent: Oracle International Corporation

20140355359 - Continuous tuning of preamble release timing in a double data-rate memory device interface: Preamble release training in a double data-rate dynamic random access memory interface uses feedback from read operations to adjust the preamble release signal so that the preamble release signal continues to be activated close to the middle of the preamble. A first signal, and then a second signal, are generated... Agent:

20140355360 - High speed and low offset sense amplifier: A sense amplifier includes a sensing circuit and an equalizing circuit. The sensing circuit is configured to supply one or more output signals according to one or more input signals. The equalizing circuit is configured to bring the sensing circuit to a metastable state from which the sensing circuit switches... Agent:

20140355362 - Pipelined one cycle throughput for single-port 6t ram: Pipelined one cycle throughput for single-port 6T RAM. In accordance with a first embodiment, an electronic circuit is configured to perform consecutive read accesses using one sense amplifier. The electronic circuit includes circuitry configured to precharge the sense amplifier, circuitry configured to precharge a sense node coupled to the sense... Agent:

20140355364 - Memory and memory system: A memory may include first to Nth cell arrays configured to include a plurality of memory cells and one or more first to Nth data input/output pads respectively corresponding to the first to Nth cell arrays, wherein the one or more first to Nth data input/output pads are configured to... Agent: Sk Hynix Inc.

20140355363 - Memory chip and semiconductor package including the same: A memory chip includes a data processing block suitable for serial-parallel converting data inputted and for parallel-serial converting data to be outputted, a write data transmitting unit suitable for transmitting the data serial-parallel converted by the data processing block to a write data interlayer channel, a write data receiving unit... Agent: Sk Hynix Inc.

20140355365 - Pulse generator: Various circuits and methods of operating circuits are disclosed. A circuit may include a pulse generator and a latch having an output configured to trigger the pulse generator, wherein the latch is configured to be set by an input signal and reset by feedback from the pulse generator. A method... Agent:

20140355366 - Multiple data rate memory with read timing information: A memory includes a memory array, read circuitry, and a strobe generator. The read circuitry is configured to provide read data from the memory array in response to a read request, wherein the read circuitry provides the read data in accordance with a first clock. The strobe generator is configured... Agent:

20140355367 - Multiple data rate memory with read timing information: A memory includes a memory array, read circuitry, and a strobe generator. The read circuitry is configured to provide read data from the memory array in response to a read request, wherein the read circuitry provides the read data in accordance with a first clock. The strobe generator is configured... Agent: Freescale Semiconductor, Inc.

20140355369 - Memory operation upon failure of one of two paired memory devices: A method and apparatus for continued operation of a memory module, including a first and second memory device, when one of memory devices has failed. The method includes receiving a write operation request to write a data word, having first and second sections, by a first memory module. The memory... Agent:

20140355368 - Semiconductor device: An embodiment of the present invention provides a semiconductor, including a non-volatile storage unit suitable for storing one or more first addresses; an address storage unit suitable for storing the first addresses sequentially received from the non-volatile storage unit as second addresses while deleting previously stored second addresses identical to... Agent: Sk Hynix Inc.

20140355370 - Semiconductor system and semiconductor package: A semiconductor system includes a plurality of memory chips. Each of the memory chips includes an oscillator suitable for generating a periodic wave in a self refresh mode, and a delay unit suitable for delaying the periodic wave to generate a refresh pulse and for setting a delay value based... Agent: Sk Hynix Inc.

20140355371 - Address detection circuit, memory system including the same: An address detection circuit includes an address storage unit suitable for receiving an address when an active command is activated, and storing recently inputted N number of addresses; and an address determination unit suitable for determining whether an address currently inputted to the address storage unit is already inputted at... Agent: Sk Hynix Inc.

  
11/27/2014 > 46 patent applications in 28 patent subcategories.

20140347907 - Electronic component including a matrix of tcam cells: Electronic component including a ternary content-addressable memory component, configured to compare the input data items with a set of pre-recorded reference data words; the memory component incorporates a matrix of elementary cells arranged in lines and columns; each line incorporates cells in each of which is recorded one bit of... Agent: Stmicroelectronics S.a.

20140347906 - Tcam memory cell and component incorporating a matrix of such cells: A ternary content-addressable cell is configured to compare an input binary data item present on an input terminal with two reference binary data items, and to output a match signal on a match line. The cell includes: a first storage circuit (storing a potential representing the first reference binary data... Agent: Stmicroelectronics Sa

20140347908 - Semiconductor memory and method of making the same: A semiconductor cell comprises a plurality of metal layers. A first layer comprises a VDD conductor, a bit-line, and a complimentary bit-line. Each of the VDD conductor, the bit-line, and the complementary bit-line extend in a first direction. A second layer comprises a first VSS conductor and a first word-line.... Agent:

20140347909 - Semiconductor device and semiconductor memory device: A semiconductor device includes a fuse array having a plurality of fuse sets suitable for outputting a plurality of fuse status signals having different levels according to whether fuses of the plurality of fuse sets are cut or not, a code counter suitable for counting selection codes in a preset... Agent: Sk Hynic Inc.

20140347914 - Multi-function resistance change memory cells and apparatuses including the same: Various embodiments comprise apparatuses including drive circuitry to provide signal pulses of a selected time duration and/or amplitude to a number of memory cells. The memory cells may include an array of resistance change memory cells to be electrically coupled to the drive circuitry. The resistance change memory cells may... Agent:

20140347911 - Nonvolatile semiconductor memory device: A nonvolatile semiconductor memory device according to an embodiment comprises a memory cell block that includes a memory cell array, the memory cell array including: a plurality of first lines; a plurality of second lines intersecting the plurality of first lines; and a memory cell that is provided at each... Agent: Kabushiki Kaisha Toshiba

20140347910 - Reading memory elements within a crossbar array: A method for reading the state of a memory element within a crossbar memory array includes storing a first electric current sensed from a half-selected target memory element within the crossbar memory array; and outputting a final electric current based on the stored first electric current and a second electric... Agent: Hewlett-packard Development Company, L.p.

20140347913 - Resistive switching memory device and method for operating the same: A resistive switching memory device and a method for operating the same are disclosed. The device includes a plurality of resistive switching memory units arranged in a matrix, each of which includes a switching element and a resistive switching device, and the switching element being connected to a word line... Agent:

20140347912 - Sense amplifier local feedback to control bit line voltage: Methods for precharging bit lines using closed-loop feedback are described. In one embodiment, a sense amplifier may include a bit line precharge circuit for setting a bit line to a read voltage prior to sensing a memory cell connected to the bit line. The bit line precharge circuit may include... Agent: Sandisk 3d LLC

20140347915 - Cmos image sensor with noise cancellation: A memory comprises a two dimensional array of memory cells. Each memory cell comprises a first transistor, a second transistor and a capacitor. A multi-bit datum is stored as one of a plurality of voltage signal levels driven over a vertical input signal line and further across a source and... Agent:

20140347916 - Eight transistor (8t) write assist static random access memory (sram) cell: Disclosed are devices, systems and/or methods relating to an eight transistor (8T) static random access memory (SRAM) cell, according to one or more embodiments. In one embodiment, an SRAM storage cell is disclosed comprising a word line, a write column select line, a cross-coupled data latch, and a first NMOS... Agent: Nvidia Corporation

20140347917 - Static random access memory structures: A static random access memory structure is provided. The static random access memory structure includes a storage region having a first storage node and a second storage node which is complementary to the first storage node. The static random access memory structure also includes a reading region having a first... Agent: Semiconductor Manufacturing International (shanghai) Corporation

20140347918 - Mram write pulses to dissipate intermediate state domains: A write method for a STT-RAM MTJ is disclosed that substantially reduces the bit error rate caused by intermediate domain states generated during write pulses. The method includes a plurality of “n” write periods or pulses and “n−1” domain dissipation periods where a domain dissipation period separates successive write periods.... Agent: Headway Technologies, Inc.

20140347919 - Semiconductor storage device: A semiconductor storage device includes: a memory cell array in which a plurality of pairs of bit lines and source lines, a plurality of word lines, and a plurality of resistance change memory cells are arranged; a write driver, a sense amplifier, a global bit line and a global source... Agent: Fujitsu Limited

20140347920 - Dual mode clock and data scheme for memory programming: A Phase-Change Memory (PCM) includes a factory programming interface to receive data changing on both a positive transition and a negative transition of a dual edge clock. A transition detector generated internal clock provides a delayed edge to latch the program data. This dual-edge clock scheme provides a doubling in... Agent:

20140347921 - Semiconductor memory device and method of operating the same: A semiconductor memory device includes memory cell strings including selection transistors and memory cells coupled between the selection transistors, a peripheral circuit configured to apply an operating voltage to the memory cell strings during a read operation or a verify operation, and a control circuit configured to control the peripheral... Agent: Sk Hynix Inc.

20140347922 - Semiconductor memory device and method of operating the same: A method of operating a semiconductor memory device includes checking an erase-program cycling number, setting a target erase level to be maintained when the erase-program cycling number is less than a predetermined critical number, and setting the target erase level to be increased when the erase-program cycling number is greater... Agent: Sk Hynix Inc.

20140347924 - Data storage in analog memory cells across word lines using a non-integer number of bits per cell: A method for data storage includes accepting data for storage in an array of analog memory cells, which are arranged in rows associated with respective word lines. At least a first page of the data is stored in a first row of the array, and at least a second page... Agent:

20140347925 - Internal data load for non-volatile storage: Techniques are disclosed herein for performing an Internal Data Load (IDL) to sense non-volatile storage elements. Read pass voltages that are applied to the two neighbor word lines to a selected word line may be adjusted to result in a more accurate IDL. The read pass voltage for one neighbor... Agent:

20140347923 - Threshold voltage calibration using reference pattern detection: A memory controller identifies a predominant type of error of a memory unit of solid state memory cells. An error type differential is calculated. The error type differential is a difference between a number of charge loss errors and a number of charge gain errors of the memory unit. A... Agent: Seagate Technology LLC

20140347926 - Vertical memory with body connection: An embodiment of an apparatus includes a substrate, a body semiconductor, a vertical memory access line stack over the body semiconductor, and a body connection to the body semiconductor.... Agent:

20140347929 - Apparatuses and methods for transposing select gates: Apparatuses and methods for transposing select gates, such as in a computing system and/or memory device, are provided. One example apparatus can include a group of memory cells and select gates electrically coupled to the group of memory cells. The select gates are arranged such that a pair of select... Agent:

20140347928 - Low disturbance, power-consumption, and latency in nand read and program-verify operations: A HiNAND array with a hierarchical-BL scheme configured to divide a large global bit line (GBL) capacitance into J number of small local bit line (LBL) capacitances for reducing bit line precharge voltage and discharge time to achieve faster Read and Program-Verify speed, lower power consumption, lower latency, and lower... Agent:

20140347930 - Non-volative electronic memory device with nand structure being monolithically integrated on semiconductor: A non-volatile electronic memory device is integrated on a semiconductor and is of the Flash EEPROM type with a NAND architecture including at least one memory matrix divided into physical sectors, intended as smallest erasable units, and organized in rows or word lines and columns or bit lines of memory... Agent:

20140347927 - Nonvolatile memory device having split ground selection line structures: A nonvolatile memory device comprises a plurality of vertical NAND flash memory cells arranged in a three dimensional (3D) structure, a first memory block disposed in the 3D structure and having memory cells selected by a first ground selection line and a second ground selection line, wherein the first and... Agent:

20140347932 - Memory with three transistor memory cell device: Memory, memory devices, and a method for a backup sequence are disclosed. In one such memory device, sense circuitry and page buffers are coupled between a three transistor memory cell device and a non-volatile memory device. Enable/disable gates enable selective access to the sense circuitry and page buffers by either... Agent: Micron Technology, Inc.

20140347931 - Writing into an eeprom on an i2c bus: An EEPROM circuit includes a data reception register and a column decoder. A buffer memory having a size corresponding to the size of a data page is included between the data reception register and the column decoder.... Agent: Stmicroelectronics (rousset) Sas

20140347934 - Memory devices having select gates with p type bodies, memory strings having separate source lines and methods: Memory devices and methods of operating memory devices are shown. Configurations described include a memory cell string having an elongated n type body region and having select gates with p type bodies. Configurations and methods shown can provide a reliable bias to a body region for memory operations such as... Agent:

20140347935 - Method of providing an operating voltage in a memory device and a memory controller for the memory device: A method of providing an operating voltage in a memory device includes applying a read voltage to a selected word line while applying a first pass voltage to at least one unselected word line among word lines adjacent to the selected word line; and while applying a second pass voltage... Agent:

20140347933 - Nor-based bcam/tcam cell and array with nand scalability: This invention discloses a 2T-string NOR-based CAM logic cell comprising two physical NAND cells connected in series with two horizontal WLs and one vertical BL and one vertical SL. Additionally, a sector of NOR-based CAM logic cell array is configured with N vertical cell strings each including M 2T-string NOR-based... Agent: Aplus Flash Technology, Inc.

20140347936 - Recovery of interfacial defects in memory cells: A group of non-volatile, solid state memory cells are transferred from an active list that includes memory cells accessible to a host to a temporary list that includes memory cells temporarily inaccessible to the host. The memory cells included in the temporary list are maintained at a temperature that is... Agent: Seagate Technology LLC

20140347937 - Semiconductor device and method of operating the same: A semiconductor device includes a memory block coupled to word lines and configured to a memory cell including a floating gate, an inter-poly dielectric and a control gate and a peripheral circuit configured to perform an erase loop operation, a program loop operation an electron injection operation of the memory... Agent: Sk Hynix Inc.

20140347938 - Semiconductor apparatus: A semiconductor apparatus includes an input buffer configured to buffer data inputted through a data input/output pad; a data input control unit configured to transfer an output of the input buffer to a data input/output line in response to a write clock; a test loop control unit configured to output... Agent: Sk Hynix Inc.

20140347940 - Semiconductor devices and semiconductor systems including the same: Semiconductor devices are provided. The semiconductor device includes a control signal generator and a first data input unit. The control signal generator generates an inverted control signal including a first bit and a second bit using a decoded signal in response to a test enable signal. The first data input... Agent: Sk Hynix Inc.

20140347939 - Semiconductor devices including pipe latch units and system including the same: The semiconductor device includes a pre-signal generator and a data output portion. The pre-signal generator generates a pre-input control signal and a pre-output control signal. The pre-signal generator also generates a pre-latch pulse signal by detecting when the pre-input control signal and the pre-output control signal are generated. The data... Agent: Sk Hynix Inc.

20140347941 - Low latency synchronization scheme for mesochronous ddr system: In one embodiment, a memory interface comprises a cleanup phase-locked loop (PLL) configured to receive a reference clock signal, and to generate a clean clock signal based on the reference clock signal. The memory interface also comprises a synchronization circuit configured to receive data, a data clock signal, and the... Agent: Qualcomm Incorporated

20140347942 - Nonvolatile memory device, read method for nonvolatile memory device, and memory system incorporating nonvolatile memory device: A method of performing a read operation on nonvolatile memory device comprises receiving a read command, receiving addresses, detecting a transition of a read enable signal, generating a strobe signal based on the transition of the read enable signal, reading data corresponding to the received addresses, and outputting the read... Agent:

20140347943 - Semiconductor package including stacked chips and method of fabricating the same: A semiconductor package includes first and second slave chips stacked vertically; and a master chip connected to the first and second slave chips, each of the slave chips including, a plurality of memory blocks, and a redundancy block, and the master chip including, a fuse block configured to repair a... Agent: Samsung Electronics Co., Ltd.

20140347944 - Methods and apparatuses for stacked device testing: Various embodiments include apparatus, systems, and methods having multiple dies arranged in a stack in which the dies or a logic chip in communication with the dies stores a flag for indicating whether a threshold number of cells of the dies have failed during test operations.... Agent: Micron Technology, Inc.

20140347945 - Apparatuses including a memory array with separate global read and write lines and/or sense amplifier region column select line and related methods: Apparatuses and methods related to memory arrays with separate global read and write lines and/or sense amplifier region column select lines are disclosed. An example apparatus includes first and second memory sections, and further includes a sense amplifier region. A memory section includes a word line extending in a first... Agent: Micron Technology, Inc.

20140347947 - Apparatus and methods to provide power management for memory devices: An apparatus, such as a nonvolatile solid-state memory device, may, in some implementations, include access line bias circuitry to set a bias level associated with a deselected access line(s) of a memory core in response to mode information. In one approach, access line bias circuitry may use linear down regulation... Agent:

20140347946 - Voltage regulator:

20140347948 - Apparatuses and methods for unit identification in a master/slave memory stack: Apparatuses and methods including a plurality of memory units are disclosed. An example apparatus includes a plurality of memory units. Each of the plurality of memory units include a master/slave identification (ID) node coupled to a first voltage source node via a resistive element. Each of the plurality of memory... Agent:

20140347949 - Block selection circuit and semiconductor device having the same: A block selection circuit and a semiconductor device having the same may include a row decoder which includes a high voltage generating circuit configured to output a block selection voltage in response to upper addresses, switching circuits configured to receive the block selection voltage and aprecharge high voltage, and forward... Agent: Sk Hynix Inc.

20140347950 - Memory systems and methods for dividing physical memory locations into temporal memory locations: Described are memory modules that support dynamic point-to-point extensibility using fixed-width memory die. The memory modules include data-width translators that allow the modules to vary the effective width of their external memory interfaces without varying the width of the internal memory interfaces extending between the translators and associated fixed-width dies.... Agent:

20140347951 - Semiconductor memory device having sub word line driver and driving method thereof: A semiconductor memory device may include a memory cell array, a plurality of first sub word line drivers, and a plurality of second sub word line drivers. The memory cell array may comprise a plurality of sub cell arrays, a plurality of first word lines and a plurality of second... Agent:

  
11/20/2014 > 28 patent applications in 23 patent subcategories.

20140340951 - Applications for inter-word-line programming: A method includes, in an array of analog memory cells that are arranged in rows associated with respective word lines, reading a first group of the memory cells in a selected word line, including one or more memory cells that store a status of at least one word line in... Agent:

20140340952 - Apparatuses having a ferroelectric field-effect transistor memory array and related method: An apparatus comprises field-effect transistor (FET) structures stacked horizontally and vertically in a three-dimensional memory array architecture, gates extending vertically and spaced horizontally between the plurality of FET structures, and a ferroelectric material separating the FET structures and the gates. Individual ferroelectric FETs (FeFETs) are formed at intersections of the... Agent: Micron Technology, Inc.

20140340953 - Semiconductor device: An object of the present invention is to provide a semiconductor device combining transistors integrating on a same substrate transistors including an oxide semiconductor in their channel formation region and transistors including non-oxide semiconductor in their channel formation region. An application of the present invention is to realize substantially non-volatile... Agent:

20140340954 - Low-pin-count non-volatile memory interface with soft programming capability: A low-pin-count non-volatile (NVM) memory with no more than two control signals that can at least program NVM cells, load data to be programmed into output registers, or read the NVM cells. At least one of the NVM cells has at least one NVM element coupled to at least one... Agent:

20140340955 - One time programable memory cell and method for programing and reading a memory array comprising the same: The present invention provides a one time programmable (OTP) memory cell including a select gate transistor, a following gate transistor, and an antifuse varactor. The select gate transistor has a first gate terminal, a first drain terminal, a first source terminal, and two first source/drain extension areas respectively coupled to... Agent: Ememory Technology Inc.

20140340956 - Memory device and method of controlling memory device: According to one embodiment, a memory device includes a semiconductor layer connected between a first conductive line and one end of a third conductive line, resistance change elements connected between second conductive lines and the third conductive line respectively, a select FET having a select gate electrode, and using the... Agent: Kabushiki Kaisha Toshiba

20140340960 - Memory device: A memory device includes: a memory element which includes three or more resistance states by using plural magneto-resistive elements each having a first resistance state or a second resistance state; and a comparison and determination circuit which compares the resistance states of the memory element before and after one first... Agent: Fujitsu Limited

20140340957 - Non-volatile latch using spin-transfer torque memory device: Described is an apparatus of a non-volatile logic (NVL), the apparatus comprises: a sensing circuit to sense differential resistance; a first magnetic-tunneling-junction (MTJ) device coupled to the sensing circuit; a second MTJ device coupled to the sensing circuit, the first and second MTJ devices operable to provide differential resistance; and... Agent:

20140340959 - Nonvolatile memory device and data processing method thereof: A nonvolatile memory device is provided comprising a memory cell array including first and second memory cells. Data is stored at the first memory cell. The device further comprises an access control circuit configured to read the data stored at the first memory cell and to subsequently perform a data... Agent:

20140340958 - Reliability of magnetoresistive random-access memory: A memory cell comprises a dual-gate fin field effect transistor (FinFET) and first and second serially connected magnetic tunnel junction (MTJ) devices for improving reliability of memory operations. The FinFET represents an access transistor and includes a first gate and a second gate. The second gate is configured to be... Agent:

20140340961 - Tunnel magnetoresistive effect element and random access memory using same: Provided is a tunnel magnetoresistive effect element such that a high TMR ratio and a low write current can be realized, and the thermal stability factor (E/kBT) of a recording layer and a pinned layer is increased while an increase in resistance of the element as a whole is suppressed,... Agent: Tohoku University

20140340962 - Thyristor memory and methods of operation: Apparatuses and methods can include write schemes for a thyristor memory cell in which an access pulse applied to the gate of the thyristor memory cell is adjusted relative to the data pulse to write data into the thyristor memory cell. Some of the write schemes may substantially reduce or... Agent:

20140340963 - Apparatus and methods including source gates: Apparatus and methods are disclosed, such as an apparatus that includes a string of charge storage devices associated with a pillar (e.g., of semiconductor material), a source gate device, and a source select device coupled between the source gate device and the string. Additional apparatus and methods are described.... Agent:

20140340964 - Nonvolatile semiconductor memory device: According to one embodiment, a nonvolatile semiconductor memory device includes a memory cell array and a control circuit configured to repeat a program operation and a verify operation. The control circuit performs a first verify operation of sensing whether threshold voltages of selected memory cells are greater than or equal... Agent:

20140340965 - Selective re-programming of analog memory cells: A method for data storage includes defining, in a memory that includes multiple analog memory cells, an erased state, a set of non-erased programming states and a partial subset of the non-erased programming states. Data is initially stored in a first group of the analog memory cells by programming each... Agent:

20140340966 - Semiconductor memory device and method of operating the same: A semiconductor memory device includes a memory string and a peripheral circuit. The memory string has a pipe cell, a plurality of memory cells, and at least one channel layer having a three-dimensional U-shaped structure. The peripheral circuit is configured to perform an erase operation on the pipe cell. A... Agent: Sk Hynix Inc.

20140340967 - Split gate nand flash memory structure and array, method of programming, erasing and reading thereof, and method of manufacturing: A split gate NAND flash memory structure is formed on a semiconductor substrate of a first conductivity type. The NAND structure comprises a first region of a second conductivity type in the substrate with a second region of the second conductivity type in the substrate, spaced apart from the first... Agent:

20140340972 - Method of maintaining the state of semiconductor memory having electrically floating body transistor: Methods of maintaining a state of a memory cell without interrupting access to the memory cell are provided, including applying a back bias to the cell to offset charge leakage out of a floating body of the cell, wherein a charge level of the floating body indicates a state of... Agent:

20140340968 - Semiconductor integrated circuit: A semiconductor integrated circuit includes: a latch unit configured to latch data in response to an input control signal; and a latch control unit configured to determine whether or not any one of first and second memory areas is successively accessed, and adjust timing of the input control signal.... Agent: Sk Hynix Inc.

20140340969 - Semiconductor apparatus: A semiconductor apparatus includes: a command control unit configured to generate a read strobe signal, a write strobe signal, a read command, and a write command; a clock enable signal generation unit configured to generate a read clock enable signal in response to the read strobe signal and generate a... Agent: Sk Hynix Inc.

20140340970 - Memory with dynamic feedback control circuit: A memory comprising a word line having a word line voltage, a charge pump coupled to the word line, and a dynamic feedback control circuit coupled to the charge pump. The dynamic feedback control circuit is configured to boost the word line voltage to a predetermined voltage value greater than... Agent:

20140340971 - Semiconductor circuit and leakage current test system: A semiconductor circuit includes a test control unit configured to generate a driving activation signal and a sensing activation signal in response to a command and an address; a pad; a driver configured to drive the pad to a predetermined level in response to activation of the driving activation signal;... Agent: Sk Hynix Inc.

20140340973 - Semiconductor device having pda function: A method for writing a mode register in a semiconductor device, the method includes receiving a mode register command and a mode signal, generating a first mode register setting signal, delaying the first mode register setting signal in a first latency shifter to provide a second mode register setting signal,... Agent:

20140340974 - Apparatus and method for writing data into storage of electronic device: An electronic device includes a storage and a processor. When the processor performs a data transmission process performed by the processor to transmit data to the storage, a time period duration of writing data into the storage is timed. An Acknowledge (ACK) signal indicating the data is successfully written into... Agent: Hon Hai Precision Industry Co., Ltd.

20140340975 - Semiconductor integrated circuit and method of testing semiconductor integrated circuit: A semiconductor integrated circuit is provided with: a memory under test; a test-result-storage memory; a test-data generation part for generating in a sequential manner a test address signal and test data for supplying to the memory under test; and a control circuit. The control circuit includes a delay circuit, which,... Agent:

20140340976 - Information processing system including semiconductor device having self-refresh mode: A method for controlling termination impedance of a data terminal in a dynamic random access memory device includes receiving a mode register set command to set an operation mode to a first mode, setting the operation mode in a mode register to the first mode, receiving a self-refresh entry command,... Agent:

20140340977 - Low power transient voltage collapse apparatus and method for a memory cell: Described is an apparatus for memory write assist which consumes low power during write assist operation. The apparatus comprises: a power supply node; a device operable to adjust voltage on the power supply node; and a feedback unit coupled to the power supply node, the feedback unit to control the... Agent:

20140340978 - Access methods and circuits for memory devices having multiple banks: A method can include storing a plurality of addresses within one cycle of a timing clock, each address corresponding to a storage location of a memory device; and following the one cycle, accessing a plurality of banks of the memory device in response to the stored addresses corresponding to different... Agent: Cypress Semiconductor Corporation

  
11/13/2014 > 28 patent applications in 20 patent subcategories.

20140334216 - General structure for computational random access memory (cram): A cell array includes a logic connection line, a plurality of bit selection lines, and a plurality of cells. Each cell includes a memory element connected to a respective bit selection line and a logic switching element that selectively connects the memory element to the logic connection line. When logic... Agent: Regents Of The University Of Minnesota

20140334217 - Nonvolatile semiconductor memory device: A nonvolatile semiconductor memory device includes: a memory cell array having a plurality of memory cells arranged in a matrix; a reference bit line; a reference source line; at least one reference cell including first and second transistors serially connected between these lines; a reference word line connected to the... Agent:

20140334218 - Semiconductor device: Provided is a memory device in which memory capacity per unit area is increased without making the manufacturing process complicated. The memory device includes a plurality of memory cells, a plurality of word lines, and a plurality of bit lines. Each of the plurality of memory cells includes a switching... Agent:

20140334219 - Apparatuses and methods including memory with top and bottom data lines: Some embodiments include apparatuses and methods having a first set of data lines, a second set of data lines, and memory cells located in different levels of the apparatus. In at least one of such embodiments, the memory cells can be arranged in memory cell strings between the first and... Agent:

20140334220 - Embedded non-volatile memory circuit for implementing logic functions across periods of power disruption: A circuit having an autonomous ferroelectric memory latch (AML) is disclosed. An AML characterized by an AML input, an AML output, a first AML power contact, a second AML power contact and an AML state, and a first switch in series with one of the AML input or the AML... Agent: Radiant Technologies, Inc.

20140334223 - Apparatuses and methods for determining stability of a memory cell: Examples described include apparatuses and methods for determining stability of memory cells. Resistance variable memory cells may be used. Once a memory cell is placed in a low or high resistance state responsive to set or reset pulses, the stability of the state may be determined, such as by providing... Agent:

20140334222 - Low read current architecture for memory: A low read current architecture for memory. Bit lines of a cross point memory array are allowed to be charged by a selected word line until a minimum voltage differential between a memory state and a reference level is assured.... Agent: Unity Semiconductor Corporation

20140334221 - Resistance change memory: According to one embodiment, a memory includes memory cells between first conductive lines and second conductive lines. A control circuit is configured to apply a first potential to a first end of a selected first conductive line connected to the selected memory cell among the first conductive lines and first... Agent: Kabushiki Kaisha Toshiba

20140334225 - Prioritizing refreshes in a memory device: A method and apparatus for refreshing a row of a memory device prior to a scheduled refresh. A memory array may include a plurality of memory cells. The memory array may be configured to be refreshed at a first refresh time interval. The memory device may also include an intermediate... Agent: International Business Machines Corporation

20140334224 - Reference voltage modification in a memory device: A method and apparatus for modifying a reference voltage between refreshes in a memory device are disclosed. The memory array may include a plurality of memory cells. The memory device may also include a sense amplifier. The sense amplifier may be configured to read data from the plurality of memory... Agent: International Business Machines Corporation

20140334226 - Circuit for reverse biasing inverters for reducing the power consumption of an sram memory: CMOS integrated circuits with very low consumption when idle, and notably the SRAM volatile memories, are provided. The inverters of the circuit are made up of an NMOS transistor and a PMOS transistor. A bias circuit applies a first rear bias voltage NBIAS to the wells of the NMOS transistors... Agent:

20140334227 - Memory circuit, method of driving the same, nonvolatile storage device using the same, and liquid crystal display device: The present invention provides a memory circuit including a memory element to which writing can be performed with a small current and a low voltage, i.e., low power consumption, and provides a non-volatile storage device that can easily reduce a chip size by using this memory circuit. A memory element... Agent:

20140334228 - Linearly related threshold voltage offsets: Threshold voltage offsets for threshold voltages are determined. The threshold voltage offsets may be linearly related by a non-zero slope. The threshold voltages are shifted using their respective threshold voltage offsets. The threshold voltages that are shifted by their respective threshold voltage offsets are used to read data from multi-level... Agent: Seagate Technology LLC

20140334229 - Semiconductor device with floating gate and electrically floating body: Techniques for providing floating body memory devices are disclosed. In one particular exemplary embodiment, the techniques may be realized as a semiconductor device comprising a floating gate, a control gate disposed over the floating gate, a body region that is electrically floating, wherein the body region is configured so that... Agent: Micron Technology, Inc.

20140334230 - Semiconductor memory device and system having the same: A semiconductor memory device includes a first dummy transistor coupled to a bit line, a first select transistor formed where a first selection line surrounds a vertical channel layer, a second dummy transistor coupled to a common source line, a second select transistor formed where a second selection line surrounds... Agent: Sk Hynix Inc.

20140334231 - Semiconductor memory device and system having the same: A control circuit is configured to set a drain-side select transistor and a source-side select transistor connected to a selected memory string to non-conductive states. The control circuit is configured to apply a first voltage to a non-selected word line connected to a gate of a non-selected memory cell in... Agent: Kabushiki Kaisha Toshiba

20140334232 - 3d flash memory device having different dummy word lines and data storage devices including same: A three-dimensional (3D) flash memory includes a first dummy word line disposed between a ground select line and a lowermost main word line, and a second dummy word line of different word line configuration disposed between a string select line and an upper most main word line.... Agent:

20140334233 - Method of reading memory cells with different threshold voltages without variation of word line voltage and nonvolatile memory device using the same: A soft-decision read method of a nonvolatile memory device includes receiving a soft-decision read command, applying a read voltage to a selected word line, pre-charging bit lines respectively connected to selected memory cells of the selected word line, continuously sensing states of the selected memory cells. The pre-charged voltages of... Agent: Samsung Electronics Co., Ltd.

20140334234 - Semiconductor device including memory cell having charge accumulation layer: A semiconductor device includes MOS transistors, capacitor elements, a voltage generating circuit, a contact plug, and a memory cell. The MOS transistor and the capacitor element are formed on a first one of the element regions and a second one of the element regions, respectively. In the voltage generating circuit,... Agent: Kabushiki Kaisha Toshiba

20140334237 - Apparatuses, devices and methods for sensing a snapback event in a circuit: Example subject matter disclosed herein relates to apparatuses and/or devices, and/or various methods for use therein, in which an application of an electric potential to a circuit may be initiated and subsequently changed in response to a determination that a snapback event has occurred in a circuit. For example, a... Agent:

20140334235 - Memory macro configuration and method: A memory macro comprises a plurality of memory array segments, each having a predetermined number of data inputs and outputs. A segment decoder circuit is configured to: receive a first value indicating a number of memory partitions among which the memory array segments are to be divided, and output a... Agent: Taiwan Semiconductor Manufacturing Co., Ltd.

20140334236 - Low-power source-synchronous signaling: A method of operating a memory controller is disclosed. The method includes transmitting data signals to a memory device over each one of at least two parallel data links. A timing signal is sent to the memory device on a first dedicated link. The timing signal has a fixed phase... Agent:

20140334238 - Low power memory device: A method of operation within a memory device is disclosed. The method comprises receiving address information and corresponding enable information in association with a memory access request. The address information includes a row address that specifies a row of storage cells within a storage array of the memory device, and... Agent: Rambus Inc.

20140334239 - I/o circuit with phase mixer for slew rate control: An apparatus includes a terminal, a first plurality of driver lines, and a first phase mixer. The driver lines drive the terminal to a first logic state responsive to a first enable signal. The first phase mixer is coupled to a first one of the first plurality of driver lines.... Agent:

20140334240 - Semiconductor integrated circuit device: An output signal characteristic of a differential amplifier circuit is improved. When an input data signal becomes ‘Low’, current flowing through a first transistor will decrease and potential at a connection (a node) between a first resistor and a second resistor will increase. This potential is input (negatively fed back)... Agent: Renesas Electronics Corporation

20140334241 - Circuits, apparatuses, and methods for oscillators: Circuits, apparatuses, and methods are disclosed for oscillators. In one such example oscillator circuit, a plurality of delay stages are coupled in series. A variable delay circuit stage is coupled to the plurality of delay stages and is configured to delay a signal through the variable delay circuit stage by... Agent:

20140334242 - Semiconductor memory apparatus and method of operating using the same: A semiconductor memory apparatus includes a reset pad configured to receive and transfer an external reset signal and an external control signal; a first input buffer configured to buffer the external reset signal in response to a buffer control signal and output an internal reset signal; a second input buffer... Agent:

20140334243 - Write level training using dual frequencies in a double data-rate memory device interface: A write leveling calibration system and method for double data-rate dynamic random access memory includes performing write leveling at two different frequencies to determine to which of two successive rising clock cycle edges each data strobe signal would be aligned as a result of applying the write leveling delay determined... Agent: Avago Technologies GeneralIP(singapore) Pte. Ltd

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