Static information storage and retrieval inventions

20090262564 - Circuit wiring layout in semiconductor memory device and layout method: An improved circuit wiring layout provides smooth circuit wiring in a peripheral circuit region adjacent to a memory cell region of a semiconductor memory device, and eliminates a write-speed limiting factor. Forming a metal (instead of a metal silicided polysilicon) wiring layer to be connected to a gate layer, to... Agent: F. Chau & Associates, LLC

20090262563 - Memory device capable of one-time data writing and repeated data reproduction, and method and display apparatus for operating the memory device: Provided are a memory device where data may be recorded one time and/or reproduced repeatedly, and a method and display apparatus for operating the memory device. The memory device may include a program area having a plurality of memory cells and a spare area having a plurality of memory cells.... Agent: Harness, Dickey & Pierce, P.L.C

20090262565 - Method for programming nonvolatile memory device: Disclosed is a method for programming a nonvolatile memory device including one time programmable unit cells. The method for programming a nonvolatile memory device including one time programmable (OTP) unit cells, the method comprising applying a pulse type program voltage having a plurality of cycles. The present invention relates to... Agent: Morgan Lewis & Bockius LLP

20090262566 - Mask programmable anti-fuse architecture: A memory array having both mask programmable and one-time programmable memory cells connected to the wordlines and the bitlines. All memory cells of the memory array are configured as one-time programmable memory cells. Any number of these one-time programmable memory cells are convertible into mask programmable memory cells through mask... Agent: Borden Ladner Gervais LLP Anne Kinsman

20090262567 - Nonvolatile memory device: A nonvolatile memory device including one-time programmable (OTP) unit cell is provided. The nonvolatile memory device includes: a unit cell; a detecting unit configured to detect data from the unit cell; and a read voltage varying unit configured to vary an input voltage and supply a varied read voltage to... Agent: Morgan Lewis & Bockius LLP

20090262568 - Semiconductor memory device: A resistance variable memory reduces the nonuniformity of resistance values after programming, so that a rewrite operation can be performed on a memory cell at high speed. A reference resistor is connected in series with the resistance variable memory cell, and a sensor amplifier detects whether the potential at an... Agent: Miles & Stockbridge PC

20090262569 - Semiconductor memory device with stacked memory cell structure: A semiconductor device including: a first memory cell including a non-volatile first variable resistance element that stores data by varying a resistance value and a selection transistor that selects the first variable resistance element; a first memory layer provided with more than one such first memory cell arranged in a... Agent: Spansion LLC C/o Murabito , Hao & Barnes LLP

20090262570 - Giant magnetoresistance (gmr) memory device: The present magnetic memory device includes a pinned ferromagnetic layer, and a switchable ferromagnetic layer, the memory device being programmable to have a first programmed state wherein the resistance of the device is at a first level, a second programmed state wherein the resistance of the device is at a... Agent: Hamilton & Terrile, LLP - Amd

20090262571 - Magnetic random access memory and operating method of magnetic random access memory: A magnetic random access memory includes: a first and second wirings, a plurality of third wirings, a plurality of memory cells and a terminating unit. The first and second wirings extend in a Y direction. The plurality of third wirings extends in an X direction. The memory cell is provided... Agent: Sughrue Mion, PLLC

20090262572 - Multilayer storage class memory using externally heated phase change material: A multi-layer, phase change material (PCM) memory apparatus includes a plurality of semiconductor layers sequentially formed over a base substrate, wherein each layer comprises an array of memory cells formed therein, each memory cell further including a PCM element, a first diode serving as a heater diode in thermal proximity... Agent: Cantor Colburn LLP-ibm Yorktown

20090262573 - Multilevel nonvolatile memory device using variable resistance: A multilevel nonvolatile memory device using a resistance material is provided. The multilevel nonvolatile memory device includes at least one multilevel memory cell and a read circuit. The at least one multilevel memory cell has a level of resistance that varies according to data stored therein. The read circuit first... Agent: Volentine & Whitt PLLC

20090262574 - Semiconductor device: A highly reliable large capacity phase change memory module is realized. A semiconductor device according to the present invention includes a memory array having a structure in which a storage layer using a chalcogenide material and a memory cell constituted of a diode are stacked, and an initialization condition and... Agent: Miles & Stockbridge PC

20090262575 - Thin film magnetic memory device capable of conducting stable data read and write operations: A tunnel magnetic resistive element forming a magnetic memory cell includes a fixed magnetic layer having a fixed magnetic field of a fixed direction, a free magnetic layer magnetized by an applied magnetic field, and a tunnel barrier that is an insulator film provided between the fixed and free magnetic... Agent: Mcdermott Will & Emery LLP

20090262577 - Multi-level cell flash memory: Most drivers of flash memories used for embedded systems are often designed to use power from batteries, but not from a commercial power supply, and therefore are required to be protected against power failures. In addition, if a power failure occurs in the middle of programming a cell, the driver... Agent: Ditthavong Mori & Steiner, P.C.

20090262578 - Use of data latches in cache operations of non-volatile memories: Methods and circuitry are present for improving performance in non-volatile memory devices by allowing the inter-phase pipelining of operations with the same memory, allowing, for example, a read operation to be interleaved between the pulse and verify phases of a write operation. In the exemplary embodiment, the two operations share... Agent: Davis Wright Tremaine LLP - Sandisk Corporation

20090262580 - Flash memory device adapted to prevent read failures due to dummy strings: In a NAND flash memory device, a dummy NAND string is arranged between a plurality of normal NAND strings. A dummy bit line connected to the dummy NAND string is formed and/or controlled such that when program voltages are applied to the normal NAND strings, memory cells within the dummy... Agent: Volentine & Whitt PLLC

20090262579 - Non-volatile semiconductor memory device and method of writing data in non-volatile semiconductor memory devices: The device has a data write mode to boost a first boost channel region that contains a non-write selected memory cell and non-selected memory cells located closer to the first selection gate transistor, and a second boost channel region that contains non-selected memory cells located closer to the second selection... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, L.L.P.

20090262581 - Non volatile memory: An electrically programmable and erasable non-volatile semiconductor memory such as a flash memory is designed into a configuration in which, when a cutoff of the power supply occurs in the course of a write or erase operation carried out on a memory cell employed in the non-volatile semiconductor memory, the... Agent: Miles & Stockbridge PC

20090262582 - Method of programming flash memory device: Flash memory devices include a memory array having a plurality of NAND strings of EEPROM cells therein. A word line driver is provided to improve programming efficiency. The word line driver is electrically coupled to the memory array by a plurality of word lines. The word line driver includes a... Agent: Myers Bigel Sibley & Sajovec

20090262576 - Flash memory device and operating method of flash memory device: Disclosed is an operating method of a flash memory device, which includes normal memory cells and dummy memory cells. The operating method includes programming the normal memory cells and programming the dummy memory cells. A dummy pass voltage used for programming the dummy memory cells is different from a normal... Agent: Volentine & Whitt PLLC

20090262583 - Floating gate memory device with interpoly charge trapping structure: A charge trapping floating gate is described with asymmetric tunneling barriers. The memory cell includes a source region and a drain region separated by a channel region. A first tunneling barrier structure is disposed above the channel region. A floating gate is disposed above the first tunneling barrier structure covering... Agent: Macronix C/o Haynes Beffel & Wolfeld LLP

20090262584 - Nonvolatile memory cell and data latch incorporating nonvolatile memory cell: A nonvolatile memory cell, comprising: a first NMOS transistor having a floating gate; a second NMOS transistor and a third NMOS transistor connected to a drain side and a source side of the first NMOS transistor; and a first PMOS transistor and a second PMOS transistor each having the floating... Agent: The Webb Law Firm, P.C.

20090262589 - Semiconductor memory device and method for operating the same: A semiconductor memory device and a method for operating the same can improve a refresh characteristic of the semiconductor memory device by physically writing only logic low data in memory cells, irrespective of logic level of input data, either high or low. The semiconductor memory device includes a positive word... Agent: Mannava & Kang, P.C.

20090262585 - Input buffer and method with ac positive feedback, and a memory device and computer system using same: An input buffer having a comparator that receives an input signal, a reference signal and a positive feedback. The comparator compares the input signal relative to the reference signal and generates an output signal transitioning between a first logic state and a second logic state responsive to the magnitude of... Agent: Dorsey & Whitney LLP Intellectual Property Department

20090262586 - Semiconductor memory device voltage generating circuit for avoiding leakage currents of parasitic diodes: A voltage generating circuit for semiconductor memory devices for use in avoiding the occurrence of leakage currents associated with parasitic diodes is presented. The circuit controls and stabilizes the generation of a fedback negative voltage to prevent parasitic diode malfunctions by a in a wordline driver. The voltage generating circuit... Agent: Ladas & Parry LLP

20090262587 - Semiconductor memory device: A semiconductor memory device includes a plurality of memory cell array blocks connected to word lines, source lines, and bit lines, each memory cell array including memory cells each having a transistor with a floating body, a reference voltage generator configured to have a reference memory cell and generate a... Agent: Lee & Morse, P.C.

20090262588 - Power savings with a level-shifting boundary isolation flip-flop (lsiff) and a clock controlled data retention scheme: An apparatus for providing active mode power reduction for circuits having data retention includes a master slave flip flop (MSFF) for latching a data input. An output level shifter (OLS), coupled to the MSFF, retains the data input in response to the MSFF being operable in an active power saving... Agent: Texas Instruments Incorporated

20090262590 - Semiconductor memory device: A semiconductor memory device has a command decoder responsive to a plurality of commands to set the semiconductor memory device to a normal mode, for generating control signals corresponding to the commands, respectively, and a row address prelatch circuit for holding a row address except for a bank address input... Agent: Katten Muchin Rosenman LLP

20090262591 - Nand system with a data write frequency greater than a command-and-address-load frequency: The invention provides methods and apparatus. A NAND flash memory device receives command and address signals at a first frequency and a data signal at a second frequency that is greater than the first frequency.... Agent: Leffert Jay & Polglaze, P.A.

20090262592 - Method and apparatus for synchronization of row and column access operations: A circuit for synchronizing row and column access operations in a semiconductor memory having an array of bit line pairs, word lines, memory cells, sense amplifiers, and a sense amplifier power supply circuit for powering the sense amplifiers, the circuit comprising, a first delay circuit for delaying a word line... Agent: Borden Ladner Gervais LLP Anne Kinsman

20090262593 - Circuit and method for retrieving data stored in semiconductor memory cells: A circuit comprises at least one memory cell adapted to store data in terms of values of an electrical characteristic thereof, which exhibits a variability with temperature according to a first variation law; a voltage generator is provided for generating a voltage to be supplied to the at least one... Agent: Gerbera/bstz Blakely Sokoloff Taylor & Zafman LLP

20090262594 - Memory cells with power switch circuit for improved low voltage operation: Static random access memory (SRAM) cells and methods of operation are provided which may be used to provide improved writeability and stability to support low voltage operation of memory devices. For example, in one implementation, by temporarily interrupting the connection between portions of an SRAM cell and a power source... Agent: Osha Liang L.L.P./sun

20090262596 - Address decoder and/or access line driver and method for memory devices: Address decoders and access line drivers are provided. One such row decoder and access line driver receives power supply voltages in a manner that prevents CHC damage and avoids GIDL currents in transistors in the decoder and driver. The row decoder and a latch in the driver are powered by... Agent: Edward W. Bulchis, Esq. Dorsey & Whitney LLP

20090262595 - Method and apparatus for operating maskable memory cells: A plurality of masked memory cells organized in at least two groups, each group using an individual mask signal, is operated by providing a logically valid mask signal only for a selected group comprising the memory cell to be accessed while a logically invalid mask signal are used for all... Agent: Dickstein Shapiro LLP

20090257262 - Dram and memory array: A dynamic random access memory (DRAM) includes a substrate, a plurality of bit lines, a plurality of word lines, a plurality of recess channels, a plurality of conductive plugs and a plurality of trench capacitors. In the DRAM, the bit lines are disposed on the substrate in a first direction,... Agent: Jianq Chyun Intellectual Property Office

20090257263 - Method and apparatus for computer memory: A method and apparatus for forming computer memory 10 including RAM, ROM, Stacks and other registers. The memory array 10 includes a number of individual memory cells 40, 42, 44, 46 connected to each other by word lines 18, 20 and bit lines 30, 32. Memory cells 40, 42, 44,... Agent: Henneman & Associates, PLC

20090257270 - Damascene integration methods for graphitic films in three-dimensional memories and memories formed therefrom: In some aspects, a microelectronic structure is provided that includes (1) a first conducting layer; (2) a first dielectric layer formed above the first conducting layer and having a feature that exposes a portion of the first conducting layer; (3) a graphitic carbon film disposed on a sidewall of the... Agent: Dugan & Dugan, PC

20090257269 - Low-complexity electronic circuits and methods of forming the same: An electronic circuit such as a latch or a sequencer includes a plurality of transistors, all of the transistors being either NMOS transistors or PMOS transistors, and dissipates less than or approximately the same amount of power as an equivalent CMOS circuit.... Agent: Goodwin Procter LLP Patent Administrator

20090257264 - Memory and method of evaluating a memory state of a resistive memory cell: An integrated circuit comprises a first signal line, a second signal line and a resistive memory cell. The resistive memory cell is actively connectable to the first signal line. The integrated circuit further comprises a coupling device configured to generate a difference of potential between the first and second signal... Agent: Patterson & Sheridan, LLP Gero Mcclellan / Qimonda

20090257265 - Multilevel nonvolatile memory device containing a carbon storage material and methods of making and using same: A nonvolatile memory cell includes a steering element located in series with a storage element. The storage element includes a carbon material and the memory cell includes a rewritable cell having multiple memory levels.... Agent: Sandisk Corporation C/o Foley & Lardner LLP

20090257266 - Multilevel nonvolatile memory device containing a carbon storage material and methods of making and using same: A method of programming a nonvolatile memory cell includes applying at least one initialization pulse having a duration of at least 1 ms, followed by applying plural programming pulses having a duration of less than 1 ms. The cell includes a steering element located in series with a storage element,... Agent: Sandisk Corporation C/o Foley & Lardner LLP

20090257267 - Non-volatile multi-level re-writable memory cell incorporating a diode in series with multiple resistors and method for writing same: A very dense cross-point memory array of multi-level read/write two-terminal memory cells, and methods for its programming, are described. Multiple states are achieved using two or more films that each have bi-stable resistivity states, rather than “tuning” the resistance of a single resistive element. An exemplary memory cell includes a... Agent: Zagorin O'brien Graham LLP (023)

20090257271 - Resistance change element and method of manufacturing the same: In a resistance change memory (ReRAM) storing data by utilizing change in resistance of a resistance change element, a lower electrode (ground-side electrode) of the resistance change element is formed of a transition metal such as Ni, and an upper electrode (positive polarity-side electrode) is configured of a noble metal... Agent: Westerman, Hattori, Daniels & Adrian, LLP

20090257268 - Semiconductor device having single-ended sensing amplifier: A sense amplifier in a semiconductor storage device includes a memory cell for storing information on the basis of the size of the resistance value between a signal input/output terminal and a power supply terminal, the semiconductor storage device having a structure in which the bit line capacitance during signal... Agent: Mcginn Intellectual Property Law Group, PLLC

20090257273 - 2t sram cell structure: A SRAM cell structure includes a first N type switch, a second N type switch, a first storage node, and a second storage node. The first N type switch has a control terminal connected to a word line and a first terminal connected to a bit line. The second N... Agent: Wpat, PC

20090257272 - Reduced size charge pump for dram system: A memory system includes: a memory array, comprising a plurality of memory banks, respectively enabled by a plurality of bank enable signals; a bank selector circuit, for generating the plurality of bank enable signals; a plurality of charge pump components, coupled between the plurality of memory banks and the bank... Agent: North America Intellectual Property Corporation

20090257274 - Semiconductor memory device: A semiconductor memory device includes n resistance change elements which are arranged in one cell, have a low-resistance state and a high resistance state, are connected in series or parallel, have different resistance values in the same resistance state, and change between the low-resistance state and the high-resistance state under... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, L.L.P.

20090257275 - Seasoning phase change memories: A seasoned phase change memory has been subjected to a longer pulse to adjust resistance levels prior to use of the phase change memory.... Agent: Trop, Pruner & Hu, P.C.

20090257278 - Flash memory device having shared row decoder: A flash memory device includes at least two mats and a row decoder shared by the mats. Each mat includes multiple word lines, bit lines, and blocks that share the bit lines. The row decoder includes a block decoder that generates a block selection signal for selecting a block, a... Agent: Volentine & Whitt PLLC

20090257279 - Memory device operation: Non-volatile memory devices utilizing a modified NAND architecture where ends of the NAND string of memory cells are selectively coupled to different bit lines may facilitate increased memory densities, reduced fabrication steps and faster read operations when compared to traditional NAND memory array architectures. Programming and erasing of the memory... Agent: Leffert Jay & Polglaze, P.A. Attn: Thomas W. Leffert

20090257281 - Method of programming a flash memory device using self boosting: A method of programming a flash memory device controls a channel boosting level to ensure device properties. The flash memory device is programmed in an Incremental Step Pulse Program (ISPP) manner by applying a program voltage to a selected memory cell and a pass voltage to unselected memory cells. The... Agent: Townsend And Townsend And Crew, LLP

20090257280 - Nand flash memory device and method of operating same: An flash memory device includes a block of NAND cell units, each NAND cell unit in the block includes n memory cell transistors MC controlled by a plurality of n wordlines, and is connected in series between a string selection transistor SST connected to a bitline and a ground selection... Agent: F. Chau & Associates, LLC

20090257282 - Non-volatile storage system with initial programming voltage based on trial: A trial programming process is performed for a first set of one or more non-volatile storage elements to test usage of the non-volatile storage system. Based on this trial programming, a programming signal is calibrated by adjusting its initial magnitude. The calibrated programming signal is then used to program a... Agent: Vierra Magen/sandisk Corporation

20090257277 - Flash memory including reduced swing amplifiers: For realizing low power and high speed flash memory, reduced swing amplifiers are used for reading, such that a first reduced swing amplifier serves as a local sense amp for reading a memory cell through a short local bit line, a second reduced swing amplifier serves as a segment sense... Agent: Juhan Kim

20090257276 - Nonvolatile analog memory: A nonvolatile analog memory has a floating gate point. The nonvolatile analog memory includes a first current source, a second current source, and a current adjuster. The first current source generates a first current, and the second current source generates a second current. The current adjuster turns on or turns... Agent: Jianq Chyun Intellectual Property Office

20090257283 - Method for deleting data from nand type nonvolatile memory: To provide a method of releasing charges which have been injected into charge accumulating layers of nonvolatile memory elements without using a substrate terminal such as a p well or an n well, as a method for deleting data from a NAND-type nonvolatile memory. In the method for deleting data... Agent: Eric Robinson

20090257284 - Method and apparatus for improving storage performance using a background erase: Disclosed are an apparatus, method, and computer readable medium configured for performing a background erase in a memory device. Included is the act of receiving at least one erase command and at least one erasable block address for the memory device. Also included is the act of asserting a background-process-busy... Agent: Trask Britt, P.C./ Micron Technology

20090257286 - Apparatus and method for outputting data in semiconductor integrated circuit: An apparatus for outputting data in a semiconductor integrated circuit includes a clock generation block configured to activate a first clock signal for outputting a data signal and a second clock signal for outputting a data strobe signal based on a predetermined timing, and a data output block configured to... Agent: Baker & Mckenzie LLP Patent Department

20090257285 - Semiconductor memory apparatus: A semiconductor memory apparatus includes an input buffering block configured to buffer an input signal transmitted from an input pin, a latch block configured to latch the input signal buffered by the input buffering block, a defect discriminating block configured to discriminate whether or not the input signal latched by... Agent: Baker & Mckenzie LLP Patent Department

20090257288 - Apparatus and method for increasing data line noise tolerance: Circuits and methods for improving noise tolerance in memories are disclosed such as those that include biasing a data line above a normal threshold voltage, either by providing a higher data line charge voltage with a voltage source, or by providing a higher data line charge voltage with a current... Agent: Leffert Jay & Polglaze, P.A.

20090257289 - Internal voltage generator and semiconductor memory device including the same: A semiconductor device including an internal voltage generator circuit that provides an internal voltage having a different level depending on the operation speed is provided. The semiconductor device includes an internal voltage generator circuit configured to receive operation speed information to generate an internal voltage having a different level depending... Agent: Mannava & Kang, P.C.

20090257287 - Programmable bias circuit architecture for a digital data/clock receiver: Receiver architectures and related bias circuits for a data processor are provided. One embodiment of a receiver architecture for a computer processor includes a first linear receiver stage configured to receive a first input, a second input, and a first bias voltage. The first linear receiver stage is configured to... Agent: Ingrassia Fisher & Lorenz, P.C. (amd)

20090257290 - Low power shift register and semiconductor memory device including the same: A shift register includes a shift circuit configured to shift an input signal in synchronization with a shift clock to output an output signal of the shift register, and a clock control circuit configured to enable the shift clock in response to the input signal and disable the shift clock... Agent: Mannava & Kang, P.C.

20090257292 - Semiconductor device having resistance based memory array, method of reading, and writing, and systems associated therewith: One embodiment includes a non-volatile memory cell array, and a read unit configured to disable read operation for the non-volatile memory cell array for a time period following writing of data in the non-volatile memory cell array.... Agent: Harness, Dickey & Pierce, P.L.C

20090257293 - Semiconductor memory device: A semiconductor memory device includes a selector line selection circuit for selecting, in a read operation, a selector line for connecting a first main bit line connected to the sense amplifier with a sub-bit line to which the memory cell being read is connected, a selector line for connecting the... Agent: Mcdermott Will & Emery LLP

20090257291 - Semiconductor memory device and method for generating pipe-in signal thereof: A semiconductor memory device includes a preliminary signal generator configured to output a preliminary pipe-in signal enabled when a read command is applied. A delay unit is configured to delay the preliminary pipe-in signal and output the delayed preliminary pipe-in signal to match the timing of output data. A pipe-in... Agent: Mannava & Kang, P.C.

20090257294 - Programmable linear receiver for digital data clock signals: Receiver architectures and related bias circuits for a data processor are provided. One embodiment of a receiver architecture includes three linear receiver stages coupled in series. The first stage receives a differential data strobe (DQS) input signal associated with a plurality of data (DQ) signals, and the first stage has... Agent: Ingrassia Fisher & Lorenz, P.C. (amd)

20090257295 - Randomizing current consumption in memory devices: In some implementations, a memory device includes a plurality of memory cells, each memory cell storing a plurality of data bits; an input/output interface that is configured to, in response to receiving a read signal and an address value that identifies a specific memory cell in the plurality of memory... Agent: Fish & Richardson P.C.

20090257297 - Multi-chip semiconductor device providing enhanced redundancy capabilities: A semiconductor device including a plurality of semiconductor chips is provided. A semiconductor device includes a storing unit in which redundancy information portions are stored, and a comparing unit comparing a current address to the redundancy information portions and enabling or disabling operation of a semiconductor device based on the... Agent: Volentine & Whitt PLLC

20090257296 - Programmable memory repair scheme: The present disclosure provides semiconductor devices and methods, systems, and apparatus for testing and operating the same. A semiconductor memory device includes data storage elements and a repair circuit. The data storage elements include primary data storage elements and one or more redundant data storage elements, the primary data storage... Agent: Sidley Austin LLP

20090257298 - Semiconductor device having single-ended sensing amplifier: A single-ended sense amplifier in a semiconductor storage device having a hierarchical bit line structure includes a first MOS transistor for amplifying a signal outputted from a memory cell to a bit line, a second MOS transistor for feeding the output of the first MOS transistor to a global bit... Agent: Mcginn Intellectual Property Law Group, PLLC

20090257299 - Software refreshed memory device and method: A software refreshed memory device comprises a plurality of memory cells that must be periodically refreshed to avoid losing data. Preferably, the memory cells can avoid losing data even though the time interval between successive memory refresh operations is relatively long, as compared to the time interval between successive memory... Agent: Dickstein Shapiro LLP

20090257300 - Fuse information control device, semiconductor integrated circuit using the same, and control method thereof: A fuse information control device having a delay circuit to delay an active signal, includes a fuse circuit that outputs fuse information in response to a fuse information control signal, and a fuse information control signal generating unit that generates the fuse information control signal in response to one of... Agent: Baker & Mckenzie LLP Patent Department

20090257302 - Semiconductor memory apparatus capable of reducing ground noise: An apparatus includes a plurality of first driving signal driving units, and generates a first driving signal by driving an input signal, a plurality of second driving signal driving units, each of which drives an input signal and generates a second driving signal, a timing control unit that controls each... Agent: Venable LLP

20090257301 - Voltage level comparison circuit of semiconductor memory apparatus, voltage adjustment circuit using voltage level comparison circuit, and semiconductor memory apparatus using the same: A voltage adjustment circuit of a semiconductor memory apparatus includes a control voltage generating unit configured to distribute an external voltage for selectively outputting a plurality of distribution voltages as a control voltage in response to a control signal, the plurality of the distribution voltages each have different voltage levels,... Agent: Baker & Mckenzie LLP Patent Department

20090251939 - Priority encoder: A priority encoder encodes an (N+1)-bit thermometer code, where N indicates a natural number. A plurality of selectors are arranged in a matrix of M rows and (N+1) columns, where M indicates a natural number, and select one of signals at first and second input terminals (1,0) in accordance with... Agent: Martine Penilla & Gencarella, LLP

20090251940 - Nonvolatile semiconductor memory device using a variable resistance film and method of manufacturing the same: A plurality of bit lines s arranged crossing a plurality of first word lines. A first diode is arranged at each cross point of the first word lines and the bit lines. A cathode of the first diode is connected to one of the first word lines. A first variable... Agent: Finnegan, Henderson, Farabow, Garrett & Dunner LLP

20090251941 - Semiconductor device: A semiconductor device is provided, which includes a transistor, a memory element, a first control circuit and a second control circuit. A gate of the transistor is electrically connected to the first control circuit through a first word line, one of a source and a drain of the transistor is... Agent: Cook Alex Ltd

20090251942 - Method of programming a memory device of the one-time programmable type and integrated circuit incorporating such a memory: A memory device of the irreversibly electrically programmable type is provided with a memory cell having a dielectric zone disposed between a first electrode and second electrode. An access transistor is connected in series with the second electrode, and an auxiliary transistor is connected in series with the first electrode.... Agent: Gardere Wynne Sewell LLP Intellectual Property Section

20090251943 - Test circuit for an unprogrammed otp memory array: Circuits for testing unprogrammed OTP memories to ensure that wordline and bitline connections, column decoders, wordline drivers, correctness of decoding, sensing and multiplexing operate properly. The OTP testing system includes one or both of column test circuitry and row test circuitry. The column test circuitry charges all the bitlines to... Agent: Borden Ladner Gervais LLP Anne Kinsman

20090251944 - Memory cell having improved mechanical stability: Memory cells are described along with methods for manufacturing. A memory cell described herein includes a bottom electrode comprising a base portion and a pillar portion on the base portion, the pillar portion and the base portion having respective outer surfaces and the pillar portion having a width less than... Agent: Macronix C/o Haynes Beffel & Wolfeld LLP

20090251945 - System and method of operation for resistive change memory: The present invention provides a semiconductor device and a method for manufacturing thereof. The semiconductor device includes a data storage element which includes a variable resistance and an electrode, and a controller which selects a first mode that stores data by the resistance value of the variable resistance and a... Agent: Spansion LLC C/o Murabito , Hao & Barnes LLP

20090251946 - Data cells with drivers and methods of making and operating the same: Disclosed are methods and devices, among which is a device that includes a first semiconductor fin having a first gate, a second semiconductor fin adjacent the first semiconductor fin and having a second gate, and a third gate extending between the first semiconductor fin and the second semiconductor fin. In... Agent: Wells St. John P.s.

20090251947 - Semiconductor device having single-ended sensing amplifier: A semiconductor device has a DRAM cell configured from an information charge accumulating capacitor and a memory cell selecting transistor, the threshold voltage value of a MOS transistor that constitutes a sense circuit is monitored, and the monitored threshold voltage value of the MOS transistor is converted through the use... Agent: Mcginn Intellectual Property Law Group, PLLC

20090251948 - Semiconductor memory device: In a semiconductor memory device, a memory cell is connected with a local sense amplifier and a global sense amplifier via a local bit line and a global bit line. The local sense amplifier is a single-ended sense amplifier including a single MOS transistor, which detects a potential of the... Agent: Sughrue Mion, PLLC

20090251949 - Array structural design of magnetoresistive random access memory (mram) bit cells: Spin Transfer Torque Magnetoresistive Random Access Memory (STT-MRAM) bit cells are disclosed. The bit cells include a source line formed in a first plane and a bit line formed in a second plane. The bit line has a longitudinal axis that is parallel to a longitudinal axis of the source... Agent: Qualcomm Incorporated

20090251950 - Integrated circuit, memory cell arrangement, thermal select magneto-resistive memory cell, method of operating a thermal select magneto-resistive memory cell, and method of manufacturing a thermal select magneto-resistive memory cell: According to one embodiment of the present invention, an integrated circuit includes a thermal select magneto-resistive memory cell. The memory cell includes a stack of layers including a storage memory layer. The memory cell also includes a heating element which covers at least a part of the sidewalls of the... Agent: Slater & Matsil, L.L.P.

20090251951 - Magnetoresistive element and magnetic random access memory: A magnetoresistive element includes a foundation layer, a first magnetic layer on the foundation layer, a tunnel barrier layer on the first magnetic layer, and a second magnetic layer on the tunnel barrier layer. The first magnetic layer is made of a ferromagnetic metal containing one or more elements selected... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20090251952 - State machine sensing of memory cells: The present disclosure includes methods, devices, modules, and systems for sensing memory cells using a state machine. One method embodiment includes generating a first sensing reference according to a first output of a state machine. The method includes bifurcating a range of possible programmed levels to which a memory cell... Agent: Brooks, Cameron & Huebsch , PLLC

20090251953 - Variable resistance memory device: A variable resistance memory device includes a variable resistance memory cell array including a plurality of variable resistance memory cells; a plurality of global word lines configured to drive the variable resistance memory cell array; and a plurality of local word line decoders. Each of the plurality of local word... Agent: Harness, Dickey & Pierce, P.L.C

20090251954 - Variable resistance memory device and system: Disclosed is a semiconductor memory device including a memory cell array having a plurality of variable resistance memory cells divided into first and second areas. An I/O circuit is configured to access the memory cell array under the control of control logic so as to access the first or second... Agent: Volentine & Whitt PLLC

20090251956 - Magnetic random access memory devices, methods of driving the same and data writing and reading methods for the same: A magnetic memory device includes a lower structure or an antiferromagnetic layer, a pinned layer, an information storage layer, and a free layer formed on the lower structure or the antiferromagnetic layer. In a method of operating a magnetic memory device, information from the storage information layer is read or... Agent: Harness, Dickey & Pierce, P.L.C

20090251955 - Mram and data read/write method for mram: An MRAM according to the present invention is provided with a magnetic recording layer being a ferromagnetic layer and a pinned layer connected to the magnetic recording layer through a nonmagnetic layer. The magnetic recording layer includes a magnetization switching region, a first magnetization fixed region and a second magnetization... Agent: Young & Thompson

20090251957 - System and method for writing data to magnetoresistive random access memory cells: Magnetic random access memory (MRAM) cell with a thermally assisted switching writing procedure and methods for manufacturing and using same. The MRAM cell includes a magnetic tunnel junction that has at least a first magnetic layer, a second magnetic layer, and an insulating layer disposed between the first and a... Agent: Orrick, Herrington & Sutcliffe, LLPIPProsecution Department

20090251958 - Read circuitry for an integrated circuit having memory cells and/or a memory cell array, and method of operating same: An integrated circuit device (e.g., a logic device or a memory device) having a memory cell array which includes (i) a plurality of memory cells, wherein each memory cell is programmable to store one of a plurality of data states, and (ii) a bit line, having a plurality of memory... Agent: Neil Steinberg

20090251959 - Semiconductor memory device and driving method thereof: A memory includes: memory cells including floating bodies, wherein in a data holding state, a potential of the first gate electrode is set to be higher than one of potentials of the source and drain layer and lower than the other of the potentials of the source and drain layer... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20090251960 - High temperature memory device: Disclosed herein are various nonvolatile integrated device embodiments suitable for use at high temperatures. In some embodiments, a high temperature nonvolatile integrated device comprises a sapphire or spinel substrate having multiple ferroelectric memory cells disposed upon it. In other embodiments, a high temperature nonvolatile integrated device comprises a silicon on... Agent: Krueger Iselin LLP (1391)

20090251962 - Three-dimensional memory device and driving method thereof: A driving method of a three-dimensional memory device having a plurality of layers is provided. One of the layers is selected. A well of the selected layer is biased with a first well voltage. A word line voltage is applied to a selected word line of the selected layer. A... Agent: F. Chau & Associates, LLC

20090251963 - Non-volatile memory device and method of manufacturing the same: A multi-layered non-volatile memory device and a method of manufacturing the same. The non-volatile memory device may include a plurality of first semiconductor layers having a stack structure. A plurality of control gate electrodes may extend across the first semiconductor layers. A first body contact layer may extend across the... Agent: Harness, Dickey & Pierce, P.L.C

20090251965 - Nonvolatile memory device including circuit formed of thin film transistors: A transistor is arranged for electrically isolating a sense amplifier formed of a thin film transistor from a data line electrically coupled to the sense amplifier. When a write driver drives the data line, a control signal is applied to isolate the data line from the sense amplifier.... Agent: Mcdermott Will & Emery LLP

20090251964 - Nonvolatile semiconductor memory device: A nonvolatile semiconductor memory device according to the present invention is a NAND-type flash memory which is electrically capable of programming/erasing. The nonvolatile semiconductor memory device has at least 3 or more memory cell columns in which a plurality of memory cells are connected in series, and these memory cell... Agent: Miles & Stockbridge PC

20090251966 - Semiconductor memory having volatile and multi-bit, non-volatile functionality and methods of operating: A semiconductor memory cell, semiconductor memory devices comprising a plurality of the semiconductor memory cells, and methods of using the semiconductor memory cell and devices are described. A semiconductor memory cell includes a substrate having a first conductivity type; a first region embedded in the substrate at a first location... Agent: Law Office Of Alan W. Cannon

20090251968 - Integrated circuit having a base structure and a nanostructure: In an embodiment, an integrated circuit may include a metallically conductive structure, a base structure having a crystal orientation, the base structure being adjacent to the metallically conductive structure, and a nanostructure disposed on the base structure, the nanostructure having substantially the same crystal orientation as the base structure.... Agent: Slater & Matsil, L.L.P.

20090251967 - Non-volatile storage having a connected source and well: A non-volatile storage device is disclosed that includes a set of connected non-volatile storage elements formed on a well, a bit line contact positioned in the well, a source line contact positioned in the well, a bit line that is connected to the bit line contact, and a source line... Agent: Vierra Magen/sandisk Corporation

20090251969 - Analog read and write paths in a solid state memory device: A memory array in a memory device is coupled to an analog I/O data interface that enables analog voltage levels to be written to the memory array. The I/O interface is comprised of a plurality of analog data paths that each includes a capacitor for storing charge corresponding to a... Agent: Attn: Kenneth W. Bolvin Leffert Jay & Polglaze, P.A.

20090251970 - Semiconductor device and control method thereof: A semiconductor device in accordance with one embodiment of the invention can include a first data storage region including a non-volatile main data storage region. Additionally, the semiconductor device can include a second data storage region including a non-volatile reference region wherein an erasing operation and a writing operation are... Agent: Spansion LLC C/o Murabito , Hao & Barnes LLP

20090251961 - Flash memory device and voltage generating circuit for the same: Disclosed is a flash memory device which includes a memory core, a high voltage generating circuit and a reference voltage generating circuit. The high voltage generating circuit is configured to generate a high voltage to be supplied to the memory core. The reference voltage generating circuit is configured to generate... Agent: Volentine & Whitt PLLC

20090251971 - Non-volatile semiconductor storage device and memory system: According to an aspect of the invention, a non-volatile semiconductor storage device includes: a memory cell array including memory strings, each of the memory strings having: a first end; a second end; and a plurality of memory cells connected in series between the first end and the second end, the... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20090251972 - Nonvolatile memory arrays with charge trapping dielectric and with non-dielectric nanodots: Charge-trapping dielectric (160) in a nonvolatile memory cell is recessed from under the control gate's edge and/or from an edge of a substrate isolation region. The recessed geometry serves to reduce or eliminate charge trapping in regions from which the charge may be difficult to erase.... Agent: Haynes And Boone, LLPIPSection

20090251973 - Trench monos memory cell and array: The MONOS vertical memory cell of the present invention allow miniaturization of the memory cell area. The two embodiments of split gate and single gate provide for efficient program and erase modes as well as preventing read disturb in the read mode.... Agent: Saile Ackerman LLC

20090251974 - Memory circuits with reduced leakage power and design structures for same: A memory circuit includes a global read bit line, a global read bit line latch, and a plurality of sub-arrays, each of which includes first and second local read bit lines, first and second local write bit lines, and first and second pluralities of memory cells interconnected, respectively, with the... Agent: Ryan, Mason & Lewis, LLP

20090251975 - Circuit and method for a sense amplifier with instantaneous pull up/pull down sensing: A circuit and method for a sense amplifier for sensing the charge stored when a select signal couples a memory cell to the sense amplifier. A pull up voltage and a pull down voltage are instantaneously supplied to the sense amplifier to sense the small signal differential input on the... Agent: Slater & Matsil, L.L.P.

20090251976 - Method and apparatus for dqs postamble detection and drift compensation in a double data rate (ddr) physical interface: Circuitry for reading from a double data rate type memory, the circuitry including control logic, a first bi-directional input/output interface (I/O) configured to be coupled to a data bus of a double data rate type memory and to receive therefrom a data transmission having a duration selected by the control... Agent: Abelman, Frayne & Schwab

20090251977 - Device having malfunction preventing circuit: A fixing device fixes a toner image on a recording medium. The fixing device includes a heat source that converts electric power into heat and a fixing member that gives the heat generated by the heat source to the recording medium on which the toner image is formed. The fixing... Agent: Patterson & Sheridan, L.L.P.

20090251978 - Integration of lbist into array bisr flow: A method, an integrated circuit structure, and an associated design structure for the integrated circuit structure have a plurality of logic blocks, at least one of which is a redundant logic block. In addition, the structure includes a logic built-in self test device (LBIST) operatively connected to the logic blocks... Agent: Frederick W. Gibb, Iii Gibb Intellectual Property Law Firm, LLC

20090251979 - Method for suppressing current leakage in memory: A method for suppressing a current leakage of a memory is provided. The memory at least includes a memory cell, an equalizing circuit, a current limiter, a word line and a pair of complementary bit lines. The method includes: having the memory cell entering a pre-charging mode; having the equalizing... Agent: Jianq Chyun Intellectual Property Office

20090251980 - Semiconductor memory device: A semiconductor memory device includes a discharge circuit that discharges bit lines to a ground potential, a sense amplifier of a single-ended input configuration, and a charging transistor connected between a power supply and an input node of the sense amplifier. The charging transistor charges a bit line from a... Agent: Young & Thompson

20090251981 - Memory with a fast stable sensing amplifier: A memory includes a memory cell, a sensing amplifier, four N-type MOS transistors, a reference circuit, and a comparator. The sensing amplifier is used for sensing digital data stored in the memory cell of the memory and generating an output signal corresponding to the digital data when the memory cell... Agent: North America Intellectual Property Corporation

20090251982 - Low energy memory component: The present invention is directed to a DRAM circuit that implements a self-refresh scheme to substantially reduce its power dissipation level during self-refresh operations. A ramped power supply voltage in replacement of a substantially invariant power supply voltage is used to power a sense amplifier in the DRAM circuit for... Agent: Morgan Lewis & Bockius LLP/rambus Inc.

20090251985 - Semiconductor memory apparatus: A first signal input circuit outputs a first control signal in response to self-refresh and active signals. A second signal input circuit outputs a second control signal in response to the self-refresh and active signals. The power supply circuit applies a first supply voltage to an output terminal in response... Agent: Venable LLP

20090251983 - Semiconductor memory apparatus capable of reducing ground noise: An apparatus includes a plurality of first driving signal driving units, and generates a first driving signal by driving an input signal, a plurality of second driving signal driving units, each of which drives an input signal and generates a second driving signal, a timing control unit that controls each... Agent: Venable LLP

20090251984 - Static memory device and static random access memory device: A static memory device includes a bit cell connected to an internal voltage line, and a power supply control circuit connected between the internal voltage line and a power supply voltage, wherein the power supply control circuit is configured to supply the power supply voltage level to the internal voltage... Agent: Lee & Morse, P.C.

20090251986 - Fifo peek access: Disclosed is a FIFO peek access device that utilizes a peek signal to access data stored in a FIFO without losing or erasing data. The peek signal is applied to read address logic and prevents the incrementing of the pointers in the peek address logic, so that after a read... Agent: Cochran Freund & Young LLC Lsi Corporation

20090251987 - Memory data transfer: In one aspect, there is provided a method for controlling data output by a memory device. The method may include receiving a first clock signal having a first frequency. Moreover, a second and third clock signals may be produced from the first clock signal. The second and third clock signals... Agent: Courtney Staniford & Gregory LLP

20090251988 - System and method for providing a non-power-of-two burst length in a memory system: A memory system, memory interface device and method for a non-power-of-two burst length are provided. The memory system includes a plurality of memory devices with non-power-of-two burst length logic and a memory interface device including non-power-of-two burst length generation logic. The non-power-of-two burst length generation logic extends a burst length... Agent: Cantor Colburn LLP-ibm Poughkeepsie