Static information storage and retrieval inventions

20080106922 - Semiconductor memory device and layout structure of word line contacts: A semiconductor memory device and a layout structure of word line contacts, in which the semiconductor memory device includes an active region, a plurality of memory cells, and word line contacts. The active region is disposed in a first direction as a length direction on a semiconductor substrate and is... Agent: F. Chau & Associates, LLC

20080106923 - Phase change memory cells with dual access devices: A self aligning memory device, with a memory element switchable between electrical property states by the application of energy, includes a substrate and word lines, at least the sides of the word lines covered with a dielectric material which defines gaps. An access device within a substrate has a first... Agent: Macronix C/o Haynes Beffel & Wolfeld LLP

20080106925 - Correlated electron memory: A non-volatile resistive switching memory that includes a homogeneous material which changes between the insulative and conductive states due to correlations between electrons, particularly via a Mott transition. The material is crystallized into the conductive state and does not require electroforming.... Agent: Patton Boggs LLP

20080106926 - Non-volatile resistance switching memories and methods of making same: An integrated circuit memory cell including: a semiconductor having a first active area, a second active area, and a channel between the active areas; and a layer of a variable resistance material (VRM) directly above the channel. In one embodiment, there is a first conductive layer between the VRM and... Agent: Patton Boggs LLP

20080106924 - Resistive memory device and method of writing data: A resistive memory device is provided. The resistive memory device includes word lines arranged in M rows, bit lines arranged in N columns, local source lines arranged in M/2 rows, and resistive memory cells arranged in M rows and N columns. Each of the resistive memory cells includes a resistance... Agent: Volentine & Whitt PLLC

20080106927 - Stabilized resistive switching memory: A non-volatile resistive switching memory that includes a material which changes between the insulative and conductive states. The material is stabilized against charge trapping by oxygen vacancies by an extrinsic ligand, such as carbon.... Agent: Patton Boggs LLP

20080106928 - Energy adjusted write pulses in phase-change memory cells: An integrated circuit that includes a plurality of phase-change memory cells, at least one write pulse generator, and at least one temperature sensor. The plurality of phase-change memory cells are each capable of defining at least a first and a second state. The write pulse generator generates a write pulse... Agent: Dicke, Billig & Czaja

20080106929 - Electrochemical memory with heater: Non-volatile resistance change memories, systems, arrangements and associated methods are implemented in a variety of embodiments. According to one embodiment, resistance-change memory devices are implemented having a pair of electrodes and an intervening electrochemical material. A heating element facilitates changes in resistance of the electrochemical material-region due to changes in... Agent: Crawford Maunu PLLC

20080106930 - Pram and method of firing memory cells: A PRAM includes a memory cell array of phase change memory cells, and a write circuit receiving an externally provided first voltage and supplying a write pulse for writing data to the memory cells in a normal operation mode. The write circuit also receives an externally provided second voltage higher... Agent: Volentine & Whitt PLLC

20080106931 - Phase change memory device: A phase change memory device has a semiconductor substrate; a plurality of cell arrays stacked above the semiconductor substrate, each cell array having memory cells arranged in a matrix manner for storing resistance values as data that are determined by phase change of the memory cells, bit lines each commonly... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.c.

20080106932 - Coil sensor memory device and method: A non-volatile random access memory device. The non-volatile random access memory device may include a magnetic bit, a write/sense, and a read pulse module. The read pulse module may be configured to send a read pulse signal to the magnetic bit. In addition, a write module may be in communication... Agent: Advantia Law Group

20080106933 - Advanced multi-bit magnetic random access memory device: An advanced multi-bit magnetic random access memory device and a method for writing to the advanced multi-bit magnetic random access memory device. The magnetic memory includes one or more pair-cells. A pair-cell is two memory cells. Each memory cell has a magnetic multilayer structure. The structure includes a magnetically changeable... Agent: Sughrue Mion, PLLC

20080106934 - Memory device and method of operating and fabricating the same: A memory transistor including a substrate, a tunnel insulating pattern on the substrate, a charge storage pattern on the tunnel insulating pattern, a blocking insulating pattern on the charge storage pattern, and a gate electrode on the blocking insulating pattern, the blocking insulating pattern surrounding the gate electrode and methods... Agent: Harness, Dickey & Pierce, P.L.C

20080106935 - Non-volatile semiconductor memory device using weak cells as reading identifier: A non-volatile semiconductor memory is configured to monitor for onset of a read disturbance (e.g., due to soft programming) and to carry out operations to protect data therein. A non-volatile semiconductor memory has a memory cell array that includes normal memory cells and a flag memory cell. The flag memory... Agent: Myers Bigel Sibley & Sajovec

20080106937 - Memory device employing three-level cells and related methods of managing: A memory device may include an array of addressable three-level cells, a coding circuit being input with three-bit strings and generating corresponding ternary strings based upon a code, and a program circuit being input with the ternary strings and storing them in respective pairs of three-level cells. The memory device... Agent: Allen, Dyer, Doppelt, Milbrath & Gilchrist P.A.

20080106936 - Adaptive read and write systems and methods for memory cells: Adaptive memory read and write systems and methods are described herein that adapts to changes to threshold voltage distributions of memory cells as of result of, for example, the detrimental affects of repeated cycling operations of the memory cells. The novel systems may include at least multi-level memory cells, which... Agent: Schwabe, Williamson & Wyatt, P.c.

20080106938 - Semiconductor integrated circuit device and data processor device: A semiconductor device includes a sense amplifier and a decoder provided on a semiconductor substrate together with memory cells provided above the sense amplifier and the decoder. Each of the memory cells includes a channel region, in which current flows in a direction perpendicular to a surface of the semiconductor... Agent: Antonelli, Terry, Stout & Kraus, LLP

20080106939 - Storage device employing a flash memory: A semiconductor disk wherein a flash memory into which data is rewritten in block unit is employed as a storage medium, the semiconductor disk including a data memory in which file data are stored, a substitutive memory which substitutes for blocks of errors in the data memory, an error memory... Agent: Mattingly, Stanger, Malur & Brundidge, P.c.

20080106940 - Apparatus and method for improving write/read endurance of non-volatile memory: An apparatus for improving write/read endurance of non-volatile memory includes a non-volatile memory area including a plurality of non-volatile memory cells to store data, and an endurance improving circuit detecting a degradation characteristic of the non-volatile memory cells upon the integrated circuit card being reset and initialized. The apparatus increases... Agent: Frank Chau, Esq. F. Chau & Associates, LLC

20080106941 - Decoders and decoding methods for nonvolatile semiconductor memory devices: A decoder for a non-volatile semiconductor memory device includes a level shifter configured to generate a negative first voltage at an output thereof responsive to a first state of a global word line and to generate a second voltage more positive than the first voltage responsive to a second state... Agent: Myers Bigel Sibley & Sajovec

20080106942 - Nand type non-volatile memory device and method for fabricating the same: A method for fabricating a NAND type flash memory device includes defining a select transistor region and a memory cell region in a semiconductor substrate, forming a tunnel insulating layer, a floating gate conductive layer, and a dielectric layer over a semiconductor substrate, etching the dielectric layer, thereby forming an... Agent: Marshall, Gerstein & Borun LLP

20080106943 - Nonvolatile semiconductor memory: In an EEPROM consisting of a NAND cell in which a plurality of memory cells are connected in series, the control gate voltage Vread of the memory cell in a block selected by the data read operation is made different from the each of the voltages Vsg1, Vsg2 of the... Agent: Banner & Witcoff, Ltd. Attorneys For Client No. 000449, 001701

20080106944 - Method for setting programming start bias for flash memory device and programming method using the same: A method for setting a programming start bias for a flash memory device to perform a programming operation is provided. First, the method performs pre-programming to change a threshold voltage distribution of a selected transistor using a first programming voltage and detects the maximum threshold voltage level of the changed... Agent: Townsend And Townsend And Crew, LLP

20080106945 - Self-reference sense amplifier circuit and sensing method: A sense amplifier circuit for a flash memory device is disclosed. The sense amplifier including a first transistor controlled by a first voltage applied via a selected bit line, and a second transistor controlled by a second voltage applied via an unselected bit line. The second transistor has a current... Agent: Volentine & Whitt PLLC

20080106946 - Nonvolatile semiconductor memory device and nonvolatile memory system: A nonvolatile semiconductor memory device including a memory cell array including a plurality of electrically rewritable nonvolatile memory cells arranged in series, the memory cell storing data using a plurality of threshold levels, a threshold level storage section storing a programming method switch threshold level on which a first programming... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.c.

20080106947 - Decoders and decoding methods for nonvolatile memory devices using level shifting: A decoder for a nonvolatile memory device includes a level shifter configured to produce a first voltage at an output thereof responsive to a first state of a global word line and to produce a second voltage at the output responsive to a second state of the global word line.... Agent: Myers Bigel Sibley & Sajovec

20080106948 - Nonvolatile semiconductor memory device, manufacturing method thereof and method of programming information into the memory device: A nonvolatile semiconductor memory device capable of improving injection efficiency and simplifying manufacturing process is provided. The device comprises a memory cell having second conductive type of first impurity diffusion area and second impurity diffusion area on a first conductive type of semiconductor substrate, between the first and second impurity... Agent: Morrison & Foerster LLP

20080106949 - Array source line (avss) controlled high voltage regulation for programming flash or ee array: A method for programming a Flash memory array comprises coupling at least one of a current source and a potential source to at least one selected bitline of a Flash memory array, monitoring a potential VAVSS of an array VSS line by means of a comparator, allowing the array VSS... Agent: Schneck & Schneck

20080106950 - High-speed memory device easily testable by low-speed automatic test equipment and input/output pin control method thereof: The present invention provides a high-speed memory device that can be easily tested using the existing low-speed Automatic Test Equipment (ATE). In an embodiment of the invention, a memory device includes two channels. During normal communications with a host, one channel is used for bidirectional communications with a host. But... Agent: Volentine & Whitt PLLC

20080106951 - Architecture for an output buffered switch with input groups: Embodiments of the present invention provide a system that transfers data between the components in the computer system through a switch. In these embodiments, the switch includes multiple switch chips which are coupled together and are configured to collectively function as a switch. During operation, each switch chip, receives cells... Agent: Sun Microsystems Inc. C/o Park, Vaughan & Fleming LLP

20080106953 - Multi-port memory devices: A semiconductor storage device, comprising: a first port to write data to a storage element; and a second port to read a signal generated by the storage element, wherein reading the generated signal protects data stored at the storage element from a read condition disturbance.... Agent: Raminda U. Madurawe

20080106952 - Multimode data buffer and method for controlling propagation delay time: A data buffer, such as a data strobe input buffer or a data input buffer, which may operate in multiple modes, such as a single mode (SM) and a dual mode (DM) and where the mode is selected by providing a signal, such as an external signal such as an... Agent: Harness, Dickey & Pierce, P.L.C

20080106954 - Voltage and temperature compensation delay system and method: A delay circuit provides a voltage and temperature compensated delayed output signal. The delay circuit includes a first delay stage that receives an input signal, and generates a delayed output signal from the input signal. The delay circuit also includes a second delay stage that receives the delayed output signal... Agent: Dorsey & Whitney LLP Intellectual Property Department

20080106955 - Sram split write control for a delay element: A Static Random Access Memory (SRAM) having a split write control is described. The SRAM includes bit, write, and write-word lines. Each memory cell within the SRAM includes a delay which is coupled to a dedicated write-word line. When a cell is not being written, its delay receives a delay... Agent: Honeywell International Inc.

20080106957 - Method and apparatus for generating high-frequency command and address signals for high-speed semiconductor memory device testing: A method and system for testing a semiconductor memory device using low-speed test equipment. The method includes providing a high-frequency test pattern by grouping a command signal and an address signal into command signal groups and address signal groups each corresponding to L cycles of a clock signal output from... Agent: Volentine & Whitt PLLC

20080106958 - Semiconductor chip package and method and system for testing the same: A semiconductor chip package with a flash memory portion and a method and system for testing the same are provided. After an internal cycling test is automatically and independently initiated on the flash memory chip, a test on other memory portions in the semiconductor chip package is performed. The semiconductor... Agent: Marger Johnson & Mccollom, P.c.

20080106956 - Sram test method and sram test arrangement to detect weak cells: A method and a test arrangement for testing an SRAM having a first cell and a second cell coupled between a pair of bitlines is disclosed. In a first step (410), a data value is stored in the first cell being the cell under test (CUT), and its complement is... Agent: Nxp, B.v. Nxp Intellectual Property Department

20080106959 - Semiconductor memory device having advanced test mode: An apparatus for testing an operation of a semiconductor memory device having a plurality of banks in a compress test mode includes an internal address generator for receiving an external bank address and generating internal bank addresses in response to a bank interleaving test signal; a read operation testing block... Agent: Blakely Sokoloff Taylor & Zafman

20080106961 - Data transmission control device, and data transmission control method: A data transmission control device includes: a memory control unit that is connected to a DRAM, and accesses to the DRAM in accordance with a read/write request from various devices that request read/write of data from/into the DRAM; and a command control unit that issues an active command of designating... Agent: Sughrue-265550

20080106962 - Memory device and method thereof: A memory device and a method thereof. The memory described includes a control module and a single-port memory array. The control circuit generates control signals according to a clock signal, a read command signal and a write command signal. The single-port memory array is accessed according to the control signals.... Agent: Thomas, Kayden, Horstemeyer & Risley, LLP

20080106960 - Memory device architecture and method for improved bitline pre-charge and wordline timing: A memory device architecture having improved bitline pre-charge and wordline timing operations includes a pre-charge driver, a pre-charge line, a timing controller, a wordline driver, and a wordline coupled to a selected memory cell. The pre-charge driver is operable to supply a pre-charge signal to a pre-charge line when activated... Agent: Slater & Matsil LLP

20080106963 - Circuit and method for an sram with two phase word line pulse: A circuit and method for providing a two phase word line pulse for use during access cycles in an SRAM memory with improved operating margins. A first and a second timing circuit are provided and a word line voltage suppression circuit is provided to reduce the voltage on the active... Agent: Slater & Matsil, L.L.P.

20080106964 - Semiconductor storage device: A semiconductor storage device comprising: unit blocks each including memory cells, first row of sense amplifiers on one side of bit lines; second row of sense amplifiers on an other side of the bit lines; first switch means which switches a connection state between the one side of the bit... Agent: Mcdermott Will & Emery LLP

20080106965 - Semiconductor device and memory: A semiconductor device of the present invention comprises a first step-down voltage circuit to generate a first step-down voltage lower than an externally-supplied power supply voltage, and a second step-down voltage circuit to generate a second step-down voltage lower than the first step-down voltage. The first step-down voltage circuit has... Agent: Young & Thompson

20080106966 - Circuit of detecting power-up and power-down: A power-up/power-down detecting circuit may include a power detecting circuit, a selecting circuit, and a determining circuit. The power detecting circuit may generate a plurality of detection signals based on a plurality of sensing signals corresponding to currents flowing through a plurality of function blocks. The selecting circuit may generate... Agent: Harness, Dickey & Pierce, P.L.C

20080106967 - Method and apparatus for communicating command and address signals: Apparatus and methods for communicating command and address inputs to a memory device. In one embodiment, a memory device includes a shared bus interface defined by a portion of pins from a command bus interface and a portion of pins from an address bus interface. Each portion of pins is... Agent: Patterson & Sheridan, LLP Gero Mcclellan / Qimonda

20080101104 - Stacked memory: A stacked memory is configured such that a ratio between data and ECC bits, a ratio between quantities of data layers and ECC layers, and a ratio between quantities of data activated mats and ECC activated mats are equal to each other. The memory chip has a greater quantity of... Agent: Foley And Lardner LLP Suite 500

20080101105 - Memory module and method for operating a memory module: A memory module includes an electronic printed circuit board with at least one contact strip, a plurality of integrated memory components, at least one first and one second buffer component, and a number of conductor tracks, which proceed from the contact strip and which are arranged on or in the... Agent: Slater & Matsil, L.L.P.

20080101106 - State storage with defined retention time: A state storage device for use in an RFID tag includes, in at least one embodiment, a capacitor coupled to a high impedance node. The storage device can be configured to indicate a high or low bit condition. The high impedance node can be designed to dissipate the stored electrical... Agent: Perkins Coie LLP Patent-sea

20080101107 - Ferroelectric semiconductor memory device and method for reading the same: A first ferroelectric memory cell and a second ferroelectric memory cell each include a ferroelectric capacitor and a transistor and each store one set of information. A word-line is shared by the first and second ferroelectric memory cells. A first plate line is connected to the first ferroelectric memory cell... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20080101108 - Semiconductor device including storage device and method for driving the same: A structure of a storage device which can operate memory elements utilizing silicide reaction using the same voltage value for writing and for reading, and a method for driving the same are proposed. The present invention relates to a storage device including a memory element and a circuit which changes... Agent: Eric Robinson

20080101110 - Combined read/write circuit for memory: A memory device includes an array portion of resistive memory cells organized in rows and columns, wherein the rows correspond to word lines and the columns correspond to bit lines. The device further includes a combined read/write circuit associated with each respective bit line in the array portion configured to... Agent: Eschweiler & Associates LLC

20080101111 - Phase change memory device with ensured sensing margin and method of manufacturing the same: Disclosed is a phase change memory device including: a semiconductor substrate having a plurality of bar-type active areas; a plurality of word lines arranged in a direction perpendicular to the active areas on the semiconductor substrate and in which a first pair of the word lines connected to each other... Agent: Ladas & Parry LLP

20080101112 - Phase change memory device with reduced unit cell size and improved transistor current flow and method for manufacturing the same: A phase change memory device includes: a semiconductor substrate having active areas; a pair of word lines formed over the active areas and connected with each other at each end thereof; source areas formed in the respective active areas at both sides of the pair of word lines; drain areas... Agent: Ladas & Parry LLP

20080101109 - Phase change memory, phase change memory assembly, phase change memory cell, 2d phase change memory cell array, 3d phase change memory cell array and electronic component: A phase change memory having a memory material layer consisting of a phase change material, and a first and second electrical contact which are located at a distance from one another and via which a switching zone of the memory material layer can be traversed by a current signal, wherein... Agent: Bachman & Lapointe, P.C.

20080101113 - Memory device and method of manufacturing the same: There are provided a memory device capable of writing and reading data at a low voltage and a method of manufacturing the same. The memory device comprises: a bit line formed in one direction; a plurality of word lines provided crosswise above the bit line, the word lines formed in... Agent: Mills & Onello LLP

20080101114 - Floating body semiconductor memory device and method of operating the same: A semiconductor memory device includes a memory cell array having first and second blocks, respectively including first and second memory cells with floating bodies. The first memory cell is connected between a first bit line and a source line, and the second memory cell is connected between a second bit... Agent: Volentine & Whitt PLLC

20080101115 - Semiconductor memory device comprising floating body memory cells and related methods of operation: A semiconductor device comprising floating body memory cells performs read and write operations by selectively connecting bit lines and inverted bit lines to sense bit lines and inverted sense bit lines.... Agent: Volentine & Whitt PLLC

20080101116 - Multi-level cell copyback program method in a non-volatile memory device: A multi-level cell copyback program method in a non-volatile memory device is disclosed. The method includes reading LSB data of a source page, and storing the read LSB data in a second register of a page buffer, transmitting the data stored in the second register to a first register coupled... Agent: Townsend And Townsend And Crew, LLP

20080101117 - Trap-charge non-volatile switch connector for programmable logic: A nonvolatile trap charge storage cell selects a logic interconnect transistor uses in programmable logic applications, such as FPGA. The nonvolatile trap charge element is an insulator located under a control gate and above an oxide on the surface of a semiconductor substrate. The preferred embodiment is an integrated device... Agent: Stephen B. Ackerman

20080101118 - Method for preventing over-erasing of unused column redundant memory cells in a flash memory having single-transistor memory cells: A method is provided for testing and for preventing over-erasure of unused redundant memory cells that can be subsequently used to replace defective memory cells in a Flash memory. An unused redundant memory cell is preprogrammed and tested simultaneously with each group of n memory cells. The selected unused redundant... Agent: Schneck & Schneck

20080101119 - Non-volatile memory device and method of erasing the same: A non-volatile memory device includes planes, a control logic circuit, a high voltage generator, and a X-decoder. The planes have a plurality of memory cell blocks, respectively. The control logic circuit outputs a row address, which allows a block address to select the same memory cell blocks from different planes... Agent: Townsend And Townsend And Crew, LLP

20080101120 - Method of programming multi-pages and flash memory device of performing the same: In programming multi-pages in a flash memory device, a first page group and a second page group are formed with respect to each of at least one memory plane by grouping page buffers such that logical odd bitlines and logical even bitlines correspond to one of the first page group... Agent: Myers Bigel Sibley & Sajovec

20080101121 - Modifiable gate stack memory element: An apparatus and method for storing information are provided, including using an integrated circuit including a transistor having a channel, a gate oxide layer, a gate electrode, and a modifiable gate stack layer. To store information, the on-resistance of the transistor is changed by causing a non-charge-storage based physical change... Agent: Slater & Matsil LLP

20080101122 - Methods of applying read voltages in nand flash memory arrays: Provided is a method of improving the read disturb characteristics of a flash memory array. According to the method, in a flash memory array having at least one cell string in which a string selection transistor, a plurality of memory cells, and a ground selection transistor are connected in series,... Agent: Myers Bigel Sibley & Sajovec

20080101123 - Nand flash memory cell programming: A flash memory device, such as a NAND flash, is described having an array of floating gate transistor memory cells arranged in a first and second addressable blocks. A voltage source to supply programming voltages to control gates of the floating gate transistor memory cells is provided. The voltage source... Agent: Schwegman, Lundberg & Woessner/micron

20080101125 - Biasing circuit for eeprom memories with shared latches: An EEPROM memory having a matrix of individually selectable memory cells, the matrix having a plurality of columns, a plurality of data lines each coupled with the cells of a corresponding column, the data lines being grouped in a plurality of packets, a plurality of biasing elements for providing a... Agent: Stmicroelectronics Inc. C/o Wolf, Greenfield & Sacks, P.C.

20080101124 - Programming pulse generator: A signal generator circuit is configured to generate program signals for a memory array. The program signals are applied to word lines in the memory array, and have a transient state based on a coupling characteristic of the word lines and selector gates. The transient state is configured to minimize... Agent: Fish & Richardson P.C.

20080101126 - Faster programming of highest multi-level state for non-volatile memory: A coarse/fine programming technique is used for programming to lower states while using a standard technique (not coarse/fine programming) for programming to the highest state(s). However, when the programming of the lower states is finished, a number of programming pulses are still needed to program the highest state. To improve... Agent: Vierra Magen/sandisk Corporation

20080101127 - Reading and writing method for non-volatile memory with multiple data states: The invention provides a reading method for a memory with multiple data states by applying a plurality of reading signals to an MIM element coupled to a memory cell. The logic level of the data stored in the memory cell is determined based on the number of the reading signals... Agent: Birch Stewart Kolasch & Birch

20080101128 - Nonvolatile memory device and method of reading information from the same: A nonvolatile memory device includes a memory cell array and a voltage controller. The memory cell array includes a plurality of memory blocks each including a plurality of cell strings, where each of the cell strings includes a first selection transistor, a second selection transistor, and at least one memory... Agent: Volentine & Whitt PLLC

20080101129 - Semiconductor memory device: In a semiconductor memory device which uses a same pad for an address input and data input/output, and has an input circuit and data output circuit connected to the pad, an output of the data output circuit is turned to a high impedance state in accordance with a chip enable... Agent: Arent Fox LLP

20080101130 - Semiconductor device: A semiconductor device includes plural memory cell blocks, each having a memory cell array of plural memory cells. Plural control circuits are provided in correspondence with each of the memory cell blocks, for writing information to the memory cell blocks and for reading information written in the memory cell blocks.... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20080101131 - Semiconductor memory device and method for reducing cell activation during write operations: Embodiments of the invention provide devices or methods that include a status bit representing an inversion of stored data. New data is written to selected cells, the new data is selectively inverted, and the status bit is selectively toggled, based on a comparison between pre-existing data and new data associated... Agent: Volentine & Whitt PLLC

20080101132 - Memory output circuit and method thereof: An output circuit of a memory is provided. The output circuit includes a first pre-charge circuit, a multiplexer, and a sense amplifier. The first pre-charge circuit pre-charges the voltage of a target readout bit line to the logic high level according to a pre-charge signal. The multiplexer selects the target... Agent: Thomas, Kayden, Horstemeyer & Risley, LLP

20080101133 - Adaptive gate voltage regulation: A memory device generates a select voltage and an unselect voltage on bit lines and generates a bit line select voltage having a magnitude less than the unselect voltage so that the application of the bit line select voltage to a gate of a transistor receiving the select voltage causes... Agent: Fish & Richardson P.C.

20080101134 - Self refresh control device: Disclosed herein is a self refresh control device for reducing a current leakage of transistors in off-state. The apparatus for controlling a voltage used in a semiconductor memory device includes a first voltage supplying block for supplying a first voltage to the semiconductor memory device in response to an inputted... Agent: Mcdermott Will & Emery LLP

20080101135 - High-density semiconductor device: A high-density semiconductor device includes a first input/output line connected among a plurality of banks on a core area storing data, so that it transmits data, a second input/output line connected to a data pad capable of performing data input/output operations at a Peri-area, so that it transmits data, a... Agent: Cooper & Dunham, LLP

20080101136 - Semiconductor memory device having write data through function: A semiconductor memory device includes a switch that turns on or off connection between a write data line pair which is an output of a write buffer and read data line pair. For a Write Data Through function, the switch is turned on in response to an activated one-shot pulse... Agent: Mcginn Intellectual Property Law Group, PLLC

20080101137 - Semiconductor memory device having a plurality of chips and capability of outputting a busy signal: One package contains a plurality of memory chips. Each memory chip has an I/O terminal which generates a busy signal. The busy signal enables a busy state when a power supply voltage value reaches a specified and guaranteed range after a power-on sequence. The busy signal maintains the busy state... Agent: Frommer Lawrence & Haug

20080101140 - Cas latency circuit and semiconductor memory device including the same: Embodiments of the invention provide a column address strobe (CAS) latency circuit that generates a stable latency signal in a high-speed semiconductor memory device, and a semiconductor memory device including the CAS latency circuit. The CAS latency circuit may include an internal read command signal generator and a latency clock... Agent: Volentine & Whitt PLLC

20080101139 - Memory access strobe configuration system and process: A memory access strobe configuration system and process operable to generate a strobe signal having a selected phase. Based on the strobe signal, a write/read cycle using a first logic value at a memory location of a memory device generates a result logic value. The result logic value provided by... Agent: Hewlett Packard Company

20080101138 - Methods of operating non-volatile memory devices to generate data strobe signals during data reading and related devices: A non-volatile memory device includes a latch unit, a non-volatile memory cell array configured to store data, and a control unit. The control unit is configured to receive a read command and a read address output from a memory controller, generate a data strobe signal based on the received read... Agent: Myers Bigel Sibley & Sajovec

20080101141 - Method of arranging fuses in a fuse box of a semiconductor memory device and a semiconductor memory device including such an arrangement: A semiconductor memory device may include a memory cell array and at least one fuse box. The memory cell array may include a plurality of sub-array blocks, and a fuse box may include a plurality of fuse groups, each group corresponding to a sub-array block. Each fuse group may have... Agent: Harness, Dickey & Pierce, P.L.C

20080101142 - Semiconductor memory device and method of testing same: Provided is a semiconductor memory device in which it is possible to conduct a parallel test by comparison with an expected value after replacement with a redundant cell. A redundant circuit provided in correspondence with each of a plurality of redundant addresses includes a determination circuit for determining whether an... Agent: Foley And Lardner LLP Suite 500

20080101143 - Memory device with configurable delay tracking: A memory device with configurable delay tracking is described. The memory device includes M normal word line drivers, a dummy word line driver a memory array, N sense amplifiers, and a timing control circuit. The memory array includes M rows and N columns of memory cells and a column of... Agent: Qualcomm Incorporated

20080101144 - High program speed mlc memory: Methods and apparatus are provided for programming a flash multiple level memory cell (MLC) memory. The method may include loading data into an SRAM. The method may include reading a plurality of multiple-bit words from the data in the SRAM and loading the words into at least one latch buffer... Agent: Finnegan, Henderson, Farabow, Garrett & Dunner LLP

20080101145 - Method of providing optimal field programming of electronic fuses: A method of providing optimal fuse programming conditions by which an integrated circuit chip customer may program electronic fuses in the field, i.e., outside of the manufacturing test environment. An optimal fuse programming identifier, which is correlated to optimal fuse programming conditions, may be provided to the customer in readable... Agent: Downs Rachlin Martin PLLC

20080101146 - One-time-programmable logic bit with multiple logic elements: A memory cell with a logic bit has a first one-time-programmable (“OTP”) memory element providing a first OTP memory element output and a second OTP memory element providing a second OTP memory element output. A logic operator coupled to the first OTP memory element output and to the second OTP... Agent: Xilinx, Inc Attn: Legal Department

20080101147 - Clock and power fault detection for memory modules: A system, method and apparatus for clock and power fault detection for a memory module is provided. In one embodiment, a system is provided. The system includes a voltage detection circuit and a clock detection circuit. The system further includes a controller coupled to the voltage detection circuit and the... Agent: Perkins Coie LLP

20080101148 - Memory row decoder: A memory row decoder is disclosed, comprising a first depletion NMOS transistor having a second source/drain coupled to a first partially decoded signal, and a gate coupled to a second partially decoded signal, a first enhancement PMOS transistor having a second source/drain coupled to the second partially decoded signal, and... Agent: Birch Stewart Kolasch & Birch

20080101149 - Hierarchical decoding of dense memory arrays using multiple levels of multiple-headed decoders: A memory array comprising array lines of first and second types coupled to memory cells includes a first hierarchical decoder circuit for decoding address information and selecting one or more array lines of the first type. The first hierarchical decoder circuit includes at least two hierarchical levels of multi-headed decoder... Agent: Zagorin O'brien Graham LLP (023)

20080094869 - Semiconductor memory device layout comprising high impurity well tap areas for supplying well voltages to nwells and pwells: A semiconductor device includes a plurality of memory cells, and an error-correction circuit. Its write operation is performed by a late-write method, and ECC processing is executed in parallel with writing to shorten a cycle time. Moreover, when a memory cell is power-supplied through a well tap, the same address... Agent: Stanley P. Fisher Reed Smith LLP

20080094870 - Semiconductor memory device: A semiconductor memory device includes a memory cell array and peripheral control circuits. In each of the peripheral control circuits, a plurality of transistors are arranged at a substantially constant transistor pitch in a first direction which is the row direction or the column direction of the memory cell array.... Agent: Mcdermott Will & Emery LLP

20080094871 - Sequential and video access for non-volatile memory arrays: An array of non-volatile memory cells arranged in logical columns and logical rows, and associated circuitry to enable reading or writing one or more memory cells on a row in parallel. In some embodiments, the array of memory cells may include a phase change material. In some embodiments, the circuitry... Agent: Ovonyx, Inc

20080094872 - Method for forming organic layer pattern, organic layer pattern prepared by the same and organic memory devices comprising the pattern: Disclosed are a method for forming an organic layer pattern which is characterized by forming a thin layer by coating a coating solution including a polyimide-based polymer having a heteroaromatic pendant group including a heteroatom in its polyimide major chain, a photoinitiator and a crosslinking agent on a substrate and... Agent: Harness, Dickey & Pierce, P.L.C

20080094873 - Method and apparatus for non-volatile multi-bit memory: A memory device that selectably exhibits first and second logic levels. A first conductive material has a first surface with a first memory layer formed thereon, and a second conductive material has a second surface with a second memory layer formed thereon. A connective conductive layer joins the first and... Agent: Macronix C/o Haynes Beffel & Wolfeld LLP

20080094875 - Methods of operating a bistable resistance random access memory with multiple memory layers and multilevel memory states: A method is described for operating a bistable resistance random access memory having two memory layer stacks that are aligned in series is disclosed. The bistable resistance random access memory comprises two memory layer stacks per memory cell, the bistable resistance random access memory operates in four logic states, a... Agent: Macronix C/o Haynes Beffel & Wolfeld LLP

20080094874 - Multiple-read resistance-variable memory cell structure and method of sensing a resistance thereof: Disclosed herein is a multiple read-port nonvolatile memory cell structure, and related method of sensing a resistance state of memory cell, for high-speed and high-bandwidth applications. It provides about a 2× bandwidth gain over conventional cells during the read cycle in embodiments where two read ports are constructed. For example,... Agent: Baker & Mckenzie On Behalf Of Tsmc

20080094876 - Sensing a signal in a two-terminal memory array having leakage current: A two-terminal memory array includes a plurality of first and second conductive traces. An address unit operatively applies a select voltage across a selected pair of the first and second conductive traces and applies a non-select voltage potential to unselected traces. A total current flowing in the selected first conductive... Agent: Unity Semiconductor Corporation

20080094877 - Faster initialization of dram memory: A method of initializing dynamic random access memory (DRAM) comprises allocating one or more rows of a plurality of cells in the DRAM; signaling an initialization request to initialize the allocated one or more rows; and simultaneously initializing all cells in each of the one or more allocated rows upon... Agent: Honeywell International Inc.

20080094878 - Ring oscillator row circuit for evaluating memory cell performance: A ring oscillator row circuit for evaluating memory cell performance provides for circuit delay and performance measurements in an actual memory circuit environment. A ring oscillator is implemented with a row of memory cells and has outputs connected to one or more bitlines along with other memory cells that are... Agent: Ibm Corporation (mh) C/o Mitch Harris, Attorney At Law, L.L.C.

20080094879 - Semiconductor memory device: A storage node voltage control circuit is added to a memory cell including two load transistors, two drive transistors and two access transistors. The storage node voltage control circuit performs control so that in writing data into the memory cell, a voltage at one of the two storage nodes holding... Agent: Mcdermott Will & Emery LLP

20080094881 - Hybrid memory cell for spin-polarized electron current induced switching and writing/reading process using such memory cell: A magnetoresistive hybrid memory cell includes first and second stacked structures. The first stacked structure includes a magnetic tunnel junction including first and second magnetic regions stacked in a parallel, overlying relationship separated by a layer of non-magnetic material, wherein the first magnetic region has a fixed first magnetic moment... Agent: Edell , Shapiro & Finnan , LLC

20080094883 - Magnetic memory: To provide a magnetic memory capable of reducing the amount of write current, even when the element size is 0.7 μm or less. Each of storage areas has a transistor for read/write control, which is connected electrically to either one of the fixed layer and the free layer of each... Agent: Oliff & Berridge, PLC

20080094880 - Magneto-resistance element and magnetic random access memory: A magneto-resistance element includes a free layer, a fixed layer and a non-magnetic layer interposed between the free layer and the fixed layer. The free layer has a first magnetic layer, a second magnetic layer, a third magnetic layer, a first non-magnetic layer interposed between the first magnetic layer and... Agent: Sughrue Mion, PLLC

20080094882 - Non-volatile memory device: A non-volatile memory device according to one embodiment comprises a plurality of memory cells each comprising a magneto resistive element and a selection transistor; wherein at least some of the memory cells are arranged into a two dimensional array; a first interconnect line extending in a first direction of the... Agent: Zilka-kotab, PC- Ibm

20080094884 - Reference cell scheme for mram: An MRAM reference cell sub-array provides a mid-point reference current to sense amplifiers. The MRAM reference cell sub-array has MRAM cells arranged in rows and columns. Bit lines are associated with each column of the sub-array. A coupling connects the bit lines of pairs of the columns together at a... Agent: Saile Ackerman LLC

20080094885 - Bistable resistance random access memory structures with multiple memory layers and multilevel memory states: A bistable resistance random access memory comprises a plurality of memory cells where each memory cell having multiple memory layer stack. Each memory layer stack includes a conductive layer overlying a programmable resistance random access memory layer. A first memory layer stack overlies a second memory layer stack, and the... Agent: Macronix C/o Haynes Beffel & Wolfeld LLP

20080094886 - Non-uniform switching based non-volatile magnetic based memory: One embodiment of the present invention includes a non-uniform switching based non-volatile magnetic memory element including a fixed layer, a barrier layer formed on top of the fixed layer, a first free layer formed on top of the barrier layer, a non-uniform switching layer (NSL) formed on top of the... Agent: Law Offices Of Imam

20080094887 - Semiconductor device using magnetic domain wall movement and method of manufacturing the same: A semiconductor device using a magnetic domain wall movement and a method of manufacturing the semiconductor device are provided. The semiconductor device includes a magnetic layer that is formed on a substrate and has a plurality of magnetic domains, and a unit that supplies energy to move a magnetic domain... Agent: Sughrue Mion, PLLC

20080094888 - Magnetic tunnel junction devices and magnetic random access memory: A magnetic random access memory (MRAM) is disclosed. The MRAM includes a first electrode, an antiferromagnetic layer formed over the first electrode, a pinned layer formed over the antiferromagnetic layer, a barrier layer formed over the pinned layer, a composite free layer formed over the barrier layer, and a second... Agent: Quintero Law Office, PC

20080094889 - Semiconductor integrated circuit: The present invention provides an integrated circuit capable of reducing a leak current and reliably holding data therein in a standby mode. A potential higher than a potential of a second source line is supplied to a first source line. A potential lower than a potential of a first ground... Agent: Volentine & Whitt PLLC

20080094892 - Method for protecting memory cells during programming: Improved circuitry and methods for programming memory cells of a memory device are disclosed. The improved circuitry and methods operate to protect the memory cells from potentially damaging electrical energy that can be imposed during programming of the memory cells. Additionally, the improved circuitry and methods operate to detect when... Agent: Technology & Innovation Law Group, PC

20080094893 - Nonvolatile memory system and associated programming methods: A nonvolatile memory system includes a host system, a memory controller, and a flash memory chip including multi-level flash memory cells. The memory controller includes a backup memory adapted to store a backup copy of previously programmed data from the multi-level flash memory cells when further programming of the multi-level... Agent: Volentine & Whitt PLLC

20080094891 - Parallel threshold voltage margin search for mlc memory application: A method for determining read voltage margins in a memory array compares as-read sum codes generated from data read from the memory array with expected sum codes generated from the loaded data. The read voltage (Vt) is stepped and the as-read sum codes are compared to the expected sum codes... Agent: Macronix C/o Haynes Beffel & Wolfeld LLP

20080094894 - Nonvolatile semiconductor memory and memory system: A nonvolatile semiconductor memory includes a plurality of memory cells each configured to store M bits of data, where M is an integer greater than 1. In addition, the memory includes a selection circuit configured to select a first or second mode according to an instruction from outside of the... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20080094895 - Non-volatile memory device and method of fabricating the same: A non-volatile memory device, and method of forming the same, increases or maximizes the performance of an ultramicro-structured device. In one embodiment, a non-volatile memory device comprises a first word line and a second word line insulated from each other and positioned to intersect each other with a vacant space... Agent: Mills & Onello LLP

20080094896 - Non volatile memory rad-hard (nvm-rh) system: The embodiments of the invention provide an apparatus, method, etc. for a non volatile memory RAD-hard (NVM-rh) system. More specifically, an IC permanent non-volatile storage element comprises an integrated semiconductor stable reference component, wherein the component is resistant to external radiation. The storage element further comprises e-fuse structures in the... Agent: Frederick W. Gibb, Iii Gibb & Rahman, LLC

20080094897 - Non-volatile semiconductor memory device and method for recovering data in non-volatile semiconductor memory device: A method and device for recovering data in a non-volatile semiconductor memory device that may include controlling a reference current by the non-volatile semiconductor memory device, reading data of at least one memory cell based on the controlled reference current, storing the read data in a buffer memory, and writing... Agent: Harness, Dickey & Pierce, P.L.C

20080094899 - Non-volatile semiconductor memory device: A non-volatile semiconductor memory device, allocates data contained in an ECC frame as a first data group to be stored in a first memory cell group composed of a plurality of first memory cells selected by a first word line and a second data group to be stored in a... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20080094898 - Non-volatile semiconductor storage device: A memory cell array includes a plurality of non-volatile semiconductor memory elements, each memory element storing data in a non-volatile manner. A shift register stores data read from the semiconductor memory element and sequentially transfers the data outside, the shift register also stores data transferred from outside and stores the... Agent: Amin, Turocy & Calvin, LLP

20080094900 - Nonvolatile semiconductor memory: A nonvolatile semiconductor memory according to an example of the present invention includes first and second word lines extending in a first direction and having the same row address, a first block including the first word line and having a first block address, a second block including the second word... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20080094901 - Flash memory device capable of preventing coupling effect and program method thereof: The present invention provides a flash memory device that comprises a word line; even page cells that are physically adjacent and connected to the word line; and odd page cells that are physically adjacent and connected to the word line, wherein at a program operation, page data is programmed in... Agent: Mills & Onello LLP

20080094902 - Flash memory devices and methods of operating the same: A memory cell array includes a NAND string formed of a plurality of memory cells coupled in series between a string selection transistor and a ground selection transistor. The string selection transistor controls an electrical connection between the NAND string and a bit line based on a string selection voltage... Agent: Harness, Dickey & Pierce, P.L.C

20080094903 - Nand flash memory: A NAND flash memory, in a read operation, a p-type semiconductor substrate is set at a ground potential, a bit line is charged to a first voltage, a source line, a n-type well and a p-type well are charged to a second voltage, which lies between a ground potential and... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20080094904 - Flash memory device operating at multiple speeds: A method of operating a flash memory device includes a first operating mode and a second operating mode having different operating speeds. Each one of the first and second operating modes includes a bit line set-up interval and at least one additional interval. The flash memory is divided into first... Agent: Volentine & Whitt PLLC

20080094905 - Nonvolatile memory: A nonvolatile memory includes circuits each having first control transistors, memory transistors, second control transistors and memory transistors repeatedly connected in series in sequence. Inversion layers are formed in the direction intersecting the serial direction with turning on of the control transistors. A selection circuit selects a connection of the... Agent: Miles & Stockbridge PC

20080094906 - Voltage regulator for the programming circuit of a memory cell: A voltage regulator connected to a memory cell is configured by identifying at least a first and a second operation regions of the cell and associating the first and second operation regions with respective first and second operation conditions of the memory cell. An operative condition of the memory cell... Agent: Gardere Wynne Sewell LLP Intellectual Property Section

20080094890 - Semiconductor memory device and data write and read method thereof: A semiconductor memory device includes a memory cell array including a plurality of memory banks, an address input portion which receives a row address and a column address through address pins during a normal mode operation and which receives the row address, the column address and write data through the... Agent: Volentine & Whitt PLLC

20080094907 - Flash memories with adaptive reference voltages: Cells of a flash memory are read by determining respective adaptive reference voltages for the cells and comparing the cells' threshold voltages to their respective reference voltages. The adaptive reference voltages are determined either from analog measurements of the threshold voltages of the cells' neighbors or from preliminary estimates of... Agent: Mark M. Friedman

20080094909 - Low power multiple bit sense amplifier: A sense amplifier for multiple level flash memory cells is comprised of a voltage ramp generator that generates a ramp voltage signal. Reference sense amplifiers compare an input reference current to a ramp current generated from the ramp voltage signal. When the ramp voltage signal is greater than the reference... Agent: Attn: Kenneth W. Bolvin Leffert Jay & Polglaze, P.A.

20080094908 - Temperature compensation of voltages of unselected word lines in non-volatile memory based on word line position: Reading and verify operations are performed on non-volatile storage elements using temperature-compensated read voltages for unselected word lines, and/or for select gates such as drain or source side select gates of a NAND string. In one approach, while a read or verify voltage is applied to a selected word line,... Agent: Vierra Magen Marcus & Deniro LLP

20080094910 - Flash memory device and program method thereof: A method of programming a plurality of memory cells in a flash memory device from a first state to a second state includes verifying the plurality of memory cells using a verify voltage having a level increased according to an increase in a program loop number; and programming the plurality... Agent: F. Chau & Associates, LLC

20080094911 - Non-volatile memory with improved program-verify operations: In programming a non-volatile memory involving alternately applying a programming pulse and verifying the programming, time is saved in the program verify portion when, depending on the states of the memory cells, a portion of the verify operation is recognized to be superfluous and skipped. Preferably, in a program verify... Agent: Davis Wright Tremaine LLP - Sandisk Corporation

20080094912 - Selective slow programming convergence in a flash memory device: A plurality of memory cells are programmed with incrementally increased programming pulses applied to word lines to which the memory cells are coupled. After each pulse, a verify operation determines the threshold voltage for each cell. When the threshold voltage reaches a pre-verify threshold, only the bit line connected to... Agent: Leffert Jay & Polglaze, P.A.

20080094913 - Memory device for protecting memory cells during programming: Improved circuitry and methods for programming memory cells of a memory device are disclosed. The improved circuitry and methods operate to protect the memory cells from potentially damaging electrical energy that can be imposed during programming of the memory cells. Additionally, the improved circuitry and methods operate to detect when... Agent: Beyer Weaver LLP

20080094914 - Methods of restoring data in flash memory devices and related flash memory device memory systems: Methods for setting a read voltage in a memory system which comprises a flash memory device and a memory controller for controlling the flash memory device, comprise sequentially varying a distribution read voltage to read page data from the flash memory device; constituting a distribution table having a data bit... Agent: Myers Bigel Sibley & Sajovec

20080094916 - Memory device for controlling current during programming of memory cells: Improved circuitry and methods for programming memory cells of a memory device are disclosed. The improved circuitry and methods operate to isolate the memory cells from potentially damaging electrical energy that can be imposed during a precharge phase that precedes programming of the memory cells. Additionally, the improved circuitry and... Agent: Beyer Weaver LLP

20080094915 - Method for controlling current during programming of memory cells: Improved circuitry and methods for programming memory cells of a memory device are disclosed. The improved circuitry and methods operate to isolate the memory cells from potentially damaging electrical energy that can be imposed during a precharge phase that precedes programming of the memory cells. Additionally, the improved circuitry and... Agent: Beyer Weaver LLP

20080094917 - Method of operating a semiconductor memory device having a recessed control gate electrode: A semiconductor memory device may include a semiconductor substrate, a control gate electrode recessed in the semiconductor substrate, a storage node layer between the control gate electrode and the semiconductor substrate, a tunneling insulating layer between the storage node layer and the semiconductor substrate, a blocking insulating layer between the... Agent: Harness, Dickey & Pierce, P.L.C

20080094918 - Memory read control circuit and control method thereof: A control circuit to which a read requirement signal for data read of a memory and a burst length information signal for the read requirement are input controls a pull-up circuit so as to pull-up a data strobe signal if the read requirement signal is active. A mask signal is... Agent: Mcginn Intellectual Property Law Group, PLLC

20080094919 - Noise resistant small signal sensing circuit for a memory device: Apparatus and method for data sensing circuitry that uses averaging to sense small differences in signal levels representing data states. The apparatus periodically switches the coupling of input terminals and output terminals of an integrator circuit from a first configuration to a second configuration, where the second configuration changes the... Agent: Dorsey & Whitney LLP Intellectual Property Department

20080094920 - Memory and low offset clamp bias circuit thereof: A memory and a low offset clamp bias circuit thereof are provided. The low offset clamp bias circuit is adapted for any existing memory and is used for reducing the variation of a drain side voltage Vd supplied to a memory cell in a memory cell array area through the... Agent: J C Patents, Inc.

20080094921 - Semiconductor storage device: A semiconductor storage device according to the present invention comprises a plurality of memory cells each provided with an access transistor in which a source is connected to a bit line and a gate is connected to a word line and a capacitor in which a storage electrode is connected... Agent: Mcdermott Will & Emery LLP

20080094922 - Semiconductor device: A column circuit that amplifies signals read from a sense amplifier array SAA to local input/output lines LIO in sub-amplifiers SAMP to transfer the amplified signals to main input/output lines MIO is provided. A current control circuit IC that can set one of two kinds of currents according to read... Agent: Miles & Stockbridge PC

20080094923 - Non-volatile memory device capable of reducing threshold voltage distribution: A method for programming a flash memory device which includes a plurality of memory cells arranged in rows and columns. The method includes programming selected memory cells from among the plurality of memory cells according to loaded data bits. Data bits are read from the programmed selected memory cells. It... Agent: Frank Chau, Esq. F. Chau & Associates, LLC

20080094924 - Memory device having selectively decoupleable memory portions and method thereof: In response to determining a bit cell of a bit cell array of a memory device is a defective bit cell, a portion of the bit cell array including the defective bit cell is decoupled from a power source of the memory device. The portion can be decoupled via a... Agent: Larson Newman Abel Polansky & White, LLP

20080094925 - Soft error robust static random access memory cells: A Static Random Access Memory (SRAM) cell is provided with an improved robustness to radiation induced soft errors. The SRAM cell comprises the following elements. First and second storage nodes are configured to store complementary voltages. Access transistors are configured to selectively couple the first and second storage nodes to... Agent: Gowling Lafleur Henderson LLP

20080094926 - Portable device for storing private information such as medical, financial or emergency information: A portable housing capable of being carried by a certain person includes a circuit. The circuit includes a memory for storing private data concerning that certain person, a circuit operable to effectuate storage of the private data in the memory in a secure manner, and a processing unit operable to... Agent: Stmicroelectronics, Inc.

20080094927 - Flash memory device with word line discharge unit and data read method thereof: Exemplary embodiments of the present invention provide a flash memory device which includes a memory cell array. A decoder circuit is connected to the memory cell array via a plurality of select lines and a plurality of word lines. The detector circuit supplies voltages for a read operation to the... Agent: Frank Chau, Esq. F. Chau & Associates, LLC

20080094928 - Semiconductor memory having data line separation switch: A semiconductor memory comprises a data line separation switch circuit, which controls connection and separation of digit lines DT/DB connected to a memory cell and sense amplifier, and a control circuit, which performs a control of switching the data line separation switch circuit from turning-on to turning-off according to the... Agent: Mcginn Intellectual Property Law Group, PLLC

20080094929 - Two-cycle sensing in a two-terminal memory array having leakage current: A two-terminal memory array includes a plurality of first and second conductive traces. An address unit operatively applies a select voltage across a selected pair of the first and second conductive traces and applies a non-select voltage potential to unselected traces. A total current flowing in the selected first conductive... Agent: Unity Semiconductor Corporation

20080094930 - Temperature compensation of select gates in non-volatile memory: Reading and verify operations are performed on non-volatile storage elements using temperature-compensated read voltages for unselected word lines, and/or for select gates such as drain or source side select gates of a NAND string. In one approach, while a read or verify voltage is applied to a selected word line,... Agent: Vierra Magen/sandisk Corporation

20080094931 - Memory device performing partial refresh operation and method thereof: The present invention provides a memory device which comprises a memory cell array having a plurality of memory blocks; a memory controller for controlling a refresh operation with respect to the memory blocks; a refresh check bit storing part for storing refresh check bits corresponding to the memory blocks, respectively;... Agent: Mills & Onello LLP

20080094933 - Low-power dram and method for driving the same: A dynamic random access memory includes: an address latch configured to latch a row address in response to a row address strobe (RAS) signal and latch a column address in response to a column address strobe (CAS) signal; a row decoder configured to decode the row address; an enabler configured... Agent: Mcdermott Will & Emery LLP

20080094932 - Semiconductor memory device and methods thereof: A semiconductor memory device and methods thereof are provided. The example semiconductor memory device may include an internal address generating circuit operating in accordance with a first addressing protocol during normal operation and operating in accordance with a second addressing protocol during a test operation, the first addressing protocol associated... Agent: Harness, Dickey & Pierce, P.L.C

20080089106 - Memory circuit and semiconductor device: A semiconductor circuit of the invention comprises: a memory cell array including a plurality of memory cells formed at intersections between a plurality of word lines and a plurality of bit lines; a plurality of sense amplifiers each for amplifying data of the memory cell connected to a selected word... Agent: Mcginn Intellectual Property Law Group, PLLC

20080089104 - Semiconductor memory device and method for fabricating semiconductor memory device: According to an aspect of the present invention, there is provided a semiconductor memory device, including, a semiconductor substrate, a phase-change element formed on the semiconductor substrate, the phase-change element including a phase-change film and electrode films, a joule heat portion contacting with the electrode film, the phase-change film being... Agent: Finnegan, Henderson, Farabow, Garrett & Dunner LLP

20080089107 - Memory chip architecture with high speed operation: A semiconductor memory device includes at least one data transmission block including data I/O pads arranged in a major-axis side of the semiconductor memory device; a command and address transmission block including address and command input pads arranged in at least one minor-axis side of the semiconductor memory device; a... Agent: Blakely Sokoloff Taylor & Zafman

20080089105 - Variable resistance memory device and method of manufacturing the same: A variable resistance memory device includes a substrate, a plurality of active lines formed on the substrate, are uniformly separated, and extend in a first direction, a plurality of switching devices formed on the active lines and are separated from one another, a plurality of variable resistance devices respectively formed... Agent: F. Chau & Associates, LLC

20080089108 - Probe-based storage device: In one embodiment, the present invention includes an apparatus having a conductive storage medium to store information in the form of electrostatic charge. The conductive storage medium can be disposed in a non-conductive layer that is formed over a charge blocking layer, which in turn may be disposed over an... Agent: Trop Pruner & Hu, PC

20080089109 - Ferroelectric memory: A ferroelectric memory comprises a memory cell block of plural serially connected memory cells each including a cell transistor and a ferroelectric capacitor connected in parallel therewith. And the ferroelectric memory comprises a cell transistor resistance measuring circuit, a word line voltage controller, and a word line voltage generator. The... Agent: Banner & Witcoff, Ltd. Attorneys For Client No. 000449, 001701

20080089110 - Crossbar-memory systems and methods for writing to and reading from crossbar memory junctions of crossbar-memory systems: Various embodiments of the present invention are directed to crossbar-memory systems to methods for writing information to and reading information stored in such systems. In one embodiment of the present invention, a crossbar-memory system comprises a first layer of microscale signal lines, a second layer of microscale signal lines, a... Agent: Hewlett Packard Company

20080089111 - Resistance type memory device and fabricating method and operating method thereof: A resistance type memory device is provided. The resistance type memory device is disposed on a substrate and includes a tungsten electrode, an upper electrode, and a tungsten oxide layer. The upper electrode is disposed on the tungsten electrode. The tungsten oxide layer is sandwiched between the tungsten electrode and... Agent: J C Patents, Inc.

20080089112 - Memory element and memory device comprising memory layer positioned between first and second electrodes: A memory element 10 includes a memory layer 4 positioned between a first electrode 2 and a second electrode 6, in which an element selected from Cu, Ag, and Zn is contained in the memory layer 4 or in a layer 3 in contact with the memory layer 4, a... Agent: Wolf Greenfield & Sacks, P.C.

20080089113 - Organic-complex thin film for nonvolatile memory applications: An electronic or electro-optic device according to an embodiment of this invention has a first electrode, a second electrode spaced apart from the first electrode, and an organic composite layer disposed between the first electrode and the second electrode. The organic composite layer is composed of an electron donor material,... Agent: Venable LLP

20080089114 - Memory cell array: A memory cell array includes memory cells, bit lines running along a first direction, word lines running along a second direction perpendicular to the first direction, and continuous active area lines, wherein transistors are at least partially formed in the active area lines. The transistors electrically couple corresponding memory cells... Agent: Edell, Shapiro & Finnan, LLC

20080089115 - Semiconductor memory device: In a multiport SRAM memory cell of the present invention, an access transistor of a first port is disposed in a p-type well, and an access transistor of a second port is disposed in a p-type well. The gates of all of transistors disposed in a memory cell extend in... Agent: Mcdermott Will & Emery LLP

20080089116 - Sram voltage control for improved operational margins: A static random access memory (“SRAM”) is provided which includes a plurality of SRAM cells arranged in an array having a plurality of portions. The SRAM includes a plurality of voltage control circuits corresponding to respective ones of the plurality of portions of the array. Each of the plurality of... Agent: International Business Machines Corporation Dept. 18g

20080089118 - Magnetic random access memory and method of manufacturing the same: A magnetic random access memory includes a magnetoresistive effect element having a fixed layer in which a magnetization direction is fixed, a recording layer in which a magnetization direction is reversible, and a nonmagnetic layer formed between the fixed layer and the recording layer, a hollow portion being formed in... Agent: Finnegan, Henderson, Farabow, Garrett & Dunner LLP

20080089117 - Memory cell and magnetic random access memory: A memory cell is used which includes a plurality of magneto-resistive elements and a plurality of laminated ferrimagnetic structure substances. The plurality of the magneto-resistive elements are placed corresponding to respective positions where a plurality of first wirings extended in a first direction intersects with a plurality of second wirings... Agent: Sughrue Mion, PLLC

20080089119 - Offset compensated sensing for magnetic random access memory: An offset compensated memory element voltage supply including a differential amplifier with a compensation circuit, and a transistor with a gate connected to the output of the differential amplifier. The compensation circuit of the differential amplifier includes a compensation capacitor that stores a compensation voltage during a calibration phase, and... Agent: Dickstein Shapiro LLP

20080089120 - Resistive memory devices having a cmos compatible electrolyte layer and methods of operating the same: Example embodiments may provide a resistive memory having an amorphous solid electrolyte layer and/or a method of operating the memory. The resistive memory may include a switching device and/or a storage node connected to the switching device. The storage node may include a lower electrode, an upper electrode crossing the... Agent: Harness, Dickey & Pierce, P.L.C

20080089121 - Semiconductor memory device and method of controlling the same: A semiconductor memory device comprising: first and second wirings arranged in a matrix; and a memory cell being provided at an intersecting point of the first and second wirings and including a resistance change element and an ion conductor element connected to each other in a cascade arrangement between the... Agent: Finnegan, Henderson, Farabow, Garrett & Dunner LLP

20080089123 - Method for programming a multi-level non-volatile memory device: A method for programming multi-level non-volatile memory. A plurality of multi-bit storage cells capable of storing different levels of charge usable to represent data represented by a least significant bits (LSBs) and a most significant bits (MSBs) are programmed first with LSBs and then with MSBs. The programmed storage cells... Agent: F. Chau & Associates, LLC

20080089124 - Removable data storage device and method: Applicant's teachings relate to a removable data storage device and method. Various embodiments of applicant's teachings show a removable data storage device comprising an external connector to removably connect the data storage device to a computing device, a memory device mounted on a first printed circuit board, a flexible connector... Agent: Bereskin And Parr

20080089125 - Memory device: An embodiment of a non-volatile memory device is provided. The memory device includes a memory matrix comprising a plurality of memory cells, arranged according to a plurality of rows and a plurality of columns. The memory device further includes a plurality of word lines; each word line is associated with... Agent: Graybeal Jackson Haley LLP Bryan A. Santarelli

20080089126 - Circuitry for reliability testing as a function of slew: A reliability test chain includes: a stress chain; and transition time control circuits coupled to tap points along the stress chain such that transition times of a signal on the stress chain are controlled.... Agent: Texas Instruments Incorporated

20080089129 - Flash memory device with flexible address mapping scheme: A flash memory device includes a flash memory cell array which includes a plurality of memory cells arranged in rows and columns, reading and programming circuitry configured to read data from and program data into the memory cells of the flash memory cell array, and a control logic block configured... Agent: Volentine & Whitt PLLC

20080089127 - Non-volatile memory with dual voltage select gate structure: A select gate structure for a non-volatile storage system include a select gate and a coupling electrode which are independently drivable. The coupling electrode is adjacent to a word line in a NAND string and has a voltage applied which reduces gate induced drain lowering (GIDL) program disturb of an... Agent: Vierra Magen/sandisk Corporation

20080089128 - Programming non-volatile memory with dual voltage select gate structure: A select gate structure for a non-volatile storage system include a select gate and a coupling electrode which are independently drivable. The coupling electrode is adjacent to a word line in a NAND string and has a voltage applied which reduces gate induced drain lowering (GIDL) program disturb of an... Agent: Vierra Magen/sandisk Corporation

20080089130 -