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Static information storage and retrievalBelow are recently published patent applications awaiting approval from the USPTO. Recent week's RSS XML file available below.
Listing for abstract view: USPTO application #, Title, Abstract excerpt,Patent Agent. Listing format for list view: USPTO National Class full category number, title of the patent application. 04/10/2014 > 36 patent applications in 26 patent subcategories.
20140098589 - Replacement of a faulty memory cell with a spare cell for a memory circuit: A memory interface circuit device comprising a data structure configured to match and substitute an address in a run-time.... Agent: Inphi Corporation
20140098590 - Volatile memory access via shared bitlines: A memory includes an array of memory cells that form rows and columns. The rows of the array include memory cell pairs. The memory cells may include two cross-coupled inverters and two pass-devices that couple to alternate sides of the cross-coupled inverters. The two memory cells of a memory cell... Agent: International Business Machines Corporation
20140098591 - Antifuse otp memory cell with performance improvement prevention and operating method of memory: Provided is an OTP memory cell including a first antifuse unit, a second antifuse unit, a select transistor, and a well region. The first and the second antifuse unit respectively include an antifuse layer and an antifuse gate disposed on a substrate in sequence. The select transistor includes a select... Agent: Ememory Technology Inc.
20140098592 - Resistive memory device including compensation resistive device and method of compensating resistance distribution: A resistive memory device includes a memory cell array, an input/output (I/O) sense amplifier unit, an address input buffer, a row decoder, and a column decoder. The memory cell array includes unit memory cells, and operates in response to a word line driving signal and a column selecting signal, each... Agent:
20140098594 - Cross point variable resistance nonvolatile memory device: Each memory cell is formed at a different one of cross points of bit lines extending in an X direction and formed in a plurality of layers and word lines extending in a Y direction. In a multilayer cross point structure in which a plurality of vertical array planes sharing... Agent: Panasonic Corporation
20140098593 - Drift acceleration in resistance variable memory: The present disclosure includes apparatuses and methods including drift acceleration in resistance variable memory. A number of embodiments include applying a programming signal to the resistance variable memory cell to program the cell to a target state, subsequently applying a pre-read signal to the resistance variable memory cell to accelerate... Agent: Micron Technology, Inc.
20140098595 - Non-volatile memory device: A non-volatile memory device includes: a memory cell array including a plurality of memory cells each including a first variable resistance element and a first current steering element and a parameter generation circuit including a reference cell including a second variable resistance element and a second current steering element having... Agent: Panasonic Corporation
20140098596 - 8-transistor dual-ported static random access memory: An 8-transistor SRAM (static random access memory) storage cell provides differential read bit lines that are precharged to a low voltage level for read operations. The 8-transistor storage cell provides separate ports for read and write operations, including differential read bit lines. Prior to each read operation, the differential read... Agent: Nvidia Corporation
20140098597 - Single-ended volatile memory access: A memory includes an array of memory cells that form rows and columns. The rows include memory cell pairs. The memory cells may include two cross-coupled inverters and two pass-devices that couple to alternate sides of the cross-coupled inverters. For a read operation, a wordline drive circuit selects one memory... Agent: International Business Machines Corporation
20140098598 - Memory cell array latchup prevention: A current-limiting device may be configured to be placed along a power-supply bus to limit current through a first complimentary-metal-oxide semiconductor (CMOS) circuit coupled to the power-supply bus so that current does not exceed a trigger current level of a pnpn diode in a second CMOS circuit coupled to the... Agent: Cypress Semiconductor Corporation
20140098601 - Main memory system storing operating system program and computer system including the same: A main memory system is provided which includes a nonvolatile memory including a first memory area designated to store an operating system program and a second memory area designated to store user data; and a memory controller configured to control the nonvolatile memory such that the operating system program is... Agent:
20140098602 - Method and apparatus of probabilistic programming multi-level memory in cluster states of bi-stable elements: A probabilistic programming current is injected into a cluster of bi-stable probabilistic switching elements, the probabilistic programming current having parameters set to result in a less than unity probability of any given bi-stable switching element switching, and a resistance of the cluster of bi-stable switching elements is detected. The probabilistic... Agent:
20140098600 - Semiconductor memory device having discriminary read and write operations according to temperature: A semiconductor memory device is provided which includes a memory cell array including magnetic memory cells arranged in a matrix form of rows and columns and connected with bit lines and a source line; and a temperature sensing unit configured to generate a temperature sensing signal by sensing a temperature... Agent:
20140098599 - Semiconductor memory device with data path option function: A semiconductor memory device may include a memory cell, a bit line connected to the memory cell, a bit line data latch circuit configured to sense-amplify data stored in the memory cell connected to the bit line and to store write data in the memory cell via the bit line;... Agent:
20140098604 - Immunity of phase change material to disturb in the amorphous phase: Disturb from the reset to the set state may be reduced by creating an amorphous phase that is substantially free of crystal nuclei when programming the reset state in a phase change memory. In some embodiments, this can be achieved by using a current or a voltage to program that... Agent: Ovonyx, Inc.
20140098603 - Reliable set operation for phase-change memory cell: A Phase-Change Memory (PCM) device and a method of writing data to the PCM device are described. The PCM device includes a multi-phase data storage cell having at least a Set state and a Reset state that may be established using a heater configured to heat the data storage cell.... Agent: Micron Technology, Inc.
20140098605 - Programmable memory with restricted reprogrammability: A reprogrammable memory, which can be, programmed a limited number of times. A plurality of one-time programmable elements are combined by a logic arrangement such that the output of that logic arrangement may be reprogrammed a limited number of times.... Agent: Cambridge Silicon Radio Limited
20140098606 - Reducing programming disturbance in memory devices: Apparatus and methods are disclosed, such as a method that includes precharging channel material of a string of memory cells in an unselected sub-block of a block of memory cells to a precharge voltage during a first portion of a programming operation. A programming voltage can then be applied to... Agent: Micron Technology, Inc.
20140098607 - Sensing memory cells: The present disclosure includes methods, devices, modules, and systems for operating memory cells. One method embodiment includes applying a ramping voltage to a control gate of a memory cell and to an analog-to-digital converter (ADC). The aforementioned embodiment of a method also includes detecting an output of the ADC at... Agent: Micron Technology, Inc.
20140098608 - Apparatus and methods to perform read-while write (rww) operations: Subject matter disclosed herein relates to methods and apparatus, such as memory devices and systems including such memory devices. In one apparatus example, a plurality of block configurations may be employed. Block configurations may include an arrangement of similarly doped semiconductor switches. Block configurations may select a respective tile of... Agent: Micron Technology, Inc.
20140098609 - Nonvolatile semiconductor memory apparatus: According to one embodiment, a nonvolatile semiconductor memory apparatus includes a memory cell array, a row decoder, a controller. The memory cell array includes a plurality of memory strings. The memory strings include a first select transistor and a second select transistor, and are connected to each of a plurality... Agent:
20140098610 - Erased state reading: Memory cells that are indicated as being erased but are suspected of being partially programmed may be subject to a verification scheme that first performs a conventional read and then, if the conventional read does not indicate partial programming, performs a second read using lower read-pass voltage on at least... Agent: Sandisk Technologies Inc
20140098611 - Biasing system and method: Embodiments are provided that include a memory system that includes a memory system, having an access device coupled between a global line and a local line and a voltage source coupled to the global line and configured to output a bias voltage on the global line when the memory system... Agent: Micron Technology, Inc.
20140098612 - Nonvolatile semiconductor memory device: A nonvolatile semiconductor memory device comprises multiple memory strings each including a plurality of first and second groups of serially connected memory cells, and a back gate transistor serially connected between the first and second groups of memory cells, a plurality of word lines, each word line being connected to... Agent: Kabushiki Kaisha Toshiba
20140098613 - Multi-port semiconductor memory device with multi-interface: A semiconductor memory device is provided which includes a first port configured to connect to a first processor and including a first interface circuit; a second port configured to connect to a second processor and including a second interface circuit; and a memory cell array including a first memory area... Agent:
20140098614 - Methods, devices, and systems for dealing with threshold voltage change in memory devices: The present disclosure includes methods, devices, and systems for dealing with threshold voltage change in memory devices. A number of embodiments include an array of memory cells and control circuitry having sense circuitry coupled to the array. The control circuitry is configured to determine changes in threshold voltages (Vts) associated... Agent: Micron Technology, Inc.
20140098615 - Latent slow bit detection for non-volatile memory: In accordance with at least one embodiment, a non-volatile memory (NVM) and method is disclosed for detecting latent slow erase bits. At least a portion of an array of NVM cells is erased with a reduced erase bias. The reduced erase bias has a reduced level relative to a normal... Agent: Freescale Semiconductor, Inc.
20140098616 - Method and apparatus for reducing read disturb in memory: Various aspects of a NAND memory include a control circuit that applies a read bias arrangement to a plurality of word lines to read a selected data value stored on a plurality of memory cells by measuring current flowing between the first end and the second end of the series... Agent: Macronix International Co., Ltd.
20140098619 - Non-volatile memory with overwrite capability and low write amplification: Providing for a non-volatile memory architecture having write and overwrite capabilities providing low write amplification to a storage system is described herein. By way of example, a memory array is disclosed comprising blocks and sub-blocks of two-terminal memory cells. The two-terminal memory cells can be directly overwritten in some embodiments,... Agent: Crossbar, Inc.
20140098617 - Package: A package includes a first die and a second die. An interface connects the first die and the second die. At least one of the first and second dies includes a memory. The interface is configured to transport both control signals and memory transactions. A multiplexing circuit multiplexes the control... Agent: Stmicroelectronics (research & Development) Limited
20140098618 - Method and apparatus for timing adjustment: A strobe signal from a memory is delayed through delay circuits of a strobe delay selection section, thus obtaining a plurality of delayed strobe signals. A strobe latch section produces check data in synchronism with each of the delayed strobe signals, and a system latch section latches, with a system... Agent: Panasonic Corporation
20140098620 - Semiconductor memory device: A semiconductor memory device includes a read circuit configured to sequentially output a plurality of compressed data corresponding to all banks which are to be tested in response to a plurality of bank addresses and a read enable signal during a test mode and a pad configured to transfer the... Agent: Sk Hynix Inc.
20140098622 - Memory controller that enforces strobe-to-strobe timing offset: A memory controller outputs a clock signal to first and second DRAMs disposed on a memory module, the clock signal requiring respective first and second time intervals to propagate to the first and second DRAMs. The memory controller outputs a write command to be sampled by the first and second... Agent: Rambus Inc.
20140098621 - Semiconductor memory device and driving method thereof: A semiconductor memory device includes: a variable delay for delaying a delay locked loop (DLL) clock by a predetermined delay time to output a delayed DLL clock; an output driver for outputting data and data strobe signal in response to the delayed DLL clock; and a calibration controller for controlling... Agent: 658868 N.b. Inc.
20140098623 - Apparatuses and methods for sensing fuse states: Apparatuses and methods for sensing fuse states are disclosed herein. An apparatus may include an array having a plurality of sense lines. A plurality of cells may be coupled to a sense line of the plurality of sense lines. A fuse sense circuit may coupled to the sense line of... Agent: Micron Technology, Inc.
20140098624 - Supply power dependent controllable write throughput for memory applications: Devices and methods that allow dynamic management of throughput in a memory device based on a power supply voltage are provided. According to various embodiments, the power supply level can be monitored. Based on the result of the monitoring, an appropriate throughput can be determined. Once the appropriate throughput is... Agent: Spansion LLC04/03/2014 > 38 patent applications in 24 patent subcategories.
20140092664 - Associative memory oscillator array: An embodiment of the invention includes an analog associative memory, which includes an array of coupled voltage or current controlled oscillators, that matches patterns based on shifting frequencies away from a center frequency of the oscillators. The test and memorized patterns are programmed into the oscillators by varying the voltage... Agent:
20140092665 - Semiconductor memory device: A memory cell array includes a plurality of word lines each connected to gates of cell transistors in corresponding ones of a plurality of memory cells, a plurality of first control lines, a plurality of second control lines, a first ground circuit configured to ground the first control lines together... Agent: Panasonic Corporation
20140092671 - Cross-point variable resistance nonvolatile memory device: A cross-point memory device including memory cells each includes: a variable resistance element that reversibly changes at least between a low resistance state and a high resistance state; and a current steering element that has nonlinear current-voltage characteristics, and the cross-point memory device comprises a read circuit which includes: a... Agent:
20140092667 - Data storage in memory array with less than half of cells in any row and column in low-resistance states: A method of storing data in a memory array with less than half of memory elements in any row and column in a low-resistance state. The data are arranged in a first portion of an encoding array. High-resistance values are entered in a second portion. A codeword is selected from... Agent: Hewlett-packard Development Company, L.p.
20140092666 - Low voltage embedded memory having conductive oxide and electrode stacks: Low voltage embedded memory having conductive oxide and electrode stacks is described. For example, a material layer stack for a memory element includes a first conductive electrode. A conductive oxide layer is disposed on the first conductive electrode. The conductive oxide layer has a plurality of oxygen vacancies therein. A... Agent:
20140092670 - Non-volatile resistive memory devices and methods for biasing resistive memory structures thereof: The disclosed technology relates to a non-volatile resistive memory device and a method of using the same. In one aspect, the memory device comprises a plurality of memory cells interconnected by a plurality of bit lines, a plurality of word lines, a plurality of source lines and a plurality of... Agent: Imec
20140092669 - Non-volatile variable resistive element, controlling device and storage device: A non-volatile variable resistive element according to an embodiment comprises a first electrode including a first metal, a second electrode including a second metal, a third electrode placed opposite to the first and second electrodes, and a variable resistive layer placed between the first and second electrodes and the third... Agent: Kabushiki Kaisha Toshiba
20140092668 - Resistive switching devices and memory devices including the same: A resistive switching device includes a first material layer between a first electrode and a second electrode. The first material layer has a first region and a second region parallel to the first region. The first region corresponds to a conducting path formed in the first material layer, and is... Agent: Samsung Electronics Co., Ltd.
20140092674 - Circuits and methods of a self-timed high speed sram: Circuits and methods for precisely self-timed SRAM memory are disclosed to track the wordline and/or bitline/bitline bar (BL/BLB) propagation delays. At least one reference cell can be placed near the far end of a driver to drive a selected wordline or a reference wordline. When a wordline and/or a reference... Agent:
20140092673 - Memory cell: This invention relates generally to a memory cell. The embodiments of the present invention provide a SRAM cell and a SRAM cell array comprising such SRAM cell. The SRAM cell according to the embodiments of the present invention includes a pull-up transistor and a pull-down transistor, such that it is... Agent: International Business Machines Corporation
20140092672 - Power management domino sram bit line discharge circuit: A domino static random access memory (SRAM) having one or more SRAM memory cells connected with a local bit line is disclosed. The SRAM may include a global bit line, a first precharge device connected between a voltage supply and the local bit line, and a second precharge device connected... Agent: International Business Machines Corporation
20140092675 - Two-port sram write tracking scheme: A write tracking control circuit includes an input node, and a first transistor configured to pre-charge a word bit line connected to at least two memory cells. The write tracking control circuit further includes a second transistor configured to pre-charge a read bit line connected to the at least two... Agent: Taiwan Simiconductor Manufacturing Company, Ltd.
20140092676 - Integrated circuit with separate supply voltage for memory that is different from logic circuit supply voltage: In one embodiment, an integrated circuit includes at least one logic circuit supplied by a first supply voltage and at least one memory circuit coupled to the logic circuit and supplied by a second supply voltage. The memory circuit is configured to be read and written responsive to the logic... Agent: Apple Inc.
20140092677 - Decreased switching current in spin-transfer torque memory: Switching current in Spin-Transfer Torque Memory (STTM) can be decreased. A magnetic memory cell is driven with a first pulse on a write line of the memory cell to heat the cell. The cell is then driven with a second pulse on the write line to set the state of... Agent:
20140092678 - Intelligent far memory bandwith scaling: Memory bandwidth management. In a two-level memory (2LM) system far memory bandwidth utilization at least a far memory is monitored and the available far memory bandwidth availability is dynamically modified based on monitored far memory bandwidth utilization. The operational state of at least one processing core is dynamically modified in... Agent:
20140092679 - Memory device and writing method thereof: A write amplifier for driving a bit line connected to a selected phase change memory cell drives the bit line with a first current driving capability and then drives the bit line with a second current driving capability lower than the first current driving capability.... Agent: Elpida Memory, Inc.
20140092680 - Multiple well bias memory: A multiple well bias memory device that includes a semiconductor substrate; a first well of a first conductivity type formed in the semiconductor substrate and having a memory cell formed therein; and a second well of the first conductivity type formed in the semiconductor substrate and having formed therein a... Agent:
20140092681 - Semiconductor device and driving method thereof: A semiconductor device includes: a source line; a bit line; a word line; a memory cell connected to the bit line and the word line; a driver circuit which drives a plurality of second signal lines and a plurality of word lines so as to select the memory cell specified... Agent: Semiconductor Energy Laboratory Co., Ltd.
20140092682 - Method for programming and reading flash memory by storing last programming page number: The invention is to provide a method for programming and reading a flash memory, storing the last programming page in a block while programming the flash memory, judging the programming times in the cell of the block by means of the last programming page and the order and distribution of... Agent:
20140092683 - Adjustable read time for memory: A method facilitates controlling a read time (tREAD) of an electronic memory device. The method includes implementing a first read time indicative of an array time for a read process for a memory array of the electronic memory device. The first read time relates to the time allocated to make... Agent: Fusion-io
20140092684 - Nonvolatile semiconductor memory device: When selectively erasing one sub-block, a control circuit applies, in a first sub-block, a first voltage to bit lines and a source line, and applies a second voltage smaller than the first voltage to the word lines. Then, the control circuit applies a third voltage lower than the first voltage... Agent: Kabushiki Kaisha Toshiba
20140092685 - Nonvolatile memory device, operating method thereof and memory system including the same: A method of operating a non-volatile memory device includes performing an erasing operation to memory cells associated with a plurality of string selection lines (SSLs), the memory cells associated with the plurality of SSLs constituting a memory block, and verifying the erasing operation to second memory cells associated with a... Agent: Samsung Electronics Co., Ltd.
20140092686 - Vertically-integrated nonvolatile memory devices having laterally-integrated ground select transistors: Nonvolatile memory devices utilize vertically-stacked strings of nonvolatile memory cells (e.g., NAND-type strings) that can be selectively coupled to common source lines within a substrate. This selective coupling may be provided by lateral ground select transistors having different threshold voltages that account for different lateral spacings between the vertically-stacked strings... Agent: Samsung Electronics Co., Ltd.
20140092687 - Method, apparatus, and manufacture for staggered start for memory module: A method, apparatus, and manufacture for memory device startup is provided. Flash memory devices are configured such that, upon the power supply voltage reaching a pre-determined level, each flash memory is arranged to load the random access memory with instructions for the flash memory, and then execute a first portion... Agent: Spansion LLC
20140092688 - Non-volatile semiconductor storage device: In a split gate MONOS memory which carries out rewrite by hot carrier injection, retention characteristics are improved. A select gate electrode of a memory cell is connected to a select gate line, and a memory gate electrode is connected to a memory gate line. A drain region is connected... Agent: Renesas Electronics Corporation
20140092689 - Method for programming non-volatile memory cell, non-volatile memory array and non-volatile memory apparatus: A method for programming a non-volatile memory cell is described. The memory cell includes a substrate, a gate over the substrate, a charge-trapping structure at least between the substrate and the gate, and first and second S/D regions in the substrate beside the gate. The method includes performing a channel-initiated... Agent: United Microelectronics Corp.
20140092694 - Multi-bit resistance measurement: An example embodiment is a circuit for determining a binary value of a memory cell. The circuit includes shunt capacitors having different capacitances to selectively couple with the memory cell, and a controller configured to iteratively charge the shunt capacitors to a first voltage until a selected shunt capacitor causes... Agent: International Business Machines Corporation
20140092691 - Semiconductor storage device: A semiconductor includes a memory cell array including a plurality of memory cells. A first amplifier produces, when activated, a first data signal related to data stored in a selected first one of the memory cells. A first transistor is between the output node of the first amplifier and a... Agent: Elpida Memory, Inc.
20140092690 - Variable rate parallel to serial shift register: A shift register structure is presented that can be used in variable rate parallel to serial data conversions. In an N to I conversion, data is received from an (N×m)-wide parallel data bus in an N by in wide latch. This data can include m-bit wide units of data are... Agent:
20140092692 - Variable rate serial to parallel shift register: A shift register structure is presented that can be used in fixed or variable rate serial to parallel data conversions. In an 1 to N conversion, data is received off an m-bit serial data bus and loaded into a N by m wide latch, before being transfer out onto an... Agent:
20140092693 - Semiconductor device and operating method thereof: A semiconductor device may test a semiconductor memory device by storing a data sample that is sampled from among data requested to be written into a semiconductor memory device and by comparing the data sample with data read from the semiconductor memory device which corresponds to the data sample.... Agent: Sk Hynix Inc.
20140092695 - Header circuit for controlling supply voltage of a cell: One or more techniques or systems for controlling a supply voltage of a cell are provided herein. Additionally, one or more techniques or systems for mitigating leakage of the cell are provided. In some embodiments, a header circuit is provided, including a first pull-up p-type metal-oxide-semiconductor (PMOS) transistor including a... Agent: Taiwan Semiconductor Manufacturing Company Limited
20140092696 - Power management domino sram bit line discharge circuit: A domino static random access memory (SRAM) having one or more SRAM memory cells connected with a local bit line is disclosed. The SRAM may include a global bit line, a first precharge device connected between a voltage supply and the local bit line, and a second precharge device connected... Agent: International Business Machines Corporation
20140092697 - Read timing generation circuit: Disclosed is a read timing generation circuit, capable of reducing dynamic power consumption. After a multi-bit address Add1, Add2, . . . , and AddN passes through an address change monitoring unit (100), a response pulse signal corresponding the address is generated. After the response pulse signal passes through an... Agent:
20140092699 - Intermediate circuit and method for dram: An intermediate circuit and method for hiding refresh confliction. The intermediate circuit includes: a first control circuit configured to generate a Command Output Enable signal CON, a Data Read Enable signal DRN and a Refresh Enable signal REFN based on the second clock, wherein a ration of duration the signal... Agent: International Business Machines Corporation
20140092698 - Semiconductor device and operating method thereof: An operating method of a semiconductor device may comprise monitoring error handling information corresponding to an address of a semiconductor memory device, setting a refresh period for the address considering the error handling information and requesting a refresh request for the address.... Agent: Sk Hynix Inc.
20140092700 - Fine granularity power gating: Rows of a memory array are segmented into a predetermined number of word line groups. Each row in a word line group has a word line disposed between parallel power supply lines. Each of the power supply lines in a row of a word line group is shared by an... Agent: International Business Machines Corporation
20140092701 - Multiple device apparatus, systems, and methods: Apparatus, systems, and methods are disclosed that operate to generate a clock signal in a die in a stack and to receive the clock signal in another die in the stack. Additional apparatus, systems, and methods are disclosed.... Agent: Micron Technology, Inc.03/27/2014 > 46 patent applications in 27 patent subcategories.
20140085958 - Pre-computation based ternary content addressable memory: A pre-computation based TCAM configured to reduce the number of match lines being pre-charged during a search operation to save power is disclosed. The pre-computation based TCAM stores additional information in a secondary TCAM that can be used to determine which match lines in a primary TCAM storing data words... Agent: Broadcom Corporation
20140085957 - Shared stack dual phase content addressable memory (cam) cell: A shared stack dual-phase CAM cell is provided. The CAM cell includes at least first and second stacks that share a single pair of pull-down transistors. At least one pair of pull-down transistors can thus be eliminated, reducing the area and power consumption of the CAM cell. Sharing of the... Agent: Broadcom Corporation
20140085959 - 3d memory configurable for performance and power: A 3D memory that is configurable for performance and power. An embodiment of a memory device includes a dynamic random-access memory (DRAM) including multiple memory dies, each memory die including multiple memory arrays, each memory array including peripheral logic circuits and a configurable logic. The memory device further includes a... Agent:
20140085960 - Semiconductor memory device and electronic device: A semiconductor memory device including a plurality of memory blocks MBA0, MBA1, MBB0, MBB1; a plurality of bus lines 26 provided respectively associated with the plurality of memory blocks; a plurality of input/output ports 22a, 22b; a selector 28a, 28b selectively connecting each of the plurality of bus lines to... Agent: Fujitsu Semiconductor Limited
20140085961 - Semiconductor memory device: According to example embodiments of inventive concepts, a semiconductor memory devices includes: a plurality of memory blocks that each include a plurality of stack structures, global bit lines connected in common to the plurality of memory blocks, block selection lines configured to control electrical connect between the global bit lines... Agent:
20140085962 - Systems and methods for reading ferroelectric memories: A system and method are provided for reading ferroelectric memories in a manner that does away with a conventional requirement for inclusion of a charge or sense amplifier associated with each ferroelectric memory cell. Simple circuits are employed for modulating an AC signal that is generated and input, including wirelessly,... Agent: Palo Alto Research Center Incorporated
20140085963 - Systems and methods for writing and non-destructively reading ferroelectric memories: Ferroelectric memory cell configurations, a system for controlling writing and reading to those configurations and a method for employing those configurations for writing and reading ferroelectric memories are provided. Ferroelectric memory cells according to the disclosed configurations are read without disturbing the stored data, i.e., not requiring any modification of... Agent: Palo Alto Research Center Incorporated
20140085964 - Semiconductor storage device: A control circuit controls memory operations such that, in a first rewriting operation in which a resistance state of a variable resistance element is changed from a first state to a second state, a first voltage pulse is applied to both terminals of a memory cell while limiting the amount... Agent: Sharp Kabushiki Kaisha
20140085965 - Column select multiplexer and method for static random-access memory and computer memory subsystem employing the same: A column select multiplexer, a method of reading data from a random-access memory and a memory subsystem incorporating the multiplexer or the method. In one embodiment, the column select multiplexer includes: (1) a first field-effect transistor having a gate coupled via an inverter to a bitline of a static random-access... Agent: Nvidia Corporation
20140085966 - Field effect transistors including asymmetrical silicide structures and related devices: A fin Field Effect Transistor (finFET) can include a source region and a drain region of the finFET. A gate of the finFET can cross over a fin of the finFET between the source and drain regions. First and second silicide layers can be on the source and drain regions... Agent:
20140085967 - Memory elements with relay devices: Integrated circuits with memory elements are provided. An integrated circuit may include logic circuitry formed in a first portion having complementary metal-oxide-semiconductor (CMOS) devices and may include at least a portion of the memory elements and associated memory circuitry formed in a second portion having nano-electromechanical (NEM) relay devices. The... Agent: Altera Corporation
20140085970 - Magnetic memory: A magnetic memory includes a magnetic wire, a first insulating layer, first electrodes a second electrode, a current supplying module, and a voltage applying module. The magnetic wire includes a first portion and a second portion, has a first electric resistance value, and is configured to form magnetic domains. The... Agent: Kabushiki Kaisha Toshiba
20140085971 - Magnetoresistive effect element: According to one embodiment, a magnetoresistive effect element includes the following structure. A first ferromagnetic layer has a variable magnetization direction. A second ferromagnetic layer has an invariable magnetization direction. A tunnel barrier layer is formed between the first and second ferromagnetic layers. An energy barrier between the first ferromagnetic... Agent:
20140085968 - Nonvolatile memory device: According to one embodiment, a nonvolatile memory device includes: a magnetic memory element and a control unit. The magnetic memory element includes a stacked body, and a first and a second stacked units. The first stacked unit includes a first and second ferromagnetic layers and a first nonmagnetic layer provided... Agent: Kabushiki Kaisha Toshiba
20140085969 - Nonvolatile memory device: c
20140085972 - Semiconductor memory device, memory system and access method to semiconductor memory device: A semiconductor memory device includes a block array having an m number of memory blocks in a row direction and an n number of memory blocks in a column direction (m being an integer of 2 or more and n being an integer of 1 or more), a page selection... Agent: Kabushiki Kaisha Toshiba
20140085973 - Method, system and device for recessed contact in memory array: Embodiments disclosed herein may relate to forming a contact region for an interconnect between a selector transistor and a word-line electrode in a memory device.... Agent: Micron Technology, Inc.
20140085974 - Method, system, and device for phase change memory switch wall cell with approximately horizontal electrode contact: Embodiments disclosed herein may include depositing a storage component material over and/or in a trench in a dielectric material, including depositing the storage component material on approximately vertical walls of the trench and a bottom of the trench. Embodiments may also include etching the storage component material so that at... Agent: Micron Technology, Inc.
20140085975 - Current monitoring circuit for memory wakeup time: A microcontroller system is determining to exit a power saving mode and, in response, enable a reference current source to begin providing a reference current for a memory module. The microcontroller system determines that the reference current has reached a substantial fraction of a target reference current, and, in response... Agent: Atmel Corporation
20140085976 - Nonvolatile semiconductor memory device: This nonvolatile semiconductor memory device comprises a transistor string formed on a substrate and including a plurality of first transistors connected in series with each other. A first bit line is connected to a first end of the transistor string. A source line is connected to a second end of... Agent: Kabushiki Kaisha Toshiba
20140085977 - Semiconductor memory device with memory cells each including a charge accumulation layer and a control gate: A semiconductor memory device includes a memory cell unit, word lines, a driver circuit, and first transistors. The word lines are connected to the control gates of 0-th to N-th memory cells. The (N+1) number of first transistors transfer the voltage to the word lines respectively. Above one of the... Agent: Kabushiki Kaisha Toshiba
20140085978 - Method and architecture for improving defect detectability, coupling area, and flexibility of nvsram cells and arrays: Several preferred embodiments of 1S1F 16T NVSRAM, 1S1F 20T NVSRAM, 1S2F 22T NVSRAM, 1S2F 14T NVSRAM cells are proposed, regardless of 1-poly, 2-poly, PMOS or NOS flash cell structures. Two separate sourcelines for the paired flash Strings are also proposed for easy adding ability for the NVSRAM circuit to detect... Agent: Aplus Flash Technology, Inc.
20140085980 - Memory devices and their operation with different sets of logical erase blocks: Systems comprising an array of memory cells organized into a plurality of erasable physical blocks, the address of physical block associated with an array of memory cells having a predetermined logical erase block size, wherein at least of the logical erase block size is smaller than another logical erase block... Agent: Round Rock Research, LLC
20140085979 - Nonvolatile semiconductor memory device: A memory cell array according to an embodiment includes a plurality of NAND strings with a plurality of memory cells stacked, and a bit line is connected to the NAND string. A word line is connected to a gate of the memory cell. A column system circuit is disposed directly... Agent: Kabushiki Kaisha Toshiba
20140085981 - Semiconductor memory device: A semiconductor memory device includes a memory block as a code storage memory area which has a large memory capacity and in which the number of bits to be written at once is large, and a memory block as a work memory area which has a small memory capacity and... Agent: Fujitsu Semiconductor Limited
20140085983 - Nonvolatile semiconductor memory device and control method thereof: A nonvolatile semiconductor memory device includes a memory cell array having first and second groups of memory strings, each memory string including first and second memory cells connected between select transistors. The nonvolatile semiconductor memory device further includes a first word line connected to the first memory cells of the... Agent: Kabushiki Kaisha Toshiba
20140085982 - Semiconductor memory device: A semiconductor memory device includes a memory string having first and second selective transistors, each of which includes a charge storage layer and a control gate, a back gate transistor which includes a charge storage layer and a control gate, and memory cell transistors connected to each other and to... Agent: Kabushiki Kaisha Toshiba
20140085986 - Memory array device and method for reducing read current of the same: A memory array device is disclosed, which includes a plurality of memory array rows, each memory array row including a plurality of subsidiary memory arrays and a switch arranged between every adjacent two subsidiary memory arrays; wherein each subsidiary memory array includes: a memory unit for storing a data; a... Agent: Grace Semiconductor Manufacturing Corporation
20140085988 - Nonvolatile semiconductor memory device: A nonvolatile semiconductor memory device according to one embodiment of the present invention includes: a memory cell array and a control circuit. The control circuit executes a first reading operation and a second reading operation. The first reading operation is an operation of reading a threshold voltage set in the... Agent: Kabushiki Kaisha Toshiba
20140085987 - Semiconductor memory circuit: Provided is a semiconductor memory circuit excellent in long-term reliability and reading characteristics and having low current consumption. The semiconductor memory circuit includes: a first inverter; a first non-volatile memory, which is electrically writable; a second inverter; and a second non-volatile memory, the first inverter having an output connected to... Agent: Seiko Instruments Inc.
20140085985 - Sigma delta over-sampling charge pump analog-to-digital converter: Techniques are presented for determining current levels based on the behavior of a charge pump system while driving a load under regulation. While driving the load under regulation, the number of pump clocks during a set interval is counted. This can be compared to a reference that can be obtained,... Agent: Sandisk Technologies Inc.
20140085984 - Two-transistor non-volatile memory cell and related program and read methods: A memory device includes an N-channel transistor and a P-channel transistor. A word line is electrically connected to a drain terminal of the N-channel transistor, and a source terminal of the P-channel transistor. A first bit line is electrically connected to a source terminal of the N-channel transistor. A second... Agent: Taiwan Semiconductor Manufacturing Company, Ltd.
20140085989 - Semiconductor memory device: According to one embodiment, a semiconductor memory device includes memory units each of which includes first and second select transistors and memory cells connected in series between the first and second select transistors. A control circuit applies a first potential difference between a source and a drain of either the... Agent: Kabushiki Kaisha Toshiba
20140085991 - Nonvolatile semiconductor memory device: A nonvolatile semiconductor memory device comprises a plurality of memory blocks, each including a plurality of cell units and each configured as a unit of execution of an erase operation. Each of the cell units comprises a memory string, a first transistor, a second transistor, and a diode. The first... Agent: Kabushiki Kaisha Toshiba
20140085990 - Volatile semiconductor memory device and memory system: A non-volatile semiconductor memory device includes a memory cell array and a control circuit. A control circuit performs an erase operation providing a memory cell with a first threshold voltage level for erasing data of a memory cell, and then perform a plurality of first write operations providing a memory... Agent: Kabushiki Kaisha Toshiba
20140085992 - Transistor voltage threshold mismatch compensated sense amplifiers and methods for precharging sense amplifiers: Sense amplifiers and methods for precharging are disclosed, including a sense amplifier having a pair of cross-coupled complementary transistor inverters, and a pair of transistors, each one of the pair of transistors coupled to a respective one of the complementary transistor inverters and a voltage. The sense amplifier further includes... Agent: Micron Technology, Inc.
20140085993 - Multiple bitcells tracking scheme semiconductor memory array: A read tracking system and method for advanced memory devices are provided. The read tracking system and method include tracking multiple tracking bit cells in multiple segments and columns to incorporate device performance variation of bit cells in the memory array. The tracking path mimics the worst-case read path with... Agent: Taiwan Semiconductor Manufacturing Company, Ltd.
20140085994 - Integrated circuitry, chip, method for testing a memory device, method for manufacturing an integrated circuit and method for manufacturing a chip: In various embodiments an integrated circuit or chip is provided, the integrated circuit including a memory device including a plurality of memory cells, and with the memory cells being configured to store a data content, and a controller being configured to write a predefined data pattern in the memory cells... Agent: Infineon Technologies Ag
20140085995 - Method, apparatus and system for determining a count of accesses to a row of memory: Techniques and mechanisms for determining a count of accesses to a row of a memory device. In an embodiment, the memory device includes a counter comprising circuitry to increment a value of the count in response to detecting a command to activate the row. Circuitry of counter may further set... Agent:
20140085996 - Readout circuit and semiconductor device: Provided is a readout circuit capable of detecting inversion of retained data caused by a noise, such as static electricity. The readout circuit is configured to retain opposing data in a first latch circuit and a second latch circuit in a readout period so as to be capable of detecting... Agent: Seiko Instruments Inc.
20140085997 - Semiconductor device having hierarchical bit line structure: A method includes accessing a memory cell to allow the memory cell to output data stored therein onto a local bit line; transferring, in response to a data read mode, a signal related to the data from the local bit line to a global bit line; and restoring, in response... Agent: Elpida Memory, Inc.
20140085998 - Composition comprising various proteorhodopsins and/or bacteriorhodopsins and use thereof: The present invention provides a solid material comprising an immobilized mixture of two or more proteorhodopsins, two or more bacteriorhodopsins, or one or more bacteriorhodopsin and one or more proteorhodopsins. The proteorhodopsins are selected from the group consisting of all-trans-retinal-containing proteorhodopsins and retinal analog-containing proteorhodopsins; all of which have absorption... Agent: Danisco US Inc.
20140085999 - Semiconductor memory device having adjustable refresh period, memory system comprising same, and method of operating same: A semiconductor memory device comprises a cell array comprising a plurality of cell regions, a row decoder configured to drive rows corresponding to cell regions in which a refresh operation is to be performed, based on a counting address, and a refresh address generator configured to generate the counting address... Agent: Samsung Electronics Co., Ltd.
20140086000 - Power consumption control: The present disclosure includes apparatuses and methods for power consumption control. A number of embodiments include determining power consumption information for each phase in a combination of phases of a command, and authorizing execution of at least one of the phases in the combination based, at least partially, on the... Agent: Micron Technology, Inc.
20140086001 - Nonvolatile semiconductor memory device: A nonvolatile semiconductor memory device includes a memory cell array having multiple blocks each with a plurality of memory strings. Each memory string has multiple memory cells connected in series between first and second selection transistors. The device further includes a row decoder, a block decoder, first and second signal... Agent: Kabushiki Kaisha Toshiba
20140086002 - Semiconductor memory device and detection clock pattern generating method thereof: A clock pattern generating method of a semiconductor memory device is provided. The method includes generating the same clock pattern through a plurality of detection clock output pins when an output selection control signal is in a first state and generating clock patterns different from each other through the plurality... Agent: Samsung Electronics Co., Ltd.03/20/2014 > 49 patent applications in 30 patent subcategories.
20140078804 - Mask design with optically isolated via and proximity correction features: A lithography mask and method for manufacturing such mask that includes optically isolated via features and proximity correction features. The via patterns that include via features that define vias are positioned on the mask in rows and columns with a row and a column pitch between each row and column... Agent: Macronix International Co., Ltd.
20140078805 - Semiconductor memory device having vertical transistors: A device includes first and second regions including first and second amplifiers, respectively and a memory cell array region formed between the first and second regions and includes first and second conductive layers each extending in a first direction, and a plurality of first pillar elements arranged in line in... Agent: Elpida Memory, Inc.
20140078806 - Channel hot carrier tolerant tracking circuit for signal development on a memory sram: An embodiment of the invention discloses an electronic device for reducing degradation in NMOS circuits in a tracking circuit. A first multiplexer selects, based on N bits from a row address in a memory array, which tracking circuit from a group of 2N tracking circuits will be used to provide... Agent: Texas Instruments Incorporated
20140078807 - Magnetic recording device and magnetic recording apparatus: An example magnetic recording device includes a magnetic recording section and a magnetization oscillator and a first nonmagnetic layer disposed between the magnetic recording section and the magnetization oscillator. The magnetic recording section includes a first ferromagnetic layer with a magnetization substantially fixed in a first direction; a second ferromagnetic... Agent: Kabushiki Kaisha Toshiba
20140078814 - Crosspoint nonvolatile memory device and method of driving the same: The nonvolatile memory device includes a control circuit that controls a sense amplification circuit and a writing circuit. The control circuit changes a value of at least one of (a) a load current and (b) a forming pulse current or a forming pulse voltage, according to a total number of... Agent:
20140078808 - Embedded nonvolatile memory elements having resistive switching characteristics: Provided are nonvolatile memory assemblies each including a resistive switching layer and current steering element. The steering element may be a transistor connected in series with the switching layer. Resistance control provided by the steering element allows using switching layers requiring low switching voltages and currents. Memory assemblies including such... Agent: Intermolecular, Inc.
20140078810 - Loadless volatile/non-volatile memory cell: The invention concerns a memory device comprising at least one memory cell comprising: first and second transistors (102, 104) coupled between first and second storage nodes (106, 108) respectively and a first supply voltage, a control terminal of said first transistor being coupled to said second storage node, and a... Agent: Centre National De La Recherche Scientifique
20140078812 - Methods of operating variable resistance memory devices and related variable resistance memory devices so operating: A method of operating a resistive non-volatile memory can be provided by applying a forming voltage across first and second electrodes of a selected memory cell in the variable resistance non-volatile memory device during an operation to the selected memory cell. The forming voltage can be a voltage level that... Agent: Samsung Electronics Co., Ltd.
20140078809 - Nonvolatile latch circuit, nonvolatile flip-flop circuit, and nonvolatile signal processing device: A nonvolatile latch circuit according to the present invention includes: a latch operating unit in which outputs of cross-coupled connected inverter circuit and inverter circuit are connected via a series circuit which includes a transistor, a variable resistance element, and a transistor in this order, and store and restore in... Agent: Panasonic Corporation
20140078813 - Nonvolatile semiconductor memory device: A nonvolatile semiconductor memory device includes a memory cell array including memory cells having a variable resistance element provided at intersections of crossing first and second lines, the memory cell array including third lines, fourth and fifth lines, and first and second diodes; and a control circuit which, when the... Agent: Kabushiki Kaisha Toshiba
20140078811 - Variable resistance nonvolatile memory element writing method and variable resistance nonvolatile memory device: Provided is a method of writing to a variable resistance nonvolatile memory element which is capable of both improving retention characteristics and enlarging a window of operation. In the method of writing, to write “1” data (LR), first a weak HR writing process is performed in which a weak HR... Agent: Panasonic Corporation
20140078816 - Signal processing circuit and method for driving the same: It is an object to provide a memory device for which a complex manufacturing process is not necessary and whose power consumption can be suppressed and a signal processing circuit including the memory device. In a memory element including a phase-inversion element by which the phase of an input signal... Agent: Semiconductor Energy Laboratory Co., Ltd.
20140078815 - Voltage rail noise sensing circuit and method: Apparatus and methods level shift a direct current (DC) component of a voltage rail signal from a first DC level to a second DC level such that voltage rail noise can be determined. The actual voltage rail noise can be compared to an expected amount of noise for analysis and... Agent: Micron Technology, Inc.
20140078817 - Integrated circuits with sram cells having additional read stacks and methods for their fabrication: Integrated circuits that include SRAM cells having additional read stacks and methods for their fabrication are provided. In accordance with one embodiment a method for fabricating such an integrated circuit includes forming a plurality of SRAM cells in and on a semiconductor substrate, each of the plurality of SRAM cells... Agent: Globalfoundries Inc.
20140078819 - Static random access memory cell with single-sided buffer and asymmetric construction: Balanced electrical performance in a static random access memory (SRAM) cell with an asymmetric context such as a buffer circuit. Each memory cell includes a circuit feature, such as a read buffer, that has larger transistor sizes and features than the other transistors within the cell, and in which the... Agent: Texas Instruments Incorporated
20140078818 - Static random access memory with ripple bit lines/search lines for imroving current leakage/variation tolerance and density/performance: A static random access memory includes a pre-charger, a first cell column array/peripheral circuit, and a first ripple buffer. The pre-charger is connected to a first local bit line in order to pre-charge the first local bit line. The first cell column array/peripheral circuit is connected to the first local... Agent: National Chiao Tung University
20140078821 - Complementary decoding for non-volatile memory: Decoding and decoder circuits in memory devices are disclosed. Array lines are biased or floated as memory device operations are performed in the memory device. In at least one embodiment, a decoder circuit includes complementary devices to bias array lines or float array lines in a memory device while particular... Agent: Micron Technology, Inc.
20140078820 - Data readout circuit of phase change memory: A data readout circuit of phase change memory, relating to one or more phase change memory cells, wherein each phase change memory cell is connected to the control circuit by bit line and word line; said data readout circuit comprises: a clamp voltage generating circuit, used to generate a clamp... Agent:
20140078822 - Methods and apparatuses having a voltage generator with an adjustable voltage drop for representing a voltage drop of a memory cell and/or a current mirror circuit and replica circuit: Apparatus and methods utilize a replica circuit to generate a voltage for programming of a memory cell, such as a memory cell of a phase-change memory (PCM). Current passing through a circuit including the memory cell to be programmed is mirrored in a scaled or unscaled manner, and provided as... Agent: Micron Technology, Inc.
20140078823 - Phase change memory thermal management with electrocaloric effect materials: Technologies are generally described herein for managing heat within a phase change memory (PCM) structure utilizing electrocaloric effect materials. Some example PCM structures may include an electrocaloric effect material layer thermally coupled to an array of PCM cells. The electrocaloric effect material layer may be segmented so that activation of... Agent: Empire Technology Development LLC
20140078825 - Data storage device and flash memory control method thereof: Storage space allocation and a wear leveling technique for a FLASH memory module are disclosed. The FLASH memory module includes a plurality of FLASH chips. A controller for the FLASH memory module divides the storage space of the FLASH memory module into Xblocks for management of the FLASH memory module.... Agent: Silicon Motion, Inc.
20140078827 - Apparatuses and methods including memory array and data line architecture: Some embodiments include apparatus and methods having memory cells located in different device levels of a device, at least a portion of a transistor located in a substrate of the device, and a data line coupled to the transistor and the memory cells. The data line can be located between... Agent: Micron Technology, Inc.
20140078826 - Methods of making word lines and select lines in nand flash memory: A NAND flash memory chip includes word lines formed by etching through concentric conductive loops and, in the same etch step, etching through a conductive strip to form select lines. A conductive loop forms two word lines which are in different erase blocks and are separately controlled by peripheral circuits.... Agent:
20140078828 - Nvm with charge pump and method therefor: A non-volatile memory device comprises an array of memory cells and a charge pump coupled to the memory cells. The charge pump is dynamically reconfigurable to operate in a bypass mode to provide a first voltage to the memory cells, a program mode to provide the first voltage to the... Agent:
20140078829 - Non-volatile memory (nvm) with adaptive write operations: A method of performing a write operation on memory cells of a memory array includes applying a first plurality of pulses the write operation on the memory cells in accordance with a first predetermined ramp rate, wherein the first plurality of pulses is a predetermined number of pulses; performing a... Agent:
20140078824 - Self-biasing current reference: Current appearing on a bit-line with no memory cells asserted may be used during a bit-line pre-charge time before a read is performed so as to bias a gate-drain shorted PMOS pull-up device connected between the bit-line and a power supply at a VDD potential. The capacitance connected to the... Agent:
20140078830 - Auto-refresh method for sonos non-volatile memory array: A method for performing auto-refresh of a SONOS memory in a field programmable gate array in a system, includes sensing an auto-refresh condition, selecting a memory segment that has not yet been refreshed, storing the contents of memory segment, erasing the memory cells in the memory segment, and reprogramming the... Agent: Microsemi Soc Corp.
20140078831 - Self-biasing multi-reference: Current appearing on a bit-line with no memory cells asserted may be used during a bit-line pre-charge time before a read is performed so as to bias a gate-drain shorted PMOS pull-up device connected between the bit-line and a power supply at a VDD potential. The capacitance connected to the... Agent:
20140078832 - Non-volatile memory having discrete isolation structure and sonos memory cell, method of operating the same, and method of manufacturing the same: A non-volatile memory having discrete isolation structures and SONOS memory cells, a method of operating the same, and a method of manufacturing the same are introduced. Every isolation structure on a semiconductor substrate having an array region has a plurality of gaps so as to form discrete isolation structures and... Agent: Eon Silicon Solution, Inc.
20140078833 - Increasing memory operating frequency: A memory apparatus includes a plurality of memory arrays, each memory array including a plurality of memory cells. The apparatus includes a plurality of global bit lines and each one of the global bit lines is connected to a plurality of local bit lines, which are in turn connected to... Agent: International Business Machines Corporation
20140078834 - Semiconductor memory device and information processing apparatus: A semiconductor memory device includes an address decoder to decode an address specifying pseudo-multiport cells in memory blocks, a first word line driver to output a word line selection signal selecting one of word lines of one of the pseudo-multiport cells based on a row address in the address, and... Agent: Fujitsu Limited
20140078835 - High frequency memory: Embodiments of the disclosure include a high frequency write through memory device including a plurality of memory cells and a plurality of local evaluation circuits. Each of the plurality of local evaluation circuits are coupled to at least one of the plurality of memory cells and are configured to prevent... Agent: International Business Machines Corporation
20140078836 - Using a reference bit line in a memory: Methods, memories and systems may include charging a sense node to a logic high voltage level, and supplying charge to a bit line and to a reference bit line for a precharge period that is based, at least in part, on a time for a voltage of the reference bit... Agent:
20140078837 - Compact low-power asynchronous resistor-based memory read operation and circuit: A compact, low-power, asynchronous, resistor-based memory read circuit includes a memory cell having a plurality of consecutive memory states, each of said states corresponding to a respective output voltage. A sense amplifier reads the state of the memory cell. The sense amplifier includes a voltage divider configured to receive the... Agent: International Business Machines Corporation
20140078838 - Interfacing between integrated circuits with asymmetric voltage swing: Embodiments of the invention are generally directed to interfacing between integrated circuits with asymmetric voltage swing. An embodiment of an apparatus includes a first integrated circuit including a first transmitter and a first receiver; a second integrated circuit including a second transmitter and a second receiver; and an interface including... Agent: Silicon Image, Inc.
20140078839 - Methods for sensing memory elements in semiconductor devices: A memory device that, in certain embodiments, includes a plurality of memory elements connected to a bit-line and a delta-sigma modulator with a digital output and an analog input, which may be connected to the bit-line. In some embodiments, the delta-sigma modulator includes a circuit with first and second inputs... Agent: Micron Technology Inc.
20140078840 - Memory system having memory ranks and related tuning method: A memory device comprises at least two memory ranks sharing input/output lines, at least one mode register configured to store bits used to tune delays of data signals of the at least two ranks output through the input/output lines, a controller configured to determine tuning parameters for the data signals... Agent: Samsung Electronics Co., Ltd.
20140078842 - Post package repairing method, method of preventing multiple activation of spare word lines, and semiconductor memory device including fuse programming circuit: Provided is a method of preventing simultaneous activation of redundancy memory line or spare word lines, the method including: programming a fail address of a memory line determined to be defective; reprogramming the fail address if a first spare line for the memory line is determined to be defective; storing... Agent: Samsung Electronics Co., Ltd.
20140078841 - Programmable memory built in self repair circuit: An integrated circuit chip comprising at least one programmable built-in self-repair (PBISR) for repairing memory is described. The PBISR comprises an interface that receives signals external to the integrated chip. The PBISR further includes a port slave module that programs MBISR registers, program and instruction memory. The PBISR further comprises... Agent: Mosys, Inc.
20140078843 - Semiconductor device and test method thereof: A semiconductor chip includes a memory array including a plurality of memory cells, a plurality of terminals including a plurality of test terminals to output a result of a specific test, and a circuit that outputs the result to a selected one of the plurality of test terminals based on... Agent: Elpida Memory, Inc.
20140078844 - Memory circuits, systems, and methods for accessing the memory circuits: A sense amplifier includes a first transistor. The first transistor includes a gate connected to a bit line, and a first source/drain (S/D) electrically coupled with a global bit line. The sense amplifier further includes a second transistor. The second transistor includes a gate connected to a first signal line,... Agent: Taiwan Semiconductor Manufacturing Company, Ltd.
20140078845 - Cell array, memory, and memory system including the same: A memory includes a first cell array configured to include a plurality of first memory cells connected to a plurality of word lines, a second cell array configured to include a plurality of second memory cells connected to the plurality of word lines, wherein a group of the plurality of... Agent: Sk Hynix Inc.
20140078849 - Control of inputs to a memory device: A memory device includes a command decoder and control interface logic. One or more external inputs, such as row and column address strobes, communicate with the command decoder through the control interface logic. A control signal is also in communication with the control interface logic. During operation of a drowsy... Agent: Micron Technology, Inc.
20140078847 - Memory refresh methods, memory section control circuits, and apparatuses: Apparatuses, memory section control circuits, and methods of refreshing memory are disclosed. An example apparatus includes a plurality of memory sections and a plurality of memory section control circuits. Each memory section control circuit is coupled to a respective one of the plurality of memory sections and includes a plurality... Agent: Micron Technology, Inc.
20140078846 - Semiconductor memory device capable of performing refresh operation without auto refresh command: A semiconductor memory device includes an internal address generating circuit; an internal command generating circuit; and a memory cell array including one or more memory bank groups. The semiconductor memory device is configured such that when a read command or a write command is input, if a first portion of... Agent: Samsung Electronics Co., Ltd.
20140078848 - Semiconductor memory device, memory controller, and data processing system including these: In one embodiment, a semiconductor memory device receives a refresh command and address information, and supplies a refresh control signal and the address information in common to core chips. Each of the core chips includes a layer-address comparison circuit that determines whether the address information assigns an own core chip,... Agent:
20140078850 - Semiconductor device and memory control method: An access detection section detects access to an access object circuit and outputs a signal which restricts switching the access object circuit from a first operation state to a second operation state (low power consumption operation state) in which power consumption is lower than power consumption in the first operation... Agent: Fujitsu Semiconductor Limited
20140078851 - Continuous mesh three dimensional non-volatile storage with vertical select devices: A three-dimensional array adapted for memory elements that reversibly change a level of electrical conductance in response to a voltage difference being applied across them. Memory elements are formed across a plurality of planes positioned different distances above a semiconductor substrate. Bit lines to which the memory elements of all... Agent: Sandisk 3d LLC
20140078852 - Semiconductor device including latency counter: For example, a semiconductor device includes a first latency counter, which selects whether to give an odd-cycle latency to an internal command signal; and a second latency counter, which gives a latency to an internal command signal at intervals of two cycles. The latency counters are connected in series. Since... Agent: Elpida Memory, Inc.Previous industry: Electric power conversion systems
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