|Static information storage and retrieval patents - Monitor Patents|
USPTO Class 365 | Browse by Industry: Previous - Next | All
Recent | 14: Aug | Jul | Jun | May | Apr | Mar | Feb | Jan | 13: Dec | Nov | Oct | Sep | Aug | Jul | Jun | May | Apr | Mar | Feb | Jan | 12: Dec | Nov | Oct | Sep | Aug | July | June | May | April | Mar | Feb | Jan | 11: Dec | Nov | Oct | Sep | Aug | Jul | Jun | May | Apr | Mar | Feb | Jan | 10: Dec | Nov | Oct | Sep | Aug | Jul | Jun | May | Apr | Mar | Feb | Jan | | 09: Dec | Nov | Oct | Sep | Aug | Jl | Jn | May | Apr | Mar | Fb | Jn | | 2008 | 2007 |
Static information storage and retrievalBelow are recently published patent applications awaiting approval from the USPTO. Recent week's RSS XML file available below.
Listing for abstract view: USPTO application #, Title, Abstract excerpt,Patent Agent. Listing format for list view: USPTO National Class full category number, title of the patent application. 08/07/2014 > 51 patent applications in 30 patent subcategories.
20140218994 - Power savings in a content addressable memory device using masked pre-compare operations: A CAM device for comparing a search key with a plurality of ternary words stored in a CAM array includes one or more population counters, a pre-compare memory, and a pre-compare circuit. The present embodiments reduce the power consumption of CAM devices during compare operations between a search key and... Agent: Netlogic Microsystems, Inc.
20140218995 - Semiconductor chips: A semiconductor chip includes a core region having a plurality of first memory cells and a first edge adjacent to a first side of the core region. The first edge includes a first region and a second region. The first region includes a plurality of second memory cells, and the... Agent: Sk Hynix Inc.
20140218996 - Smart bridge for memory core: An apparatus includes a semiconductor device that includes a three-dimensional (3D) memory. The 3D memory includes multiple memory cells arranged in multiple physical levels above a substrate. The 3D memory includes circuitry associated with operation of the multiple memory cells and includes a serializer/deserializer interface.... Agent: Sandisk Technologies Inc.
20140218997 - Smart bridge for memory core: An apparatus includes a semiconductor device including a three-dimensional (3D) memory. The 3D memory includes multiple memory cells arranged in multiple physical levels above a substrate. The 3D memory includes circuitry associated with operation of the multiple memory cells and includes a differential signaling interface.... Agent: Sandisk Technologies Inc.
20140218998 - Semiconductor package: In a semiconductor package, a circuit pattern is arranged in a circuit board and contact pads on the circuit board are connected with the circuit pattern. Contact terminals contact external contact elements on a first surface of the circuit board. An integrated circuit (IC) chip structure is mounted on the... Agent: Samsung Electronics Co., Ltd.
20140218999 - Semiconductor storage device: With the aim of providing a semiconductor memory device being suitable for miniaturization and allowing a contact resistance to lower, the wiring structure of a memory array (MA) is formed as follows. That is, word lines (2) and bit lines (3) are extended in parallel to each other, each of... Agent:
20140219000 - Otp cell array including protected area, semiconductor memory device including the same, and method of programming the same: A method of programming a memory device including a one-time programmable (OTP) cell array configured to include at least one of a protected area and a programmable area are disclosed. The method includes receiving a fuse-program command to initiate a fuse-programming operation; checking whether the programmable area exists in the... Agent: Samsung Electronics Co., Ltd.
20140219006 - Access signal adjustment circuits and methods for memory cells in a cross-point array: Embodiments of the invention relate generally to semiconductors and memory technology, and more particularly, to systems, integrated circuits, and methods to generate access signals to facilitate memory operations in scaled arrays of memory elements, such as memory implemented in third dimensional memory technology formed BEOL directly on top of a... Agent: Unity Semiconductor Corporation
20140219001 - Applying a bias signal to memory cells to reverse a resistance shift of the memory cells: Data is written to cells of a resistance-based, non-volatile memory. An activity metric is tracked since the writing of the data to the cells. In response to the activity metric satisfying a threshold, a bias signal is applied to the cells to reverse a resistance shift of the cells.... Agent: Seagate Technology LLC
20140219002 - Method and apparatus for adaptive timing write control in a memory: A bit line, which is coupled to a resistive element of a memory cell is set to a first voltage level. The memory cell may be an MRAM cell or an RRAM cell. The resistive element is configured to have a first resistance in a first state of the memory... Agent: Taiwan Semiconductor Manufacturing Co., Ltd.
20140219004 - Nonvolatile semiconductor memory device: b
20140219005 - Semiconductor memory device and method of controlling data thereof: A control circuit is configured to perform a state determination operation to sense voltages of a plurality of first wiring lines, the voltages changing based on current flowing from the first wiring lines to a plurality of second wiring lines via a plurality of variable resistive elements. Then, the control... Agent: Kabushiki Kaisha Toshiba
20140219003 - Temperature based logic profile for variable resistance memory cells: A data storage device may generally be constructed and operated with at least one variable resistance memory cell having a first logic state threshold that is replaced with a second logic state threshold by a controller. The first and second logic states respectively corresponding to a predicted resistance shift that... Agent: Seagate Technology LLC
20140219007 - Dram with segmented page configuration: This description is directed to a dynamic random access memory (DRAM) array having a plurality of rows and a plurality of columns. The array further includes a plurality of cells, each of which are associated with one of the columns and one of the rows. Each cell includes a capacitor... Agent: Nvidia Corporation
20140219008 - Semiconductor memory device with hierarchical bitlines: A dynamic random access memory (DRAM) device has a hierarchical bitline structure with local bitlines and global bitlines formed on different metal layers. The local bitlines are separated into a plurality of local bitline sections, and bitline isolation switches are configured to connect or disconnect the local bitline sections to... Agent: Rambus Inc.
20140219009 - Low voltage bootstrapping method for write assist: Embodiments of a memory are disclosed that may allow for a negative boost of data lines during a write. The memory device may include a data input circuit, an address decode circuit and a plurality of sub-arrays. Each of the sub-arrays may include a plurality of columns, a write selection... Agent: Apple Inc.
20140219010 - Semiconductor device: A logic circuit in a system LSI is provided with a power switch so as to cut off the switch at the time of standby, reducing leakage current. At the same time, an SRAM circuit of the system LSI controls a substrate bias to reduce leakage current.... Agent: Renesas Electronics Corporation
20140219011 - Systems and methods of sectioned bit line memory arrays, including hierarchical and/or other features: A sectioned bit line of an SRAM memory device, an SRAM memory device having a sectioned bit line, and associated systems and methods are described, including embodiments having sectioned bit lines with hierarchical aspects. In one illustrative implementation, each sectioned bit line may comprise a local bit line, a memory... Agent: Gsi Technology Inc.
20140219012 - Magnetic state element and circuits: Described is an apparatus, for spin state element device, which comprises: a variable resistive magnetic (VRM) device to receive a magnetic control signal to adjust resistance of the VRM device; and a magnetic logic gating (MLG) device, coupled to the VRM device, to receive a magnetic logic input and perform... Agent:
20140219013 - Method and apparatus for reading a magnetic tunnel junction using a sequence of short pulses: A magnetic random access memory (MRAM) array having a magnetic tunnel junction (MTJ) to be read using a magnetic state of the MTJ, the MTJ being read by applying a current there through. Further, the MRAM array has a reference MTJ, a sense amplifier coupled to the MTJ and the... Agent: Avalanche Technology, Inc.
20140219014 - Nonvolatile memory device and writing method thereof: A writing method of a nonvolatile memory device is provided which receiving data, a target time, and a target resistance value; writing the data at a memory cell; calculating a resistance drift coefficient based on resistance values of the memory cell read on at least two times; calculating a resistance... Agent:
20140219017 - Capacitor-less memory cell, device, system and method of making same: A capacitor-less memory cell, memory device, system and process of forming the capacitor-less memory cell include forming the capacitor-less memory cell in an active area of a substantially physically isolated portion of a bulk semiconductor substrate. A pass transistor is formed on the active area for coupling with a word... Agent: Micron Technology, Inc.
20140219015 - System and method of programming a memory cell: A method includes creating a breakdown condition at a semiconductor transistor structure that includes an overlap region and a channel region. The breakdown condition is created by causing a first voltage difference between a gate of the semiconductor transistor structure and the overlap region to exceed a breakdown voltage of... Agent: Qualcomm Incorporated
20140219016 - System and method of programming a memory cell: A method includes selectively creating a first breakdown condition and a second breakdown condition at a semiconductor transistor structure. The first breakdown condition is between a source overlap region of the semiconductor transistor structure and a gate of the semiconductor transistor structure. The second breakdown condition is between ad rain... Agent: Qualcomm Incorporated
20140219020 - Memory system comprising nonvolatile memory device and program method thereof: A memory system includes a nonvolatile memory device, and a memory controller configured to control the nonvolatile memory device such that memory cells connected with a selected row of the nonvolatile memory device are programmed by one of a first program mode and a second program mode. At the first... Agent:
20140219018 - Non-volatile memory device: A non-volatile memory device comprising a memory cell array including memory cells distributed among a plurality of sectors; a controller operable to program, read, and erase memory cells in said memory array, said controller further operable to generate and store EPLI values for programming a number of EPLI bits in... Agent: Spansion LLC.
20140219019 - Solid state drive and data erasing method thereof: A data erasing method of a solid state drive is provided. The solid state drive includes a memory module. The memory module includes a block. A data to be erased is stored in the block. The data erasing method includes steps of performing a first erasing operation to erase the... Agent:
20140219021 - Data protection for unexpected power loss: A data storage device receives a write data command and data. The data is stored in a buffer of the data storage device. The data storage device issues a command complete status indication. After the command complete status indication is issued, the data are stored in a primary memory of... Agent: Seagate Technology LLC
20140219022 - Smart bridge for memory core: An apparatus includes a semiconductor device that includes a multi-ported three-dimensional (3D) memory. The multi-ported 3D memory includes multiple memory cells arranged in multiple physical levels above a substrate. The multi-ported 3D memory includes circuitry associated with operation of the multiple memory cells.... Agent: Sandisk Technologies Inc.
20140219023 - Bad column management with bit information in non-volatile memory systems: Column based defect management techniques are presented. Each column of the memory has an associated isolation latch or register whose value indicates whether the column is defective, but in addition to this information, for columns marked as defective, additional information is used to indicate whether the column as a whole... Agent: Sandisk Technologies Inc.
20140219026 - Method and apparatus for leakage suppression in flash memory in response to external commands: Techniques are described herein for detecting and recovering over-erased memory cells in a flash memory device. In one embodiment, a flash memory device includes a memory array including a plurality of blocks of memory cells. The device also includes a command interface to receive a command from a source external... Agent: Macronix International Co., Ltd.
20140219024 - Nonvolatile semiconductor memory device: Word lines extend in a first direction and are commonly connected to memory cells in a plurality of NAND cell units. Bit lines extend in a second direction crossing to the first direction and connected to one ends of the NAND cell units. In one block, both a first and... Agent: Kabushiki Kaisha Toshiba
20140219025 - Program and read methods of memory devices using bit line sharing: A program method of a nonvolatile memory device includes loading first word line data to be stored in first memory cells connected to a first word line and second word line data to be stored in second memory cells connected to a second word line; setting up upper bit lines... Agent: Samsung Electronics Co., Ltd.
20140219027 - Programming select gate transistors and memory cells using dynamic verify level: Programming accuracy is increased for select gate transistors and memory cells by using a dynamic verify voltage which increases from an initial level to a final level during a programming operation. Faster-programming transistors are locked out from programming before slower-programming transistors, but experience program disturb which increases their threshold voltage... Agent: Sandisk Technologies Inc.
20140219028 - Compensation loop for read voltage adaptation: The disclosure is directed to a system and method for nominal read voltage variations of a flash device. N reads are performed, each at a selected voltage offset from an initial read voltage. An N bit digital pattern associated with the selected voltage offsets is generated for the N reads.... Agent: Lsi Corporation
20140219030 - High density vertical structure nitride flash memory: A charge trap type of memory having a memory channel with vertical and possibly horizontal components is described. The invention includes a new operation method of simultaneous hole and electron injection operation for high speed and high reliability non-volatile memories, as well as high-density non-volatile memories. Array implementations for high-density... Agent: Halo Lsi, Inc.
20140219029 - Programming method for nonvolatile semiconductor memory device: A method for programming a plurality of memory cells of a nonvolatile semiconductor memory device comprises the steps of: dividing the plurality of memory cells into M number of groups (M is an integer); successively selecting each of the M number of groups; generating M number of successive overlapping pulse... Agent: Elite Semiconductor Memory Technology Inc.
20140219031 - Smart bridge for memory core: An apparatus includes a first semiconductor device including a three-dimensional (3D) memory. The 3D memory includes multiple memory cells arranged in multiple physical levels above a substrate. The 3D memory further includes circuitry associated with operation of the multiple memory cells. The apparatus includes a second semiconductor device coupled to... Agent: Sandisk Technologies Inc.
20140219033 - Flash multiple-pass write with accurate first-pass write: An indication to store a data value in Flash memory is received. An accurate coarse write is performed on the Flash memory, including by: storing a first voltage level in the Flash memory and setting a configuration setting of the Flash memory to a first setting. The first voltage level,... Agent: Sk Hynix Memory Solutions Inc.
20140219032 - Methods for programming a memory device and memory devices: Methods for programming memory cells and memory devices are disclosed. One such method for programming includes performing a program verify operation of a group of memory cells. A number of potential CS2 situations are detected. If the number of detected potential CS2 situations is greater than a threshold, programming compensation... Agent: Micron Technology, Inc.
20140219034 - Non-volatile write buffer data retention pending scheduled verification: Method and apparatus for managing data in a memory. In accordance with some embodiments, a non-volatile (NV) buffer is adapted to store input write data having a selected logical address. A write circuit is adapted to transfer a copy of the input write data to an NV main memory while... Agent: Seagate Technology LLC
20140219035 - Semiconductor memory device: Based on a continuous erase start signal outputted, in response to an inputted continuous erase command, from a continuous erase control circuit, a shift circuit outputs a control signal for giving instructions to execute respective data erase operation to a plurality of non-volatile memory circuits sequentially, and when the data... Agent: Spansion LLC
20140219036 - Equalizer and semiconductor memory device including the same: Provided are an equalizer and a semiconductor memory device including the same. The equalizer includes a delay circuit and an inverting circuit. The delay circuit is configured to output, in response to a select signal, one of a delay signal delaying an input signal applied to an input/output node and... Agent: Samsung Electronics Co., Ltd.
20140219037 - Non-volatile semiconductor memory device and semiconductor device: Provided is a semiconductor non-volatile memory device capable of improving the accuracy of trimming by creating a written state before data is written into a non-volatile memory element. The semiconductor non-volatile memory device includes: a written data transmission circuit for transmitting written data to a non-volatile memory element; a first... Agent: Seiko Instruments Inc.
20140219038 - Devices and methods for deciding data read start: A data read start decision device includes: a storing circuit configured to store code key data; a read check circuit configured to output a read start signal in response to code key data read from the storing circuit, and a controller configured to start reading environment setting data from the... Agent: Samsung Electronics Co., Ltd.
20140219039 - Write driver for write assistance in memory device: A write assist driver circuit is provided that assists a memory cell (e.g., volatile memory bit cell) in write operations to keep the voltage at the memory core sufficiently high for correct write operations, even when the supply voltage is lowered. The write assist driver circuit may be configured to... Agent: Qualcomm Incorporated
20140219040 - Semiconductor memory device including bulk voltage generation circuit: A semiconductor memory device includes a bulk voltage generation circuit configured to interrupt driving of a bulk voltage in response to an exit signal which is generated in synchronization with a time at which a power-down mode is ended, and discharge charges of a first node from which the bulk... Agent: Sk Hynix Inc.
20140219041 - Storage device and data processing method thereof: A method of processing data in a storage device includes writing first data to a data storage unit of the storage device upon receiving the first data from an external host of the storage device, outputting a message to the external host indicating completion of writing the first data to... Agent: Samsung Electronics Co., Ltd.
20140219042 - Memory device and method of refreshing in a memory device: In a method of refreshing in a memory device having a plurality of pages, a candidate refresh address corresponding to a page scheduled to be refreshed after a monitoring period is generated. Whether an active command is processed for the candidate refresh address is monitored during the monitoring period. If... Agent: Samsung Electronics Co., Ltd.
20140219043 - Apparatuses and methods for targeted refreshing of memory: Apparatuses and methods for targeted row refreshes are disclosed herein. In an example apparatus, a predecoder receives a target row address and determines whether a target row of memory associated with the target row address is a primary or a redundant row of memory. The predecoder is further configured to... Agent: Micron Technology, Inc.
20140219044 - Memory module and memory system comprising same: A memory module comprises a plurality of semiconductor memory devices each comprising a mode register set (MRS) circuit configured to generate an enable signal corresponding to an error mode of the semiconductor memory device in response to an MRS command received from a command decoder, and an address buffer configured... Agent: Samsung Electronics Co., Ltd.07/31/2014 > 51 patent applications in 30 patent subcategories.
07/24/2014 > 54 patent applications in 33 patent subcategories.
20140204644 - Longest prefix match internet protocol content addressable memories and related methods: Embodiments of content addressable memories for internet protocol devices and operations are described herein. Other examples and related methods are also disclosed herein.... Agent: Arizona Board Of Regents For And On Behalf Of Arizona State University
20140204646 - High current capable access device for three-dimensional solid-state memory: The present invention generally relates to three-dimensional arrangement of memory cells and methods of addressing those cells. The memory cells can be arranged in a 3D orientation such that macro cells that are in the middle of the 3D arrangement can be addressed without the need for overhead wiring or... Agent: Hgst Netherlands B.v.
20140204645 - Semiconductor device: To supply a signal in which the occurrence of delays is prevented to a storage circuit. To provide a novel semiconductor device in which a load applied to a logic circuit is low. The following structure is completed: a storage circuit to which a plurality of data signals and a... Agent: Semiconductor Energy Laboratory Co., Ltd.
20140204647 - Racetrack memory cells with a vertical nanowire storage element: A racetrack memory cell device include a dielectric, an electrode disposed in the dielectric, a metal strap disposed in the dielectric, a nanowire disposed in the dielectric between the electrode and the metal strap and a magnetic tunnel junction disposed in the dielectric on the metal strap, and axially with... Agent: International Business Machines Corporation
20140204648 - Racetrack memory cells with a vertical nanowire storage element: A racetrack memory cell device include a dielectric, an electrode disposed in the dielectric, a metal strap disposed in the dielectric, a nanowire disposed in the dielectric between the electrode and the metal strap and a magnetic tunnel junction disposed in the dielectric on the metal strap, and axially with... Agent: International Business Machines Corporation
20140204649 - Memory element, semiconductor device, and writing method: A memory element includes: an electrical fuse provided to be inserted between a first input node and a second input node; and an antifuse provided to be inserted between the second input node and a third input node. The third input node is configured to be a node to which... Agent: Sony Corporation
20140204650 - Nonvolatile resistive memory device and writing method: A writing method for a resistive nonvolatile memory device includes writing data to a resistive nonvolatile memory cell using an up/down write pulse signal when the data is first data type, and writing data to the resistive nonvolatile memory cell using only one of an up write pulse signal and... Agent:
20140204651 - Reading a memory element within a crossbar array: A method for reading a memory element within a crossbar array includes switching a column line connected to a target memory element of the crossbar array to connected to an input of a current mirror; applying an error voltage to unselected rows of the crossbar array; applying a sense voltage... Agent: Hewlett-packard Development Company, L.p.
20140204652 - Resistive memory device: A resistive memory device includes memory cell array blocks, a reference cell array block, two first and second sink transistors, and a word line. Each of the memory cell array blocks includes a row line, and the reference cell array block includes a reference row line. One of the first... Agent: Samsung Electronics Co., Ltd.
20140204653 - Semiconductor memory device: A semiconductor memory device includes: a plurality of word lines extending in a first direction; first to third bit lines extending in a second direction that intersects with the first direction; a plurality of variable resistance elements each having a first terminal connected to either one of the first and... Agent: Kabushiki Kaisha Toshiba
20140204654 - Complementary metal-oxide-semiconductor (cmos) dynamic random access memory (dram) cell with sense amplifier: A complementary metal-oxide-semiconductor (CMOS) dynamic random access memory (DRAM) cell with sense amplifier is described. In one embodiment, the DRAM cell includes an n-type field-effect transistor (NFET), a p-type field-effect transistor (PFET), and a storage capacitor accessed through both the NFET and the PFET. A pair of bit lines is... Agent: International Business Machines Corporation
20140204655 - Memory device, semiconductor device, and detecting method: To provide a memory device which can perform verification operation for detecting a memory cell whose data holding time is shorter than a predetermined length, accurately in a short time. Each memory cell includes at least a first capacitor, a second capacitor, and a transistor which functions as a switching... Agent: Semiconductor Energy Laboratory Co., Ltd.
20140204656 - Low voltage dual supply memory cell with two word lines and activation circuitry: A memory cell includes a latch having a true data node and a complement data node, a true bitline, a complement bitline, a first access transistor coupled between the true bitline and the true data node, and a second access transistor coupled between the complement bitline and the complement data... Agent: Stmicroelectronics International N.v.
20140204658 - Memory cell flipping for mitigating sram bti: An apparatus may comprise a memory cell configured to operate according to a voltage mode, a voltage controller coupled with the memory cell, wherein the voltage controller is configured to change the voltage mode of the memory cell between a low voltage mode and a high voltage mode, and a... Agent: Advanced Micro Devices, Inc.
20140204657 - Sram voltage assist: The disclosure provides for an SRAM array having a plurality of wordlines and a plurality of bitlines, referred to generally as SRAM lines. The array has a plurality of cells, each cell being defined by an intersection between one of the wordlines and one of the bitlines. The SRAM array... Agent: Nvidia Corporation
20140204659 - Capacitive coupled sense amplifier biased at maximum gain point: A sense amplifier includes a first inverter including a first input node and a first output node, the first input node coupled to a first bitline through a first capacitor, the first output node coupled to a second bitline through a second capacitor, a second inverter including a second input... Agent: Lsi Corporation
20140204660 - Memory having sense amplifier for output tracking by controlled feedback latch: In described embodiments, a memory circuit includes a static random access memory (SRAM) including N banks of memory cells, rows of M sense amplifiers, a controlled feedback latch storing a previous state of input data in a read cycle, a pull down select block coupled to the controlled feedback latch... Agent: Lsi Corporation
20140204662 - Apparatus for initializing perpendicular mram device: The present invention is directed to an apparatus for initializing perpendicular magnetic tunnel junction. The apparatus comprises a permanent magnet for generating a magnetic flux; a flux concentrator made of a soft ferromagnetic material and having a base area in contact with the permanent magnet and an tip area that... Agent: Avalanche Technology Inc.
20140204661 - Memory with elements having two stacked magnetic tunneling junction (mtj) devices: A magnetic memory having memory elements each with two magnetic tunneling junction (MTJ) devices is disclosed. The devices in each element are differentially programmed with complementary data. The devices for each element are stacked one above the other so that the element requires no more substrate area than a single... Agent:
20140204663 - Efficient pcms refresh mechanism: An apparatus is described having invert determination logic circuitry to determine if a read data path that transports data read from a PCMS memory device is to be inverted or not inverted as a function of whether information represented by the data was last written in an inverted or non... Agent:
20140204664 - Method of driving phase change memory device capable of reducing heat disturbance: A method of driving phase change memory device includes initializing all memory cells and programming individually at least two selected memory cells disposed at random positions, wherein the selected memory cells are selected among the initialized memory cells.... Agent: Sk Hynix Inc.
20140204665 - Multilevel differential sensing in phase change memory: Methods and systems for multi-bit phase change memories. Using differential sensing for memory reads provides advantages including improved temperature and drift resilience, improved state discrimination and increased storage density.... Agent: Being Advanced Memory Corporation
20140204666 - Robust initialization with phase change memory cells in both configuration and array: The present application discloses phase-change memory architectures and methods, in which an additional test is performed, after the normal power-valid signal, to assure that the phase-change memory components which are used for storing configuration data are able to operate correctly. Surprisingly, the inventor has discovered that this additional test is... Agent: Being Advanced Memory Corporation
20140204667 - Robust initialization with phase change memory cells in both configuration and array: The present application discloses phase-change memory architectures and methods, in which an additional test is performed, after the normal power-valid signal, to assure that the phase-change memory components which are used for storing configuration data are able to operate correctly. Surprisingly, the inventor has discovered that this additional test is... Agent: Being Advanced Memory Corporation
20140204668 - Robust initialization with phase change memory cells in both configuration and array: The present application discloses phase-change memory architectures and methods, in which an additional test is performed, after the normal power-valid signal, to assure that the phase-change memory components which are used for storing configuration data are able to operate correctly. Surprisingly, the inventor has discovered that this additional test is... Agent: Being Advanced Memory Corporation
20140204669 - System and method of quantum computing using three-state representation of a qubit: A method (and structure) of quantum computing. Two independent magnitudes of a three-state physical (quantum) system are set to simultaneously store two real, independent numbers as a qubit. The three-state physical (quantum) system has a first energy level, a second energy level, and a third energy level capable of being... Agent: International Business Machines Corporation
20140204670 - Semiconductor memory device using only single-channel transistor to apply voltage to selected word line: A semiconductor memory device has a memory cell array, a first transistor of a first conductivity type, a second transistor of a second conductivity type and a third transistor of the first conductivity type. A source or drain of the first transistor is connected to each of word lines. A... Agent: Kabushiki Kaisha Toshiba
20140204671 - Systems and methods of updating read voltages: A method includes, in a data storage device that includes a non-volatile memory, reading data from the non-volatile memory using a first read voltage. The method includes determining a first count of errors in the data having a first error type and a second count of errors in the data... Agent: Sandisk Technologies Inc.
20140204673 - Flash memory module for realizing high reliability: A flash memory module may include a plurality of flash memory chips. The memory chips may include one or more blocks. Each block may be a unit of erasing data. A flash controller may be coupled to the plurality of flash memory chips. The flash controller may program data to... Agent: Hitachi, Ltd.
20140204672 - Memory system: A memory system includes a flash memory including a block having first sub-blocks and second sub-blocks different from each other, the second sub-blocks including free pages only; and a controller configured to erase the flash memory in units of the sub-blocks, and in a garbage collection operation, the controller is... Agent:
20140204674 - Line voltage boost system and method for non-volatile memory devices and memory devices and processor-based system using same: The voltage of a selected word line is increased beyond the voltage to which a respective string driver transistor is capable of driving the word line by capacitively coupling a voltage to the selected word line from adjacent word lines. The voltage is capacitively coupled to the selected word line... Agent: Micron Technology, Inc.
20140204675 - Multi-page program method, non-volatile memory device using the same, and data storage system including the same: A method of programming a non-volatile memory device including a plurality of strings arranged in rows and columns comprises activating all or a part of selection lines in one column at the same time depending upon data to be programmed, driving a bit line corresponding to the one column with... Agent: Samsung Electronics Co., Ltd
20140204677 - Apparatuses and methods including memory write operation: Some embodiments include apparatuses and methods having memory cells and access lines coupled to the memory cells. In one such apparatus, the access lines include a first access line and a second access line. The first access line can be adjacent to the second access line. The memory cells include... Agent: Micron Technology, Inc.
20140204676 - High voltage switch and a nonvolatile memory device including the same: A high voltage switch of a nonvolatile memory device includes a depletion type NMOS transistor configured to switch a second driving voltage in response to an output signal of the high voltage switch; at least one inverter configured to convert a voltage of an input signal of the high voltage... Agent: Samsung Electronics Co., Ltd.
20140204678 - Dynamic detection method for latent slow-to-erase bit for high performance and high reliability flash memory: A method and apparatus for detecting a latent slow bit (e.g., a latent slow-to-erase bit) in a non-volatile memory (NVM) is disclosed. A maximum number of soft program pulses among addresses during an erase cycle is counted. In accordance with at least one embodiment, a number of erase pulses during... Agent:
20140204679 - Programming and/or erasing a memory device in response to its program and/or erase history: For one embodiment, a programming method includes programming one or more memory cells of a memory device during a programming operation, determining, internal to the memory device, a number of program pulses required to program a sample of the one or more memory cells of the memory device during the... Agent: Micron Technology, Inc.
20140204680 - Nonvolatile memory device, memory system having the same, external power controlling method thereof: An external power control method includes determining whether to apply a second external voltage to a first node according to a drop of a first external voltage; generating a flag signal according to a drop of the second external voltage when the second external voltage is applied to the first... Agent: Samsung Electronics Co., Ltd.
20140204681 - Semiconductor memory device and method of operating the same: A semiconductor memory device includes strings each configured to include a drain select transistor, memory cells, and a source select transistor coupled in series between a bit line and a common source line and peripheral circuits configured to perform an operation of precharging a bit line so that the precharge... Agent: Sk Hynix Inc.
20140204688 - Reference current distribution: Example reference current distribution circuitry described herein include current mirrors having resistive elements of varying sizes between gate nodes of sense amplifier transistors along a voltage, distribution line. Examples of counter coupling capacitances which may be coupled to the gate nodes of sense amplifier transistors are also described.... Agent: Micron Technology, Inc.
20140204682 - Method and apparatus for simultaneously accessing a plurality of memory cells in a memory array to perform a read operation and/or a write operation: A memory system includes a memory array and a read/write module. The memory array includes bit lines, word lines, and memory cells. Each of the memory cells is located at an intersection of a respective one of the bit lines and a respective one of the word lines. The memory... Agent:
20140204685 - Circuits, devices, systems, and methods of operation for capturing data signals: Embodiments of the invention describe driving data onto a bus. The embodiments include a data driver circuit having a data capture circuit coupled to the bus. The data capture circuit receives data relative to a write strobe signal and captures a first digit of the data responsive to a first... Agent: Micron Technology, Inc.
20140204683 - Margin free pvt tolerant fast self-timed sense amplifier reset circuit: In described embodiments, a circuit for providing a margin free PVT tolerant fast self-timed sense amplifier reset includes a sense amplifier coupled between a complementary pair of first and second bitlines in a memory cell, a first and second PMOS drivers connected to internal nodes of the sense amplifier, respectively,... Agent: Lsi Corporation
20140204684 - Nonvolatile memory devices, memory systems and related control methods: A nonvolatile memory device includes a cell array including a plurality of cell strings extending on a substrate in a vertical direction, a page buffer connected to a plurality of bit lines and configured to store sensing data of the cell array in a sensing operation, a voltage generator configured... Agent:
20140204686 - Operation method of a supply voltage generation circuit used for a memory array: A supply voltage generation circuit includes a comparison unit, a voltage level control unit and a voltage regulator circuit. Comparison unit is configured to compare input data and output data of a memory array to each other and thereby generating a comparison result, wherein output data are storage data stored... Agent: United Microelectronics Corporation
20140204687 - System and method for performing address-based sram access assists: A method and a system are provided for performing address-based memory access assist. An address is received for a memory access and a determination is made, based on the address, that access assist is enabled for at least one storage cell corresponding to the address. The access assist is applied... Agent: Nvidia Corporation
20140204689 - Apparatus and methods of driving signal for reducing the leakage current: Apparatus and methods for driving a signal are disclosed. An example apparatus includes a pre-driver circuit and a driver circuit. The pre-driver circuit includes a step-down transistor and the driver circuit includes a pull-down transistor configured to be coupled to a reference voltage. In a first mode, the step-down transistor... Agent: Micron Technology, Inc.
20140204690 - Stacked-die memory systems and methods for training stacked-die memory systems: Systems and methods are disclosed herein, such as those that operate to control a set of delays associated with one or more data clocks to clock a set of data bits into one or more transmit registers, one or more data strobes to transfer the set of data bits to... Agent: Micron Technology, Inc.
20140204691 - Source synchronous bus signal alignment compensation mechanism: An apparatus having a bit lag control element that measures a propagation time beginning with assertion of a first signal and ending with assertion of a second signal, and that generates a first value indicating an adjusted propagation time. The control element includes delay lock control, adjust logic, and a... Agent: Via Technologies, Inc.
20140204692 - Semiconductor memory device and method with auxiliary i/o line assist circuit and functionality: A semiconductor memory device includes an I/O line for transmitting read data that has been read from a memory cell, a plurality of driver circuits for driving the I/O line on the basis of the read data, a read circuit for receiving the read data transmitted through the I/O line,... Agent: Elpida Memory, Inc.
20140204693 - Applying a voltage-delay correction to a non-defective memory block that replaces a defective memory block based on the actual location of the non-defective memory block: In an embodiment, a defective memory block is replaced with a non-defective memory block, and a voltage-delay correction is applied to the non-defective memory block that replaces the defective memory block based on the actual location of the non-defective memory block.... Agent: Micron Technology, Inc.
20140204694 - Systems and methods for adaptive soft programming for non-volatile memory using temperature sensor: Erasing of a non-volatile memory (NVM) having an array of bit cells includes soft programming after an initial erasing of the bit cells. Over-erased bit cells are determined. A temperature is detected. A first soft program gate voltage based on the temperature is provided. Soft programming on the over-erased bit... Agent:
20140204695 - Method and apparatus for increasing yield: Aspects of the disclosure provide an integrated circuit (IC) that is configured to have an increased yield. The IC includes a memory element configured to store a specific value determined based on a characteristic of the IC, and a controller configured to control an input regulator based on the specific... Agent: Marvell Israel (m.i.s.l) Ltd.
20140204696 - Memory device and semiconductor device: Provided is a memory device with reduced overhead power. A memory device includes a first circuit retaining data in a first period during which a power supply voltage is supplied; a second circuit saving the data retained in the first circuit in the first period and retaining the data saved... Agent: Semiconductor Energy Laboratory Co., Ltd.
20140204697 - Integrated circuits and methods for dynamic frequency scaling: In an integrated circuit, a first delay locked loop circuit is configured to adjust a phase of a first clock signal input to a first clock input terminal, and to at least one of transmit and receive information based on the phase-adjusted first clock signal. A second delay locked loop... Agent: Samsung Electronics Co., Ltd.07/17/2014 > 48 patent applications in 31 patent subcategories.
20140198551 - Content addressable memory device having electrically floating body transistor: A content addressable memory cell includes a first floating body transistor and a second floating body transistor. The first floating body transistor and the second floating body transistor are electrically connected in series through a common node. The first floating body transistor and the second floating body transistor store complementary... Agent:
20140198552 - Three-dimensional semiconductor devices and methods of fabricating the same: According to example embodiments of inventive concepts, a three-dimensional semiconductor device may include: a memory cell array including memory cells that may be arranged three-dimensionally, the memory cell array including a left side opposite a right side, and a top side opposite a bottom side in a plan view; at... Agent:
20140198553 - Integrated circuit 3d phase change memory array and manufacturing method: A 3D phase change memory device can store multiple bits per cell represented by a plurality of non-overlapping ranges of resistance all of which are established by different resistance ranges corresponding to respective amorphous phase thickness of the phase change memory material. An array of access devices can underlie a... Agent: Macronix International Co., Ltd.
20140198555 - Methods and apparatus for rom devices: Methods and apparatus for the encoding of an input sequence of digit data into a sequence of storage cells of a ROM device are disclosed. The input sequence is divided into a first kind of groups and a second kind of groups. A first kind of group comprises a plurality... Agent: Taiwan Semiconductor Manufacturing Company, Ltd.
20140198554 - Semiconductor device having features to prevent reverse engineering: A ROM circuit includes a first N channel transistor having an output and having device geometry and device characteristics adapted to bias the output at a predetermined level when a P channel circuit is connected to the first N channel transistor; a pass transistor connected between the output and a... Agent: Static Control Components, Inc.
20140198559 - Circuit and method for reading a resistive switching device in an array: A read circuit for sensing a resistance state of a resistive switching device in a crosspoint array utilizes a transimpedance equipotential preamplifier connected to a selected column line of the resistive switching device in the array. The equipotential preamplifier delivers a sense current while maintaining the selected column line at... Agent:
20140198558 - Non-volatile storage system using opposite polarity programming signals for mim memory cell: A reversible resistance-switching metal-insulator-metal (MIM) stack is provided which can be set to a low resistance state with a first polarity signal and reset to a higher resistance state with a second polarity signal. The first polarity signal is opposite in polarity than the second polarity signal. In one approach,... Agent: Sandisk 3d LLC
20140198556 - Nonvolatile memory device using variable resistive element and memory system having the same: A nonvolatile memory device, which has an improved read reliability through a refresh operation, and a memory system, are provided. The nonvolatile memory device includes a resistive memory cell, a reference resistor corresponding to the resistive memory cell, a reference sense amplifier electrically connected to the reference resistor and configured... Agent: Samsung Electronics Co., Ltd.
20140198557 - Read circuit and non-volatile memory using the read circuit: A read circuit includes a current load circuit configured to supply a load current from a power source to a first input and a second input; a first discharge circuit configured to discharge potential of the first and second inputs to a ground level; an equalization circuit configured to equalize... Agent: Panasonic Corporation
20140198560 - Memory cell and memory device having the same: A memory cell includes a metal oxide semiconductor (MOS) capacitor including a gate coupled to a storage node and an electrode coupled to a synchronization control line. The MOS capacitor adds a coupling voltage to the gate based on a change in voltage on the synchronization control line. The coupling... Agent:
20140198561 - Multiport memory with matching address and data line control: In a multiple port SRAM, a first bit cell is coupled to first and second word lines and a first and second bit line pair. A first data line pair is coupled to the first bit line pair via first switching logic. A second data line pair is coupled to... Agent:
20140198562 - Ten-transistor dual-port sram with shared bit-line architecture: A 10-transistor dual-port SRAM with shared bit-line architecture includes a first memory cell and a second memory cell. The first memory cell has a first storage unit, a first switch set, and a second switch set. The second memory cell has a second storage unit, a third switch set, and... Agent: National Chiao Tung University
20140198563 - Magnetic tunneling junction non-volatile register with feedback for robust read and write operations: A magnetic tunneling junction non-volatile register with feedback for robust read and write operations. In an embodiment, two MTJ devices are configured to store a logical 0 or a logical 1, and are coupled to drive an output node to a voltage indicative of the stored logical 0 or a... Agent: Qualcomm Incorporated
20140198564 - Magnetoresistive element and method of manufacturing the same: A planar STT-MRAM comprises apparatus, a method of operating and a method of manufacturing a spin-torque magnetoresistive memory and a plurality of magnetoresistive memory element having a ferromagnetic recording layer forming a flux closure with a self-aligned ferromagnetic soft adjacent layer which has an electric field enhanced perpendicular anisotropy through... Agent: T3memory, Inc.
20140198565 - Method, system and device for phase change memory with shunt: Embodiments disclosed herein may relate to forming a storage component comprising a phase change material and a shunt relative to amorphous portions of the phase change material.... Agent: Micron Technology, Inc.
20140198567 - Dynamic adjustment of read voltage levels based on memory cell threshold voltage distribution: A system and methods to find the threshold voltage distribution across a set of nonvolatile memory cells, such that embodiments may incorporate this distribution information into calculations that may change the read compare voltages used to read the memory cells, while ensuring adequate separation in read voltage between different data... Agent: Sandisk Technologies Inc.
20140198569 - Flash memory, flash memory system and operating method of the same: A flash memory, a flash memory system, and an operating method thereof. The method of operating a flash memory includes counting the number of memory cells having threshold voltages included in a first adjacent threshold voltage range (defined by a first reference read voltage for distinguishing between initially separated adjacently... Agent:
20140198568 - Non-volatile memory systems and methods: A high speed voltage mode sensing is provided for a digital multibit non-volatile memory integrated system. An embodiment has a local source follower stage followed by a high speed common source stage. Another embodiment has a local source follower stage followed by a high speed source follower stage. Another embodiment... Agent: Silicon Storage Technology, Inc.
20140198570 - Programming multibit memory cells: A multiple bits per cell memory is operated by applying a one-pass, multiple-level programming, using a single pulse sequence one time (or in one-pass), such as an incremental pulse program sequence, with program verify steps for multiple target program levels, to program multiple bits per cell in a plurality of... Agent: Macronix International Co., Ltd.
20140198571 - Selecting memory cells: A memory device comprises memory cells arranged in rows and columns, and source lines associated with memory sections, each of which includes a plurality of memory cells. Source terminals of transistors included in the memory cells in a first memory section are physically coupled to a first source line that... Agent:
20140198572 - String selection structure of three-dimensional semiconductor device: A three-dimensional semiconductor device includes first and second selection lines stacked one on the other. An upper line horizontally crosses over the first and second selection lines. First and second vertical patterns vertically cross the first and second selection lines. The first and second vertical patterns are connected in common... Agent:
20140198573 - Memory system and method of operation thereof: A method of operating a memory system including a non-volatile memory device and a memory controller controlling the non-volatile memory device, includes reading data from a memory cell array in a unit of a page which includes a plurality of sectors; performing error correction decoding on the read data in... Agent:
20140198574 - Nonvolatile memory and manipulating method thereof: A manipulating method of a nonvolatile memory is provided and comprises following steps. The nonvolatile memory having a plurality of memory cell is provided. Two adjacent memory cells correspond to one bit and comprise a substrate, a first and another first doping regions, a second doping region, a charge trapping... Agent: United Microelectronics Corp.
20140198575 - Method and apparatus for program and erase of select gate transistors: Techniques are provided for programming and erasing of select gate transistors in connection with the programming or erasing of a set of memory cells. In response to a program command to program memory cells, the select gate transistors are read to determine whether their Vth is below an acceptable range,... Agent: Sandisk Technologies Inc.
20140198578 - Method of operating a split gate flash memory cell with coupling gate: A method of operating a memory cell that comprises first and second regions spaced apart in a substrate with a channel region therebetween, a floating gate disposed over the channel region and the first region, a control gate disposed over the channel region and laterally adjacent to the floating gate... Agent: Silicon Storage Technology, Inc.
20140198576 - Programming technique for reducing program disturb in stacked memory structures: A programming bias technique is described for programming a stacked memory structure with a plurality of layers of memory cells. The technique includes the controller circuitry responsive to a program instruction to program data in target cells in a stack of cells at a particular multibit address. The circuitry is... Agent: Macronix International Co, Ltd.
20140198577 - Semiconductor device: A semiconductor device includes a plurality of nonvolatile memory cells (1). Each of the nonvolatile memory cells comprises a MOS type first transistor section (3) used for information storage, and a MOS type second transistor section (4) which selects the first transistor section. The second transistor section has a bit... Agent: Renesas Electronics Corporation
20140198579 - Disturb verify for programming memory cells: Apparatuses and methods for disturb verify for programming operations are described. Programming memory cells can include applying a number of programming pulses to a first memory cell, performing a disturb verify operation on a second memory cell adjacent to the first memory cell, and inhibiting the first memory cell from... Agent: Micron Technology, Inc.
20140198566 - Reference current sources: Systems, methods, and devices are disclosed, including an electronic device that includes a first data location, a quantizing circuit, and a reference current source, all coupled to an electrical conductor. The reference current source may include a current mirror with a side coupled to the electrical conductor and a second... Agent: Micron Technology, Inc.
20140198580 - Data path integrity verification: Methods and memories for verifying data path integrity are provided. In one such method, a first set of data are read from a first register of a memory device while a second set of data are written to an array of the memory device. The read first set of data... Agent: Micron Technology, Inc.
20140198581 - Method of storing data in nonvolatile memory device and method of testing nonvolatile memory device: A method of storing data in a nonvolatile memory device comprises performing a program operation on target memory cells among multiple memory cells, performing a first verify operation to determine whether the target memory cells are in a program pass state or a program fail state, and as a consequence... Agent:
20140198582 - Capacitor structures having improved area efficiency: Semiconductor structures including a plurality of conductive structures having a dielectric material therebetween are disclosed. The thickness of the dielectric material spacing apart the conductive structures may be adjusted to provide optimization of capacitance and voltage threshold. The semiconductor structures may be used as capacitors, for example, in memory devices.... Agent: Micron Technology, Inc.
20140198583 - Method and system for reducing the size of nonvolatile memories: Embodiments relate to system and methods including a plurality of nonvolatile memory elements wherein sets of least two nonvolatile memory elements each share one select element for selecting one of the nonvolatile memory elements of a particular one of the sets of nonvolatile memory elements for a read operation or... Agent: Infineon Technologies Ag
20140198588 - N-well switching circuit: A dual-mode PMOS transistor is disclosed that has a first mode of operation in which a switched n-well for the dual-mode PMOS transistor is biased to a high voltage. The dual-mode PMOS transistor has a second mode of operation in which the switched n-well is biased to a low voltage... Agent: Qualcomm Incorporated
20140198584 - Buffering systems for accessing multiple layers of memory in integrated circuits: Embodiments of the invention relate generally to data storage and computer memory, and more particularly, to systems, integrated circuits and methods for accessing memory in multiple layers of memory implementing, for example, third dimension memory technology. In a specific embodiment, an integrated circuit is configured to implement write buffers to... Agent: Iii Holdings 1, LLC
20140198586 - Devices and systems including enabling circuits: Examples of devices and systems including enabling circuits are described. Two voltage supplies may be used to operate different portions of the devices, including peripheral circuits and I/O circuits. When the voltage supply to the peripheral circuits of one or more devices is disabled, the I/O circuits of that device... Agent: Micron Technology, Inc.
20140198585 - Semiconductor memory apparatus: A semiconductor memory apparatus includes: a data output signal transmitter configured to receive a data signal and a data mask signal and transmit a data output signal through a global data line, the data output signal being outputted by determining whether the data signal is masked or not; and a... Agent: Sk Hynix Inc.
20140198587 - Pre-charge voltage generation and power saving modes: A system includes a voltage generator to produce a pre-charge voltage signal for pre-charging one or more signals in a memory circuit. The one or more signals can be data bus lines used to access memory. The voltage generator can include an input indicating whether the memory circuit is set... Agent: Mosaid Technlogies Incorporated
20140198589 - Memory core and semiconductor memory device including the same: A semiconductor device may include a first memory cell connected to a bit-line and a first word-line, a second memory cell connected to a complementary bit-line and a second word-line, and an equalizer. The equalizer may be configured to transition a voltage of the bit-line and the complementary bit-line from... Agent: Samsung Electronics Co., Ltd.
20140198590 - Multiport memory with matching address control: In a multiple port SRAM, a first bit cell is coupled to first and second word lines and a first and second bit line pair. A second bit cell is coupled to the first and second word lines and a third and fourth bit line pair. A first data line... Agent:
20140198591 - Apparatuses and methods for controlling a clock signal provided to a clock tree: Apparatuses, sense circuits, and methods for controlling a clock signal to a clock tree is described. An example apparatus includes a consecutive write command detection circuit configured to detect whether a next write command is received within a consecutive write command period of a current write command responsive to the... Agent: Micron Technology, Inc.
20140198592 - Fault masking method for non-volatile memories: A fault masking method is applied to a non-volatile memory array which includes a faulty cell and electrically connected to an address register providing a first address. The faulty cell can only output a fixed value. The content of the first address is not equal to the fixed value. The... Agent:
20140198593 - Redundancy circuit and semiconductor memory device including the same: A redundancy circuit includes a redundancy decoder, a fuse array, and a decoder. The redundancy decoder decodes a redundancy enable signal generated when an address of a defective cell matches an input address. The decoded redundancy enable signal is used to activate a spare column select line connected with a... Agent: Samsung Electronics Co., Ltd.
20140198595 - Multiple read port memory system with a single port memory cell: An improved multi-port register file system and method of operating. The multi-port register file memory system comprises: n single memory bit cells each storing a data value and having a single bit cell write port and a single read port connecting a respective local bit line, wherein corresponding parallel activated... Agent: International Business Machines Corporation
20140198594 - Variable pre-charge levels for improved cell stability: Embodiments of a memory device are disclosed that may allow for multiple pre-charge voltages. The memory device may include a plurality of data lines, and a plurality of pre-charge circuits. Each of the plurality of data lines may be coupled to a plurality of data storage cells. Each of the... Agent: Apple Inc.
20140198596 - Circuit for controlling sense amplifier source node in semiconductor memory device and controlling method thereof: Provided is a bit line sense amplifier source node control circuit of a semiconductor memory device. The sense amplifier source node control circuit may include a source driver connected between a source node of a sense amplifier and a sense amplifier driving signal line, for driving the source node of... Agent: Samsung Electronics Co., Ltd.
20140198597 - Dynamic random access memory for communications systems: An integrated circuit may comprise a digital logic circuit, a memory refresh circuit, a first one or more dynamic random access memory (DRAM) cells, and a second one or more DRAM cells. The first DRAM cell(s) may be refreshed by the memory refresh circuit whereas the second DRAM cell(s) is... Agent: Maxlinear, Inc.
20140198598 - System and method of performing power on reset for memory array circuits: The disclosure relates to an apparatus for deactivating one or more predecoded address lines of a memory circuit in response to one or more of the predecoded address lines being activated upon powering on of at least a portion of the apparatus. In particular, the apparatus includes a memory device;... Agent: Qualcomm IncorporatedPrevious industry: Electric power conversion systems
Next industry: Agitating
RSS FEED for 20140807:
Integrate FreshPatents.com into your RSS reader/aggregator or website to track weekly updates.
For more info, read this article.
Thank you for viewing Static information storage and retrieval patents on the FreshPatents.com website. These are patent applications which have been filed in the United States. There are a variety ways to browse Static information storage and retrieval patent applications on our website including browsing by date, agent, inventor, and industry. If you are interested in receiving occasional emails regarding Static information storage and retrieval patents we recommend signing up for free keyword monitoring by email.
Results in 0.99214 seconds