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Static information storage and retrieval

Below are recently published patent applications awaiting approval from the USPTO. Recent week's RSS XML file available below.
Listing for abstract view: USPTO application #, Title, Abstract excerpt,Patent Agent. Listing format for list view: USPTO National Class full category number, title of the patent application.
  
05/21/2015 > 46 patent applications in 24 patent subcategories.

20150138861 - Content addressable memory: This disclosure provides a content addressable memory which includes: a data memory cell for storing a data bit; a mask memory cell for storing a mask bit; and a comparing and readout unit connected to at least one read word line for receiving at least one read word signal, connected... Agent:

20150138862 - Three-dimensional semiconductor devices and fabricating methods thereof: A three-dimensional (3D) semiconductor memory device includes a CMOS circuit structure including a plurality of column blocks each comprising a plurality of page buffer circuits, and a lower wiring structure and a memory structure sequentially stacked over the CMOS circuit structure. The memory structure overlaps a first circuit region of... Agent:

20150138863 - Interleaved write assist for hierarchical bitline sram architectures: An SRAM device includes a plurality of memory cells and a first metallization layer comprising a first pair of bitlines operable to couple to a first segment of the memory cells. The device also includes a second metallization layer comprising a second pair of bitlines operable to couple to a... Agent: Lsi Corporation

20150138864 - Memory architecture with alternating segments and multiple bitlines: Systems and methods presented herein provide a memory system which includes a memory cell array. The memory cell array includes first and second segments with corresponding local bitlines connected to one or more memory cells. The memory cell array also includes first and a second metallization layers. The second metallization... Agent: Lsi Corporation

20150138865 - Semiconductor memory device and driving method thereof: A semiconductor memory device in which capacitance of a capacitor is lower and integration degree is higher. A plurality of memory blocks is connected to one bit line BL_m. A memory block MB_n_m includes a sub bit line SBL_n_m, a write switch, and a plurality of memory cells. A sub... Agent:

20150138866 - Semiconductor memory: According to an embodiment, a semiconductor memory includes word lines, a plurality of sets of a pair of bit lines, memory cells, a writing/reading circuit, and a word line selection circuit. In a state where inverted data of program data has been written to the memory cells, a stress is... Agent: Kabushiki Kaisha Toshiba

20150138868 - Bitline circuits for embedded charge trap multi-time-programmable-read-only-memory: A bitline circuit for embedded Multi-Time-Read-Only-Memory including a plurality of NMOS memory cells coupled to a plurality of wordlines in each row, bitlines in each column, and a source-line. More specifically, the bitline circuit controls a charge trap behavior of the target NMOS memory array by mode-dependent bitline pull-down circuit,... Agent: International Business Machines Corporation

20150138869 - Non-volatile memory: A non-volatile memory includes a memory unit. The memory unit includes a first word line, a second word line, a control line, a logic circuit, a bit line, a first cell, and a second cell. The logic circuit has a first input terminal connected to the first word line, a... Agent: Faraday Technology Corporation

20150138870 - One-time programmable memory and system-on chip including one-time programmable memory: A one-time programmable (OTP) memory includes an OTP cell array including a plurality of OTP cells that each include a programming transistor configured to change irreversibly when programmed; a temperature compensation reference voltage generating unit configured to sense a temperature of the OTP cell memory and generate a reference voltage... Agent:

20150138867 - Wordline decoder circuits for embedded charge trap multi-time-programmable-read-only-memory: Wordline decoder circuits for an embedded Multi-Time-Read-Only-Memory that includes a plurality of NMOS memory cells coupled to a plurality of wordlines in each row. The wordline decoder circuits control the charge trap behavior of the target NMOS memory array by the mode-dependent wordline high voltage (VWLH) and wordline low voltage... Agent: International Business Machines Corporation

20150138874 - Array voltage regulating technique to enable data operations on large memory arrays with resistive memory elements: Embodiments of the invention relate generally to semiconductors and memory technology, and more particularly, to systems, integrated circuits, and methods to preserve states of memory elements in association with data operations using variable access signal magnitudes for other memory elements, such as implemented in third dimensional memory technology. In some... Agent:

20150138872 - Electronic device including a memory and method for fabricating the same: An electronic device includes a semiconductor memory unit. The semiconductor memory unit includes first lines extending along a first direction; second lines extending along a second direction that intersects with the first direction; a silicon-added metal oxide layer disposed in each intersection region of the first lines and the second... Agent: Sk Hynix Inc.

20150138871 - Memory structure and operation method therefor: Provided is an operation method applicable to a resistive memory cell including a transistor and a resistive memory element. The operation method includes: in a programming operation, generating a programming current flowing through the transistor and the resistive memory element so that a resistance state of the resistive memory element... Agent: Macronix International Co., Ltd.

20150138873 - Silicon based nanoscale crossbar memory: The present application describes a crossbar memory array. The memory array includes a first array of parallel nanowires of a first material and a second array of parallel nanowires of a second material. The first and the second array are oriented at an angle with each other. The array further... Agent:

20150138875 - Stabilization of resistive memory: The present disclosure includes apparatuses and methods including stabilization of resistive memory. A number of embodiments include applying a programming signal to a resistive memory cell, wherein the programming signal includes a first portion having a first polarity and a second portion having a second polarity, wherein the second polarity... Agent:

20150138876 - Global bitline write assist for sram architectures: An SRAM device includes a segmented memory cell array with a plurality of memory cells. Each segment of memory cells includes a bitline coupled to the memory cells in the segment. The SRAM device further includes a global bitline traversing the segmented memory cell array and communicatively coupled to the... Agent: Lsi Corporation

20150138878 - Electronic apparatus: This invention makes is possible to protect programs and shorten the activation time of an electronic apparatus even if a non-volatile memory such as an MRAM stores the programs including a boot program, and is used as a main memory. Upon power-on or receiving a reset signal, a program stored... Agent:

20150138877 - Nonvolatile logic gate device: A nonvolatile logic gate device is configured to include a resistive network of a memory structure in which at least three nonvolatile resistive elements are connected, a reference resistive network as a reference resistance providing a tolerance of the memory structure to a resistance value of the resistive network of... Agent: Nec Corporation

20150138879 - Read circuit for memory: Embodiments are directed to detecting a state of a memory element in a memory device, comprising: applying a pulse of a predetermined magnitude and duration to the memory element to induce a transition in the state of the memory element when a polarity of the pulse is opposite to the... Agent:

20150138880 - Memory cells having a plurality of resistance variable materials: Resistance variable memory cells having a plurality of resistance variable materials and methods of operating and forming the same are described herein. As an example, a resistance variable memory cell can include a plurality of resistance variable materials located between a plug material and an electrode material. The resistance variable... Agent:

20150138881 - Thyristor memory cell integrated circuit: A semiconductor memory device including an array of memory cells (MC) formed on a substrate each realized from a load element and thyristor that define a switchable current path whose state represents a volatile bit value stored by the MC. At least one word line corresponding to a respective row... Agent: The University Of Connecticut

20150138883 - Non-volatile semiconductor device: A non-volatile semiconductor device includes first and second selecting transistors; multiple memory cells that are stacked above the substrate; multiple word lines that are connected to control gates of the multiple memory cells; selecting gate lines that are each connected to a gate of one of the selecting transistors; a... Agent:

20150138882 - Nonvolatile memory devices, operating methods thereof and memory systems including the same: Nonvolatile memory device, operating methods thereof, and memory systems including the same. In the operating method, a ground select line of a first string connected to a bit line may be floated. An erase prohibition voltage may be applied to a ground select line of a second string connected to... Agent:

20150138884 - Memory systems including nonvolatile buffering and methods of operating the same: A nonvolatile memory system can include a nonvolatile memory device that can be configured to store data and a nonvolatile memory buffer circuit that can be configured to store data of a type that is predetermined to be flushed to the nonvolatile memory device in a sudden power off backup... Agent:

20150138885 - Non-volatile semiconductor storage device, and semiconductor device: A non-volatile semiconductor storage device includes a memory cell array divided into blocks, each of which is a erasable unit, the blocks, the blocks including a first block which is determined to be a bad block and a second block which is determined to be a partial bad block, a... Agent: Kabushiki Kaisha Toshiba

20150138888 - Memory system: According to one embodiment, a memory system includes a nonvolatile semiconductor memory device, a voltage generation unit and a control unit. The nonvolatile semiconductor memory device includes a memory cell array having a plurality of blocks each including a plurality of memory cells, and a voltage generation unit configured to... Agent: Kabushiki Kaisha Toshiba

20150138887 - Method and system for improving the radiation tolerance of floating gate memories: A method of improving radiation tolerance of floating gate memories is provided herein. Floating gate memories can include a floating gate transistor or a block of floating gate transistors. A floating gate transistor can include a semiconductor region, a source region, a drain region, a floating gate region, a tunnel... Agent:

20150138889 - Method of programming non-volatile memory device and apparatuses for performing the method: A non-volatile memory device is provided. The non-volatile memory device includes a cell string including a plurality of non-volatile memory cells; and an operation control block configured to supply a program voltage to a word line connected to a selected non-volatile memory cell among the plurality of non-volatile memory cells... Agent:

20150138886 - Non-volatile semiconductor storage device, and memory system: A non-volatile semiconductor storage device includes an memory cell array including first and second blocks, each of which includes a plurality of memory strings each having n (n: natural number) memory cells, and a optionally a peripheral circuit for controlling the memory cell array. In this non-volatile semiconductor storage device,... Agent: Kabushiki Kaisha Toshiba

20150138890 - Nonvolatile memory devices and driving methods thereof: Nonvolatile memory devices including memory cell arrays with a plurality of cell strings connected between a substrate and a plurality of bit lines and selected by selection lines, and a gating circuit configured to drive the selection lines in at least two directions.... Agent: Samsung Electronics Co., Ltd.

20150138891 - Embedded charge trap multi-time-programmable-read-only-memory for high performance logic technology: An embedded Multi-Time-Read-Only-Memory having a (MOSFET) cells' array having an initial threshold voltage (VT0) including the MOSFETs arranged in a row and column matrix, having gates in each row coupled to a wordline (WL) running in a first direction and sources in each one of the columns coupled to a... Agent: International Business Machiness Corporation

20150138892 - Single poly eeprom device: The present invention proposes a single poly EEPROM cell including a first control gate capacitor, a first tunnel gate capacitor, a first sense transistor, and a first selection transistor. In a single poly EEPROM cell according to the present invention, a Fowler Nordheim (FN) tunneling method is used in order... Agent: Changwon National University Industry Academy Cooperation Corps

20150138893 - High voltage switch, nonvolatile memory device comprising same, and related method of operation: A high voltage switch operates in response to a first drive voltage and a second drive voltage higher than the first drive voltage. The high voltage switch comprises a PMOS transistor transmitting the second drive voltage to an output terminal according to a voltage applied to its gate, a first... Agent:

20150138894 - Finding optimal read thresholds and related voltages for solid state memory: A read is performed using a first iteration of a read threshold voltage that is set to a default voltage to obtain a first characteristic. A second iteration of the read threshold voltage is generated using the default voltage and an offset. A read is performed using the second iteration... Agent:

20150138899 - Data storage device and operating method thereof: An operating method of a data storage device may include performing a first write operation on a first memory region, and performing a second write operation on a second memory region to store position information on the first write operation.... Agent: Sk Hynix Inc.

20150138900 - Data storage device and operating method thereof: An operating method of a data storage device includes performing a read operation on a nonvolatile memory device based on a read request and a logical address from a host device, determining whether one or more physical addresses, which correspond to one or more logical addresses continuous to the logical... Agent: Sk Hynix Inc.

20150138895 - High capacity memory system using standard controller component: The embodiments described herein describe technologies for using the memory modules in different modes of operation, such as in a standard multi-drop mode or as in a dynamic point-to-point (DPP) mode (also referred to herein as an enhanced mode). The memory modules can also be inserted in the sockets of... Agent:

20150138896 - Apparatuses and methods for performing logical operations using sensing circuitry: The present disclosure includes apparatuses and methods related to performing logical operations using sensing circuitry. An example apparatus comprises an array of memory cells and sensing circuitry comprising a primary latch coupled to a sense line of the array. The sensing circuitry can be configured to perform a first operation... Agent:

20150138898 - Shared tracking circuit: A system includes a first plurality of memory macros and a first tracking circuit associated with a memory macro of the first plurality of memory macros. Each memory macro of the first plurality of memory macros includes a corresponding global control circuit configured to receive a first reset signal. The... Agent:

20150138897 - Stack position determination in memory devices configured for stacked arrangements: Disclosed are various embodiments related to stacked memory devices, such as DRAMs, SRAMs, EEPROMs, and CAMs. For example, stack position identifiers (SPIDs) are assigned or otherwise determined, and are used by each memory device to make a number of adjustments. In one embodiment, a self-refresh rate of a DRAM is... Agent:

20150138901 - Memory circuitry using write assist voltage boost: Within a memory 2 comprising an array 4 of bit cells 6 write driver circuitry 14 uses a boosted write signal which is boosted to a lower than normal level during a write operation. Column select transistors 16 are driven by column select circuitry 12. The column select signal is... Agent: Arm Limited

20150138902 - Three-dimensional (3-d) write assist scheme for memory cells: An integrated circuit that includes an array of memory cells and an array of write logic cells. The integrated circuit also includes a write address decoder comprising a plurality of write outputs. The array of write logic cells is electrically connected to the plurality of write outputs. The array of... Agent: Taiwan Semiconductor Manufacturing Company, Ltd.

20150138903 - Writing to multi-port memories: A circuit includes a first memory cell and a data control circuit configured to provide first data and second data. The first memory cell has a first port and a second port. The first data is written from the first port to the first memory cell. The second data is... Agent:

20150138904 - Memory circuit and method of operating the memory circuit: A memory circuit includes a memory cell, a data line configured to be coupled with the memory cell, a node, a precharge circuit, a first transistor of a first type, and a second transistor of the first type. The precharge circuit is configured to charge the node toward a predetermined... Agent:

20150138905 - Low leakage state retention synchronizer: Described is an apparatus which comprises: a first memory unit having an input and an output, wherein the first memory unit operates on a first power supply which is operable to be turned off; a second memory unit having an input coupled to the output of the first memory unit,... Agent:

20150138906 - Systems and methods for non-volatile memory: A self powered memory system is disclosed. The system includes a volatile supply component, a battery component, a switch component, and a volatile memory component. The volatile supply component is configured to provide a time varying supply. The battery component is configured to generate a non-volatile supply. The switch component... Agent: Infineon Technologies Ag

  
05/14/2015 > 44 patent applications in 29 patent subcategories.

20150131355 - Associative memory circuit: An associative memory circuit including a first memristor, a second memristor, a fixed value resistor R, and an operational comparator. One terminal of the first memristor is a first input terminal of the associative memory circuit, and the other terminal of the first memristor is connected to a first input... Agent:

20150131356 - Data processing device and manufacturing method thereof: A method by which a defective memory cell can be efficiently excluded from a memory cell array is provided. In one embodiment, the memory cell array includes M word lines and (N+K) bit lines. K of the bit lines are spares (i.e., redundant bit lines). Programmable switches in a switch... Agent:

20150131357 - Semiconductor device: Provided is a semiconductor device capable of increasing the number of signals. A semiconductor device according to an embodiment of the invention includes memories; a controller that designates addresses of the memories; amounting board having lines formed thereon, the lines connecting the controller with the memories; and a first ball... Agent: Renesas Electronics Corporation

20150131359 - Current sense amplifiers, memory devices and methods: A current sense amplifier may include one or more clamping circuits coupled between differential output nodes of the amplifier. The clamping circuits may be enabled during at least a portion of the time that the sense amplifier is sensing the state of a memory cell coupled to a differential input... Agent:

20150131358 - Semiconductor device and programing method: This semiconductor device is provided with: a variable resistance first switch (103), which has a first terminal and a second terminal, and which has the resistance value thereof varied when an applied voltage exceeds a reference value; a variable resistance second switch (104), which has a third terminal and a... Agent:

20150131362 - Memory cells with rectifying device: Memory devices and methods described are shown that provide improvements, including improved cell isolation for operations such as read and write. Further, methods and devices for addressing and accessing cells are shown that provide a simple and efficient way to manage devices with multiple cells associated with each access transistor.... Agent:

20150131361 - Memory device: A device includes a storage region, and a resistive-read-access-memory-based (RRAM-based or ReRAM-based) non-volatile storage array is disclosed herein. The storage region includes a first storage array and a second storage array. The first storage array includes a plurality of first storage cells. The second storage array includes a plurality of... Agent: Taiwan Semiconductor Manufacturing Co., Ltd.

20150131363 - Nonvolatile semiconductor memory device including variable resistance element: According to one embodiment, a nonvolatile semiconductor memory device includes a memory cell array and a control circuit. The memory cell array include the memory cells each including a variable resistance element in which a reset current flowing in a reset operation is smaller than a set current flowing in... Agent: Kabushiki Kaisha Toshiba

20150131360 - Vertical 1t-1r memory cells, memory arrays and methods of forming the same: Vertical 1T-1R memory cells, memory arrays of vertical 1T-1R memory calls, and methods of forming such memory cells and memory arrays are described. The memory cells each include a vertical transistor and a resistivity-switching element coupled in series with and disposed above or below the vertical transistor. The vertical transistor... Agent: Sandisk 3d LLC

20150131364 - Negative bitline boost scheme for sram write-assist: A device includes a transistor switch coupled between a bit line voltage node and a ground node and a boost signal circuit coupled to a gate node of the transistor switch, where the boost signal circuit providing a boost signal responsive to a write enable signal. The device also includes... Agent: Taiwan Semiconductor Manufacturing Co., Ltd.

20150131367 - Semiconductor device and method for driving semiconductor device: A normally-off state of an OS transistor is maintained or an on-state current thereof is increased without additionally generating a positive potential or a negative potential. When data is written to a node connecting an OS transistor and a capacitor, a potential supplied to the other side of the capacitor... Agent:

20150131365 - Spsram wrapper: Among other things, one or more techniques or systems for facilitating access operations to a single port memory device are provided. Multiple access operations to a single port memory device, such as a 6 transistor bitcell array of an SPSRAM, are performed during a single clock period of a system... Agent: Taiwan Semiconductor Manufacturing Company Limited

20150131366 - Voltage controller: A voltage controller is provided that is connected to a voltage inducing circuit which is connected to a static random-access memory (SRAM) cell. The voltage controller comprises a voltage clamping circuit and a pull up circuit. The voltage clamping circuit comprises one or more transistors. The voltage clamping circuit is... Agent: Taiwan Semiconductor Manufacturing Company Limited

20150131368 - Implementing sense amplifier for sensing local write driver with bootstrap write assist for sram arrays: A method and circuit for implementing sense amplifiers for sensing local write driver with bootstrap write assist for Static Random Access Memory (SRAM) arrays, and a design structure on which the subject circuit resides are provided. The circuit includes a sense amplifier used in both read and write operations with... Agent: International Business Machines Corporation

20150131371 - Magnetic resistance structure, method of manufacturing the magnetic resistance structure, and electronic device including the magnetic resistance structure: Provided are a magnetic resistance structure, a method of manufacturing the magnetic resistance structure, and an electronic device including the magnetic resistance structure. The method of manufacturing the magnetic resistance structure includes forming a hexagonal boron nitride layer, forming a graphene layer on the boron nitride layer, forming a first... Agent: Sungkyunkwan University Foundation For Corporate Collaboration

20150131370 - Multi-level cells and method for using the same: The present invention is directed to a method for reading and writing an STT-MRAM multi-level cell (MLC), which includes a plurality of memory elements coupled in series. The method detects the resistance states of individual memory elements in an MLC by sequentially writing at least one of the plurality of... Agent: Avalanche Technology Inc.

20150131369 - Pulse programming techniques for voltage-controlled magnetoresistive tunnel junction (mtj): A method of programming a voltage-controlled magnetoresistive tunnel junction (MTJ) includes applying a programming voltage pulse (Vp), reading the voltage-controlled MTJ, and determining if the voltage-controlled MTJ is programmed to a desired state and if not, changing the Vp and repeating the applying and reading steps until the voltage-controlled MTJ... Agent: Avalanche Technology, Inc.

20150131373 - Incremental programming pulse optimization to reduce write errors: In a data storage system having multi-level memory cells, a counter tracks the number of program/erase cycles, anticipated read cycles, or anticipated length of data retention of a cell. When a threshold number of cycles is reached or length of retention or read frequency are anticipated, the cell is programmed... Agent: Lsi Corporation

20150131372 - Memory controller, memory device and method of operating: A memory controller has a bit line driver configured to supply a selected bit line voltage to a selected bit line and an unselected bit line voltage to an unselected bit line. The selected bit line is coupled to a selected memory cell, and the unselected bit line is coupled... Agent: Taiwan Semiconductor Manufacturing Company, Ltd.

20150131375 - Method of driving nonvolatile memory devices: A method of driving a nonvolatile memory device, includes; forward shifting threshold voltages of nonvolatile memory cells by executing a first program loop with respect to the nonvolatile memory cells, and thereafter, reverse shifting the threshold voltages of the nonvolatile memory cells, and again forward shifting the threshold voltages of... Agent:

20150131374 - Semiconductor device and operating method thereof: The present invention relates to a semiconductor device, including memory blocks suitable for storing data, peripheral circuits suitable for refreshing the memory blocks, and a control circuit suitable for controlling the peripheral circuits to change data stored in a first memory block among the memory blocks and refresh the first... Agent: Sk Hynix Inc.

20150131376 - Threshold estimation using bit flip counts and minimums: A bit flip count is determined for each bin in a plurality of bins, including by: (1) performing a first read on a group of solid state storage cells at a first threshold that corresponds to a lower bound for a given bin and (2) performing a second read on... Agent:

20150131377 - Method and device for protecting data of flash memory: A method of protecting data of a flash memory is provided. The method includes detecting primary power applied to the flash memory, and applying secondary power converted from the primary power to the flash memory. The primary power is compared to first and second values, and a writing-protection pin of... Agent: Samsung Electronics Co., Ltd.

20150131378 - Semiconductor memory device: A semiconductor memory device includes a string of memory cell transistors that are connected to each other in series. A selection transistor is connected between one end of the string of the memory cell transistors and one of a source line and a bit line. A line is selectively connected... Agent:

20150131380 - Adaptive initial program voltage for non-volatile memory: When programming a set of non-volatile storage elements using a multi-stage programming process, a series of programming pulses are used for each stage. The magnitude of the initial program pulse for the current stage being performed is dynamically set as a function of the number of program pulses used for... Agent: Sandisk Technologies Inc.

20150131379 - Bad block compensation for solid state storage devices: Technologies and implementations for reusing bad blocks in a solid state drive are generally disclosed.... Agent:

20150131381 - Three dimensional nonvolatile memory cell structure with upper body connection: A three-dimensional integrated circuit non-volatile memory array includes a memory array of vertical channel NAND flash strings connected between a substrate source line and upper layer connection lines which each include n-type drain regions and p-type body line contact regions alternately disposed on each side of undoped or lightly doped... Agent:

20150131383 - Non-volatile in-memory computing device: Disclosed is an in-memory computing device including a memory array with non-volatile memory cells arranged in rows and columns; a multiple row decoder to activate at least two cells in a column of the memory array at the same time to generate a parametric change in a bit line connected... Agent:

20150131382 - Semiconductor storage device and method of manufacturing the same: A semiconductor storage device including a memory cell array including a memory cell and a circuit element including first wirings and a selection element, the first wirings having a wiring width smaller than a resolution limit of an exposure apparatus. The first wirings extend in a first direction and are... Agent: Kabushiki Kaisha Toshiba

20150131384 - Semiconductor device: In a nonvolatile memory device (4) provided in a semiconductor device, when data is erased based on a band-to-band tunneling scheme, supply of a boosted voltage to a memory cell (MC) to be erased is ended when a condition that an output voltage (VUCP) of a charge pump circuit (52)... Agent: Renesas Electronics Corporation

20150131385 - Flash memory device having efficient refresh operation: Provided is a flash memory device capable of efficiently performing a refresh operation. The flash memory device includes a normal memory array including a plurality of normal memory cells arranged in a matrix of word lines and bit lines, wherein the plurality of normal memory cells are divided into a... Agent:

20150131386 - Data writing method, memory storage device and memory controlling circuit unit: A data writing method, a memory storage device, and a memory controlling circuit unit are provided. The writing method includes: grouping logical erasing units into a first region and an second region; determining if a first logical erasing unit which a host system intends to write belongs to the first... Agent: Phison Electronics Corp.

20150131387 - Logic embedded nonvolatile memory device: A logic embedded nonvolatile memory device is provided which includes a first erase gate line for erasing a plurality of first memory cells; a second erase gate line electrically separated from the first erase gate line and for erasing a plurality of second memory cells; a global erase gate line... Agent:

20150131388 - High capacity memory system using standard controller component: The embodiments described herein describe technologies for using the memory modules in different modes of operation, such as in a standard multi-drop mode or as in a dynamic point-to-point (DPP) mode (also referred to herein as an enhanced mode). The memory modules can also be inserted in the sockets of... Agent:

20150131389 - Semiconductor device, method for controlling the same, and semiconductor system: The semiconductor device includes a temperature sensor controlled so that temperature measurement is made once at each of a plurality of different reference temperatures at an interval of a preset number of times of refresh operations and a plurality of latch circuits holding the results of temperature measurement. A refresh... Agent: Ps4 Luxco S.a.r.l.

20150131390 - Apparatuses and methods for performing compare operations using sensing circuitry: The present disclosure includes apparatuses and methods related to performing compare and/or report operations using sensing circuitry. An example method can include charging an input/output (IO) line of a memory array to a voltage. The method can include determining whether data stored in the memory array matches a compare value.... Agent:

20150131391 - Tracking mechanism for writing to a memory cell: A circuit includes a write driver, a data circuit, a memory cell, a tracking write buffer, a tracking write driver, and a tracking cell. The circuit is configured that, during a write operation of the memory cell based on a clock signal, the write driver circuit is configured to generate... Agent:

20150131392 - Semiconductor integrated circuit and method of testing the semiconductor integrated circuit: A semiconductor integrated circuit includes a memory having bit cells; and a frequency detector outputting a switching signal to switch a test mode from first to second test modes. Further, the memory includes an internal clock generator generating an internal clock in synchronization with the external clock; a writing part... Agent:

20150131393 - Method of repairing a memory device and method of booting a system including the memory device: A method of repairing a memory device including a boot memory region, a normal memory region, and a redundant memory region, the redundant memory region including a plurality of repair memory units, includes repairing the boot memory region by performing at least one of excluding first fault memory units of... Agent:

20150131394 - Method and apparatus for read assist to compensate for weak bit: A memory assist apparatus includes a detection circuit and a compensation circuit. The detection circuit is configured to provide a detection signal indicating whether a bit line configured to provide read access to a data bit stored at a memory bit cell has a voltage below a predetermined threshold. The... Agent:

20150131395 - Method for triggering a delay-locked loop (dll) update operation or an impedance calibration operation in a dynamic random access memory device: A method for triggering an adjustment operation in a dynamic random access memory device, the method including receiving a refresh command, generating an execute signal, counting the execute signal to provide a count value, refreshing a memory array based on the count value and triggering the adjustment operation when the... Agent: Ps4 Luxco S.a.r.l.

20150131396 - Semiconductor memory device with switches for suspending power supply: A method of making a semiconductor integrated circuit includes forming switches configured to suspend, on a way-specific basis, power supply to ways allocated to one or more RAM macros.... Agent:

20150131397 - Memory system and assembling method of memory system: According to one embodiment, each memory chip included in a memory package includes a first storage unit that stores therein first information that is n-bit information and is a comparison target of a chip address, and is used for identifying its own memory chip, a second storage unit that stores... Agent: Kabushiki Kaisha Toshiba

20150131398 - Timing-drift calibration: The disclosed embodiments relate to components of a memory system that support timing-drift calibration. In specific embodiments, this memory system contains a memory device (or multiple devices) which includes a clock distribution circuit and an oscillator circuit which can generate a frequency, wherein a change in the frequency is indicative... Agent:

  
05/07/2015 > 40 patent applications in 24 patent subcategories.

20150124510 - Semiconductor device with more than one type of memory cell: A semiconductor chip comprises a word line configured to be driven by a word line driver. The semiconductor chip also comprises a plurality of bit lines. Each bit line of the plurality of bit lines is configured to transmit a signal to a respective bit line amplifier. The semiconductor device... Agent:

20150124511 - Semiconductor storage apparatus: A semiconductor memory device, including a plurality of word lines, a plurality of pairs of bit lines, a plurality of memory cells coupled to the plurality of word lines and the plurality of pairs of bit lines, a plurality of sense amplifiers each coupled between a corresponding pair of bit... Agent:

20150124512 - Memory cell and memory device: The memory cell of a memory device comprises a MOS capacitor having a n-type gate and a n-type well, a first switch to temporarily apply a breakthrough voltage across the n-type gate and the n-type well to generate a permanent conductive breakthrough structure between the n-type gate and the n-type... Agent:

20150124513 - Light incident angle controllable electronic device and manufacturing method thereof: Disclosed herein is a method of changing characteristics of an electronic device, including the steps of: applying light to an electronic device through a plurality of media having different refractive indexes from each other, the electrical characteristics of the electronic device being changed depending on the amount of incident light;... Agent:

20150124514 - Lifetime of ferroelectric devices: A method and apparatus for increasing the lifetime of ferroelectric devices is presented. The method includes applying a waveform to the input pulse to increase the rise or fall time of the pulse. The waveform may comprise a ramp, a step, or combinations of both. The waveform may be symmetrical... Agent: Purdue Research Foundation

20150124517 - Apparatus and methods for forming a memory cell using charge monitoring: Apparatus and methods of forming a memory cell are described. In one such method, a forming charge applied to a memory cell, such as a Resistive RAM (RRAM) memory cell, is monitored to determine the progress of the forming the cell. If the cell is consuming charge too slowly, a... Agent:

20150124519 - Circuitry including resistive random access memory storage cells and methods for forming same: A method of forming a circuitry includes providing a substrate comprising a plurality of die. Each die includes a plurality of resistive random access memory (RRAM) storage cells. The method further includes concurrently initializing substantially all of the RRAM storage cells on the same wafer. Initializing can include applying a... Agent: Freescale Semiconductor, Inc.

20150124515 - Nonvolatile memory device and method for testing nonvolatile memory device using variable resistance material: A method for testing a nonvolatile memory device includes: monitoring a first resistance dispersion and a second resistance dispersion of a nonvolatile memory device, determining a lower test bias level and an upper test bias level that are disposed on opposite sides of a reference bias level, calculating the number... Agent:

20150124518 - Nonvolatile semiconductor memory device: A nonvolatile semiconductor memory device comprises a cell array including a plurality of first lines, a plurality of second lines intersecting the plurality of first lines, and a plurality of memory cells arranged in matrix and connected at intersections of the first and second lines between both lines, each memory... Agent: Kabushiki Kaisha Toshiba

20150124520 - Resistive random access memory cell structure with reduced programming voltage: A cell of a resistive random access memory including (i) a resistive element and (ii) a switch. The resistive element includes (i) a first electrode, and (ii) a second electrode. The switch includes (i) a first terminal connected to a first contact, and (i) a second terminal connected to a... Agent:

20150124516 - Semiconductor memory device: A semiconductor memory device according to an embodiment includes a memory cell array including memory cells, the memory cells each configured having a current rectifier element and a variable resistance element connected in series therein. Each of the memory cells has formed on a side surface thereof: a first insulating... Agent: Kabushiki Kaisha Toshiba

20150124522 - Semiconductor device having hierarchical bit line structure: A semiconductor device comprises first and second global bit lines, a sense amplifier amplifying a voltage difference of the first and second global bit lines, first and second local bit lines corresponding to the first and second global bit lines, and first and second hierarchical switches controlling electrical connections between... Agent: Ps4 Luxco S.a.r.i.

20150124521 - Semiconductor devices including buried channels: A semiconductor device and a method of fabricating the same are provided. The semiconductor device includes an active region defined by a device isolation layer formed in a cell region, a transistor including a buried gate in the active region, a metal contact formed on the active region positioned at... Agent:

20150124523 - Initialization method of a perpendicular magnetic random access memory (mram) device: Methods using a sequence of externally generated magnetic fields to initialize the magnetization directions of each of the layers in perpendicular MTJ MRAM elements for data and reference bits when the required magnetization directions are anti-parallel are described. The coercivity of the fixed pinned and reference layers can be made... Agent:

20150124524 - Memory device with timing overlap mode: In some examples, a memory device is configured to receive a precharge command and an activate command. The memory device performs a first series of events related to the precharge command in response to receiving the precharge command and a second series of events related to the activate command in... Agent:

20150124526 - Nonvolatile memory device, system and programming method with dynamic verification mode selection: Nonvolatile memory devices, memory systems and related methods of operating nonvolatile memory devices are presented. During a programming operation, the nonvolatile memory device is capable of using bit line forcing, and is also capable of selecting a verification mode for use during a verification operation from a group of verification... Agent:

20150124525 - Semiconductor device and method for operating the same: A semiconductor device comprises a memory cell array comprising memory cells coupled to word lines and bit lines, a voltage generator suitable for generating a drive voltage to be applied to a selected word line, and a control logic suitable for detecting the number of pulses of a program voltage... Agent: Sk Hynix Inc.

20150124527 - Detecting programmed word lines based on nand string current: A number (Nwl) of programmed word lines in a block of NAND strings is determined by measuring a reference combined current (Iref) in the block when all of the memory cells are in a conductive state. Subsequently, to determine if a word line is a programmed word line, an additional... Agent: Sandisk Technologies Inc.

20150124528 - Semiconductor memory device: A semiconductor memory device includes a memory string having first and second selective transistors, each of which includes a charge storage layer and a control gate, a back gate transistor which includes a charge storage layer and a control gate, and memory cell transistors connected to each other and to... Agent:

20150124529 - Semiconductor device, method for operating the same, and semiconductor system including the same: A semiconductor device includes a page buffer configured to read data out of a memory cell array in response to a bias enable signal, and a control logic configured to generate the bias enable signal and a bias precharge signal that are used to control the memory cell array. The... Agent: Sk Hynix Inc.

20150124530 - Memory string and semiconductor device including the same: A memory string includes a pass transistor, first memory cells connected in series to a drain terminal of the pass transistor, and first to kth memory cell groups connected in parallel to a source terminal of the pass transistor and each including a plurality of second memory cells connected in... Agent: Sk Hynix Inc.

20150124532 - Dummy memory erase or program method protected against detection: The invention relates to a method of programming or erasing memory cells of a nonvolatile memory, including a first erase or program cycle comprising i) applying at least one erase or program pulse to first memory cells, ii) determining the state, erased or programmed, of the memory cells, and repeating... Agent:

20150124531 - Ias voltage generator for reference cell and bias voltage providing method therefor: A bias voltage generator and generating method for a reference cell are provided. The bias voltage generator includes a data read detector, a cut-off signal generator and an output stage circuit. The data read detector generates a detection signal according to transition points of a sense amplifier enable signal and... Agent: Winbond Electronics Corp.

20150124534 - Semiconductor memory device capable of shortening erase time: In a memory cell array, a plurality of memory cells connected to a plurality of word lines and a plurality of bit lines are arranged in a matrix. A control circuit controls the potentials of said plurality of word lines and said plurality of bit lines. In an erase operation,... Agent: Kabushiki Kaisha Toshiba

20150124533 - Solid state storage device and sensing voltage setting method thereof: A solid state storage device and sensing voltage setting method thereof are provided, and the method includes following steps. A predetermined read voltage of the memory cells is adjusted to obtain a plurality of detection read voltages. The predetermined read voltage and the detection read voltages are respectively applied to... Agent: Lite-on It Corporation

20150124536 - Semiconductor devices: The semiconductor device includes a comparator and a data output unit. The comparator compares a phase of a first pulse signal generated in a first memory region with a phase of a second pulse signal generated in a second memory region and responsively generates a detection signal. The data output... Agent: Sk Hynix Inc.

20150124535 - Semiconductor integrated circuit: A semiconductor integrated circuit may include: a memory block partitioned into a first region and a second region; a data latch unit configured to latch data outputted from the memory block in response to a control signal; and a control circuit configured to generate a source signal separated into an... Agent: Sk Hynix Inc.

20150124537 - Semiconductor device: A semiconductor device of an embodiment is provided with a memory, a register configured to store a first data group including test data and read/write instruction data to the memory, a first inversion portion having an inverting function of a value of the test data outputted from the register, a... Agent: Kabushiki Kaisha Toshiba

20150124539 - Semiconductor device: The problem was that the high-impedance state of the difference between signals DQS and DQSB cannot be prevented from being brought in. With this invention, a first comparator circuit outputs a signal DQSIN representing the difference between DQS and DQSB after the coupling of input terminals to a terminal potential... Agent:

20150124538 - Semiconductor memory device: A semiconductor memory device includes a plurality of banks; a plurality of word lines; an advanced refresh operation mode where two or more word lines are selected in parallel in each bank; a pulse generation unit suitable for generating a single bank refresh pulse that toggles for a given time... Agent: Sk Hynix Inc.

20150124540 - Semiconductor integrated circuit: A system including a circuit integrated with a semiconductor is provided. The system includes a first data line, a second data line, and a first sense amp configured to sense and amplify data of the first data line. The first sense amp is also configured to transfer the amplified data... Agent: Sk Hynix Inc.

20150124541 - Memory card and sd card: According to one embodiment, there are provided a memory which is provided on a circuit board, a controller which is provided on the circuit board and controls the memory, and a signal line which is formed on the circuit board and configured to perform data transmission between the controller and... Agent: Kabushiki Kaisha Toshiba

20150124542 - Semiconductor memory device, semiconductor memory module and operation methods thereof: An operation method of a semiconductor memory device including a fuse array for storing one or more repair addresses includes latching additionally a repair address having an address value, which is not stored in the fuse array in response to an active command signal during a repair operation mode, receiving... Agent: Sk Hynix Inc.

20150124543 - Semiconductor devices: Semiconductor devices are provided. The semiconductor device includes a first pre-charge element and a second pre-charge element. The first pre-charge element receives a first pre-charge signal to pre-charge a first bit line to have a first pre-charge voltage signal. The second pre-charge element receives a second pre-charge signal to pre-charge... Agent: Sk Hynix Inc.

20150124545 - Semiconductor device and method for driving the same: A semiconductor device includes a periodic signal generating circuit for generating a periodic signal having a set period regardless of changes in temperature in response to a first trimming signal as a default value and controlling the set period of the periodic signal based on the temperature in response to... Agent: Sk Hynix Inc.

20150124544 - Semiconductor devices and semiconductor systems including the same: A semiconductor system includes a controller and a semiconductor device. The controller outputs offset signals whose level combination is controlled according to temperature code signals including information on an internal temperature. The semiconductor device generates the temperature code signals according to a level combination of the offset signals. Further, the... Agent: Sk Hynix Inc.

20150124547 - Semiconductor device: An object is to increase the retention characteristics of a memory device formed using a wide bandgap semiconductor. A bit line controlling transistor is inserted in a bit line in series. The minimum potential of a gate of the transistor is set to a sufficiently negative value. The gate of... Agent:

20150124548 - Switching circuit: A first transistor is turned on based on a first control signal provided to a first terminal of the first transistor. A second control signal is generated by a logic device based on a first input signal and a second input signal. The first input signal is controlled by a... Agent:

20150124546 - Voltage regulator and apparatus for controlling bias current: A voltage regulator includes: a comparator configured to compare a feedback voltage with a reference voltage to output an enable signal and operate based on a bias current; a pass transistor turned on according to the enable signal and configured to output an external power voltage as an output voltage;... Agent: Sk Hynix Inc.

20150124549 - Semiconductor devices: The semiconductor device includes a pulse width comparator suitable for generating an internal pulse signal having the same pulse width as an output pulse signal whose pulse width is controlled by first and second control signals during a predetermined period and suitable for generating first and second digital signals and... Agent: Sk Hynix Inc.

  
04/30/2015 > 56 patent applications in 34 patent subcategories.

20150117078 - Semiconductor device: A semiconductor device includes a plurality of main amplifiers provided between memory cell arrays. One of the main amplifiers is disposed closer to one of the memory cell arrays than to the other of memory cell arrays, and the other of the main amplifiers is disposed closer to the other... Agent:

20150117079 - Sub word line driver and semiconductor integrated circuit device: A sub word line driver and a semiconductor integrated circuit device having the same are provided. The semiconductor integrated circuit device includes adjacent four sub word line drivers configured to drive four sub word lines in response to signals of four main word lines, wherein first and second sub word... Agent:

20150117080 - Multi-chip package and memory system: A multi-chip package includes a first group of memory chips that includes a first memory chip and a second memory chip, a second group of memory chips that includes at least one memory chip, a first internal wiring system that couples the first memory chip and the second memory chip... Agent:

20150117081 - Memory cell with decoupled read/write path: A memory cell with a decoupled read/write path, the memory cell includes a switch comprising a gate, a first terminal and a second terminal, a resistive switching device connected to the gate of the switch, and a conductive path between the gate of the switch and the second terminal.... Agent:

20150117082 - Memory device: A memory cell includes a first transistor controlling writing of the first date by being in an on state, and holding of the first data by being in an off state, a second transistor in which a potential of one of a source and a drain is a potential of... Agent:

20150117083 - Memory device: A memory device including: a memory cell array including normal memory cells and spare memory cells arranged in rows and columns including normal columns including the normal memory cells and at least one spare column including spare memory cells, a segment match determining circuit configured to compare a segment address... Agent:

20150117084 - Multi-bit ferroelectric memory device and methods of forming the same: Multi-bit ferroelectric memory devices and methods of forming the same are provided. One example method of forming a multi-bit ferroelectric memory device can include forming a first ferroelectric material on a first side of a via, removing a material to expose a second side of the via, and forming second... Agent: Micron Technology, Inc.

20150117085 - Semiconductor memory device: According to one embodiment, a semiconductor memory device includes a memory cell and a control circuit. The memory cell is such that a ferroelectric film is provided as a gate dielectric film. When data is stored in the memory cell, the control circuit applies a first voltage to the gate... Agent: Kabushiki Kaisha Toshiba

20150117088 - Non-volatile memory device: According to one embodiment, a non-volatile memory device includes: first memory cell regions including first wirings extending in a first direction, second wirings extending in a second direction crossing the first direction, and first memory cells provided between the first wirings and the second wirings and being capable of changing... Agent: Kabushiki Kaisha Toshiba

20150117087 - Self-terminating write for a memory cell: A programmable impedance based memory device includes a programmable impedance element, read circuitry configured to determine a resistance of the programmable impedance element during a write operation; and, write circuitry configured to change the resistance of the programmable impedance element as part of performing the write operation, wherein the write... Agent: Honeywell International Inc.

20150117089 - Semiconductor memory device and memory system: A semiconductor memory device according to an embodiment includes a memory cell array and a control circuit. The memory cell array includes first lines and second lines intersecting each other, a third line commonly connecting to the first lines, memory cells disposed at intersections of the first lines and the... Agent: Kabushiki Kaisha Toshiba

20150117090 - Three-terminal synapse device and method of operating the same: A three-terminal synapse device may include a drain layer formed on a substrate, a gate layer formed on the drain layer, a source layer vertically stacked on the substrate and facing the drain layer and the gate layer. First and second vertical insulating layers may be formed between the source... Agent:

20150117086 - Write pulse width scheme in a resistive memory: A resistive memory array includes a controller, a test reset driver coupled to the controller, a test write driver also coupled to the controller, and a test read sense amplifier also coupled to the controller. The resistive memory array also includes a set of test resistive memory elements representing a... Agent: Qualcomm Incorporated

20150117093 - Method for driving semiconductor device: A semiconductor device includes SRAM that stores data in an inverter loop including a CMOS inverter, transistors electrically connected to an input terminal or an output terminal of the CMOS inverter, and capacitors electrically connected to the corresponding transistors. The semiconductor device is configured to hold potentials corresponding to data... Agent:

20150117092 - Multi-channel physical interfaces and methods for static random access memory devices: An integrated circuit (IC) device can include a static random access memory (SRAM) section comprising a plurality of memory banks; and an interface comprising physical connections for more than eight memory channels, the connections for each memory channel including an address section including connections for SRAM control inputs and a... Agent:

20150117091 - Multi-channel, multi-bank memory with wide data input/output: An integrated circuit (IC) can include M memory banks, where M is greater than 2, and each memory bank is separately accessible according to a received address value; N channels, where N is greater than 2, and each channel includes its own a data connections, address connections, and control input... Agent: Cypress Semiconductor Corporation

20150117094 - Memory device and a method of operating the same: A semiconductor memory device comprises an array of memory cells arranged in rows and columns, control lines coupled to the rows of memory cells for accessing the memory cells, conductive lines coupled to the rows of memory cells for powering the memory cells, and a control circuit configured to maintain... Agent: Taiwan Seminconductor Manufacturing Company Ltd.

20150117095 - Low resistance bitline and sourceline apparatus for improving read and write operations of a nonvolatile memory: Described is an apparatus for improving read and write margins. The apparatus comprises: a sourceline; a first bitline; a column of resistive memory cells, each resistive memory cell of the column coupled at one end to the sourceline and coupled to the first bitline at another end; and a second... Agent:

20150117096 - Write operation method and device for phase change memory: A write operation method for a phase change memory (PCM) is disclosed. The method includes when a PCM performs a write operation, generating a corresponding voltage pulse signal according to to-be-written data, and applying the voltage pulse signal to a phase change material included in a phase change storage unit... Agent:

20150117097 - Systems and methods for sub-zero threshold characterization in a memory cell: Systems and method relating generally to data processing, and more particularly to systems and methods for characterizing a solid state memory.... Agent: Lsi Corporation

20150117098 - Power drop protection for a data storage device: A data storage device includes a non-volatile memory. A method includes programming a first page at a word line of the non-volatile memory. While programming a second page at the word line, first storage elements of the word line are selectively programmed in response to a power drop at the... Agent: Sandisk Technologies Inc.

20150117099 - Selection of data for redundancy calculation by likely error rate: Layers in a multi-layer memory array are categorized according to likely error rates as predicted from their memory hole diameters. Data to be stored along a word line in a high risk layer is subject to a redundancy operation (e.g. XOR) with data to be stored along a word line... Agent: Sandisk Technologies Inc.

20150117100 - Storage device and related programming method: A method of programming a storage device comprises determining whether at least one open page exists in a memory block of a nonvolatile memory device, and as a consequence of determining that at least one open page exists in the memory block, closing the at least one open page through... Agent:

20150117101 - Split page 3d memory array: A semiconductor device includes active strips. Active strip stack selection structures electrically couple to the active strip stacks at positions between the first and second ends, and select particular ones of the active strip stacks for operations. In one embodiment, different pads coupled to opposite pads have a higher voltage,... Agent: Macronix International Co., Ltd.

20150117102 - Nonvolatile semiconductor memory apparatus: According to one embodiment, a nonvolatile semiconductor memory apparatus includes a memory cell array, a row decoder, a controller. The memory cell array includes a plurality of memory strings. The memory strings include a first select transistor and a second select transistor, and are connected to each of a plurality... Agent: Kabushiki Kaisha Toshiba

20150117103 - Split block decoder for a nonvolatile memory device: A non-volatile memory device having a memory array organized into a plurality of memory blocks, having either planar memory cells or stacks of cells. Row decoding circuitry of the memory device is configured to select a group of the plurality of memory blocks in response to a first row address,... Agent:

20150117106 - Flash memory counter: A method of updating a counter in a flash memory includes a first phase where a set of values capable of being taken by the counter are programmed in at least one page of the flash memory. A second phase of updating the counter programs a state zero in the... Agent:

20150117105 - Nonvolatile memory device and method detecting defective word line: The inventive concept relates to a nonvolatile memory device and a method of detecting a defective word line. The method includes executing a defective word line detection operation using a program/erase voltage applied to a selected word line, wherein the defective word line detection operation determines whether or not the... Agent:

20150117107 - Read operation for a non-volatile memory: Apparatuses, systems, and methods are disclosed for a read operation for a non-volatile memory. A method includes determining whether one or more non-volatile storage cells satisfy a predefined condition. A method includes preparing the one or more non-volatile storage cells for use prior to satisfying a read request from a... Agent:

20150117104 - Semiconductor memory device: A semiconductor memory device for high speed operation, and for flexible data reading and programming is disclosed. The flash memory of the present disclosure includes: a page buffer/sensor circuit including a volatile memory element that may maintain data with a size corresponding to a page of a memory array; a... Agent:

20150117110 - Connecting storage gate memory: Technologies are generally related to a connecting storage gate memory device, system, and method of manufacture.... Agent:

20150117109 - Hot-carrier injection programmable memory and method of programming such a memory: The present disclosure relates to a memory comprising at least one word line comprising a row of split gate memory cells each comprising a selection transistor section comprising a selection gate and a floating-gate transistor section comprising a floating gate and a control gate. According to the present disclosure, the... Agent:

20150117108 - Semiconductor device and methods of manufacturing and operating the same: A semiconductor device includes a memory cell array including a vertical channel layer, two or more selection transistors, and a plurality of memory cells formed along the vertical channel; a peripheral circuit suitable for programming the two or more selection transistors and the memory cells; and a control circuit suitable... Agent: Sk Hynix Inc.

20150117112 - Adaptive erase methods for non-volatile memory: A method includes an erase of a plurality of blocks of memory cells in which the memory cells within a block are simultaneously erased. The erase of each block of the plurality of blocks is performed using an erase pulse applied multiple times. The erase pulse is applied to the... Agent:

20150117111 - Methods for programming a memory device and memory devices: Methods for programming memory cells and memory devices are disclosed. One such method for programming includes performing a program verify operation of a group of memory cells. A number of potential CS2 situations are detected. If the number of detected potential CS2 situations is greater than a threshold, programming compensation... Agent: Micron Technology, Inc.

20150117113 - Programming scheme for improved voltage distribution in solid-state memory: Systems and methods are disclosed for reducing programming interference in solid-state memory using a program suspend command. A data storage system includes a non-volatile memory array including a plurality of non-volatile memory devices and a controller configured to partially program a first cell coupled to a first word line. When... Agent: Western Digital Technologies, Inc.

20150117114 - Word line coupling for deep program-verify, erase-verify and read: In a non-volatile storage system, a reduced voltage is provided on a selected word line during a sensing operation, using down coupling from one or more adjacent word lines. Voltages of one or more adjacent word lines of a selected word line are driven down while a voltage of the... Agent: Sandisk Technologies Inc.

20150117115 - Discharge circuit: A discharge circuit includes a first circuit connected between a high-voltage terminal and a connection node, wherein first circuit includes a depletion high voltage NMOS transistor of which a drain connected to the high-voltage terminal, a source connected to the connection node, and a gate receiving a reference voltage, and... Agent: Sk Hynix Inc.

20150117117 - Memory cell comprising non-self-aligned horizontal and vertical control gates: The present disclosure relates to a memory cell comprising a vertical selection gate extending in a trench made in a substrate, a floating gate extending above the substrate, and a horizontal control gate extending above the floating gate, wherein the floating gate also extends above a portion of the vertical... Agent:

20150117116 - Method for writing into and reading a multi-levels eeprom and corresponding memory device: During a phase of programming the cell, a first voltage is applied to the source region and a second voltage, higher than the first voltage, is applied to the drain region until the cell is put into conduction. The numerical value of the item of data to be written is... Agent:

20150117118 - Non-volatile memory devices, operating methods thereof and memory systems including the same: Nonvolatile memory devices, operating methods thereof, and memory systems including the same. A nonvolatile memory device may include a memory cell array and a word line driver. The memory cell array may include a plurality of memory cells. The word line driver may be configured to apply word line voltages... Agent:

20150117123 - Semiconductor memory device and method of operating the same: A semiconductor memory device includes a memory cell array having memory cells coupled to a plurality of word lines and a peripheral circuit group configured to supply a pass voltage to unselected word lines among the plurality of word lines, wherein the peripheral circuit group stepwise raises the pass voltage... Agent: Sk Hynix Inc.

20150117120 - Gated-feedback sense amplifier for single-ended local bit-line memories: A single-ended input sense amplifier uses a pass device to couple the input local bit-line to a global bit-line evaluation node. The sense amplifier also includes a pair of cross-coupled inverters, a first inverter of which has an input that coupled directly to the global bit-line evaluation node. The output... Agent: International Business Machines Corporation

20150117119 - Memory circuitry with write assist: Memory circuitry is provided with write assist circuitry for generating a lower power supply voltage during write operations. The write assist circuitry includes a plurality of series connected switches including a header switch and a footer switch. Header bias circuitry generates a header bias voltage and footer bias circuitry generates... Agent: Arm Limited

20150117121 - Semiconductor memory apparatus and data storage and power consumption: A semiconductor memory apparatus includes a write driver configured to transfer input data to a data storage region. The semiconductor memory apparatus may also include a sense amplifier configured to sense and amplify the data stored in the data storage region and output output data. Further, the semiconductor memory apparatus... Agent: Sk Hynix Inc.

20150117122 - Semiconductor memory device calibrating termination resistance and termination resistance calibration method thereof: Provided is a semiconductor memory device calibrating a termination resistance, the semiconductor memory device comprising self-adjustment logic configured to determine whether a value of an upper bit string of a calibration code generated in response to a calibration start signal is equal to or greater than an upper critical value... Agent:

20150117124 - Data line control for sense amplifiers: Some embodiments include apparatuses and methods having a first data line, a second data line, a first transistor, a sense amplifier, and a circuit. The first transistor can operate to couple the first data line to a first node during a first stage of an operation of obtaining information from... Agent: Micron Technology, Inc.

20150117125 - Semiconductor memory device, memory system including the same and operating method thereof: Provided are a semiconductor memory device, a memory system including the same, and an operating method thereof. The semiconductor memory device includes a memory cell array including a plurality of memory cells, a peripheral circuit suitable for reading least significant bit data and most significant bit data of neighboring memory... Agent: Sk Hynix Inc.

20150117126 - Pulse width modulation circuit: In order to reduce occurrence of a fetching error of a digital signal, caused by a power-source noise, there is provided a semiconductor device provided with a switching circuit for executing a switching operation according to a pulse control signal and a digital signal hold circuit for fetching a digital... Agent:

20150117127 - Random access memory and method of adjusting read timing thereof: A method of adjusting read timing of a random access memory. The method includes providing a Column Address Strobe (CAS) value for defining an CAS latency (CL) of the random access memory; generating a shift margin according to the CAS latency and a reference latency; generating a read command for... Agent: Nanya Technology Cop.

20150117128 - Optoelectronic device, in particular memory device: A memory device may include an access transistor, and a memory cell configured to store an item of information. The memory cell may include first and second electrodes configured to have different optoelectronic states corresponding respectively to two values of the item of information, and to switch between the different... Agent:

20150117129 - Semiconductor memory device, memory system including the same and operating method thereof: A semiconductor memory device includes a memory cell array including a plurality of memory cells, a peripheral circuit suitable for generating program and erase voltages and applying the program and erase voltages to the plurality of memory cells when program and erase operations are performed on the plurality of memory... Agent: Sk Hynix Inc.

20150117130 - Programming multiple serial input devices: Serial input devices (e.g., pin electronics modules) are coupled to an interface via data lines, clock lines, and select lines. A first subset and a second subset of the devices are each arrayed in columns, rows, and layers. Each data line is coupled to a respective row in the first... Agent:

20150117131 - Memory devices: A method and a system for memory cell programming and erasing with refreshing operation are disclosed. The system includes a selecting module, a processing module and a refresh module. In the method, at first, a target memory cell from a plurality of memory cells in a memory device is selected.... Agent: Taiwan Semiconductor Manufacturing Co., Ltd.

20150117132 - Semiconductor memory device and data storage device including the same: A semiconductor memory device includes a memory cell array, a voltage generator suitable for generating voltages used for controlling the memory cell array in response to a power-saving signal, and a control logic suitable for providing a power-saving signal to the voltage generator, based on a chip select signal. The... Agent: Sk Hynix Inc.

20150117133 - Semiconductor memory device capable of preventing degradation of memory cells and method for erasing the same: A semiconductor memory device according to an embodiment of the present invention may include a memory cell array having a plurality of memory cells, a pass transistor group having normal pass transistors coupled between global word lines and local word lines to which the plurality of memory cells are coupled,... Agent: Sk Hynix Inc.

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