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Static information storage and retrievalBelow are recently published patent applications awaiting approval from the USPTO. Recent week's RSS XML file available below.
Listing for abstract view: USPTO application #, Title, Abstract excerpt,Patent Agent. Listing format for list view: USPTO National Class full category number, title of the patent application. 02/05/2015 > 44 patent applications in 26 patent subcategories.
20150036406 - Data processing device: A microcomputer provided on a rectangular semiconductor board has memory interface circuits. The memory interface circuits are separately disposed in such positions as to extend along the peripheries of the semiconductor board on both sides from one corner as a reference position. In this case, limitations to size reduction imposed... Agent:
20150036405 - Memory devices: Some embodiments include memory devices having a wordline, a bitline, a memory element selectively configurable in one of three or more different resistive states, and a diode configured to allow a current to flow from the wordline through the memory element to the bitline responsive to a voltage being applied... Agent:
20150036408 - Memory system and method using stacked memory device dice: A method and apparatus for organizing memory for a computer system including a plurality of memory devices, connected to a logic device, particularly a memory system having a plurality of stacked memory dice connected to a logic die, with the logic device having capability to analyze and compensate for differing... Agent:
20150036407 - Non-volatile memory device: According to one embodiment, a non-volatile memory device includes a memory cell array and a coil provided closely to the memory cell array. The memory cell array includes memory cells provided above an underlying layer, and a first interconnection. The memory cells are aligned in a first direction perpendicular to... Agent: Kabushiki Kaisha Toshiba
20150036409 - System and method to provide a reference cell using magnetic tunnel junction cells: An apparatus includes a group of data cells and a reference cell coupled to the group of data cells. The reference cell includes four magnetic tunnel junction (MTJ) cells.... Agent: Qualcomm Incorporated
20150036410 - Semiconductor storage device: A memory includes a first and second cell storing first data and second or reference-data. A first and second bit-lines connected to the first and second cells respectively correspond to a first and second sense-nodes. A first transfer-gate is inserted/connected between the first bit-line and the first sense-node. A second... Agent: Kabushiki Kaisha Toshiba
20150036411 - Semiconductor memory device: A semiconductor memory device includes a nonvolatile device array including write-once nonvolatile devices arranged in rows and columns, row select lines, a row control circuit connected to the row select lines, column select lines, a column control circuit connected to the column select lines, a flip-flop circuit provided at least... Agent:
20150036415 - Non-volatile memory cell: The invention concerns a memory device comprising: a memory cell having at least one resistive memory element (202) with first, second and third terminals (A, B, C), a resistance between the third terminal (C) and one or both of the first and second terminals being programmable to have one of... Agent:
20150036412 - Nonvolatile memory device and semiconductor system using the same: Provided is a nonvolatile memory device including a resistive memory cell and semiconductor system using the same that is capable of setting the reference resistance value using resistance values of a plurality of memory cells. The nonvolatile memory device comprises one or more column lines, two or more row lines,... Agent: Sk Hynix Inc.
20150036413 - Resistive memory element based on oxygen-doped amorphous carbon: The present invention is notably directed to a resistive memory element comprising a resistively switchable material coupled to two conductive electrodes, wherein the resistively switchable material is an amorphous compound comprising carbon and oxygen. Moreover, the carbon and oxygen stoichiometric ratio can be within a range of 1:0.30 to 1:0.80.... Agent:
20150036414 - Shared-gate vertical-tft for vertical bit line array: A non-volatile storage device comprises: a substrate; a monolithic three dimensional array of memory cells; word lines connected to the memory cells; global bit lines; vertical bit lines connected to the memory cells; and a plurality of double gated vertically oriented select devices. The double gated vertically oriented select devices... Agent:
20150036416 - Multi-channel memory device with independent channel power supply structure and method of controlling power net: A multi-channel memory device includes a first channel memory and a second channel memory that are independently accessible within a same chip and that respectively include first and second power channel connection lines; a decoupling unit that can operationally connect or separate the first and second power channel connection lines... Agent:
20150036418 - Circuits for voltage or current biasing static random access memory (sram) bitcells during sram reset operations, and related systems and methods: Circuits for voltage or current biasing static random access memory (SRAM) bitcells during SRAM reset operations are disclosed. Related systems and methods are also disclosed. To reset a plurality of SRAM bitcells in a single reset operation, a biasing circuit is provided and coupled to the plurality of SRAM bitcells.... Agent: Qualcomm Incorporated
20150036419 - Semiconductor apparatus and data reading method: A semiconductor apparatus includes a memory array that is disposed such that bit line pairs are arranged in a plurality of columns in a column direction and the bit line pairs are connected to one data latch circuit, in which a plurality of memory cells are connected to the bit... Agent:
20150036420 - Semiconductor storage device: Provided is a semiconductor storage device including first and second load transistors, first and second drive transistors, first and second transfer transistors, and first and second cell node lines each serving as a storage node. A portion where a cell node line and a bit line corresponding to the cell... Agent:
20150036417 - Sram read buffer with reduced sensing delay and improved sensing margin: A device includes a static random access memory (SRAM) cell and a read buffer coupled to an output of the SRAM cell. The read buffer includes an inverter and a switch. An input of the inverter is responsive to the output of the SRAM cell. A control terminal of the... Agent: Industry-academic Cooperation Foundation, Yonsei University
20150036421 - Current sense amplifying circuit in semiconductor memory device: Disclosed is a current sense amplifier suitable for a nonvolatile memory device such as a magnetic random access memory. In the current sense amplifier, a reference memory cell for sensing is implemented by a memory cell equal to a normal memory cell without fabricating different reference memory cells. The current... Agent:
20150036422 - Magnetic storage element, magnetic storage device, magnetic memory, and method of driving magnetic storage element: A magnetic storage element according to an embodiment includes: a magnetic nanowire having a cross-sectional area varying in a first direction, the magnetic nanowire having at least two positions where the cross-sectional area is minimal; first and second electrode groups having the magnetic nanowire interposed in between, the magnetic nanowire... Agent: Kabushiki Kaisha Toshiba
20150036423 - Semiconductor device: An array configuration capable of supplying a necessary and sufficient current in a small area is achieved and a reference cell configuration suitable to temperature characteristics of a TMR element is achieved. In a memory using inversion of spin transfer switching, a plurality of program drivers are arranged separately along... Agent:
20150036424 - Semiconductor memory device, memory system and access method to semiconductor memory device: A semiconductor memory device includes a block array having an m number of memory blocks in a row direction and an n number of memory blocks in a column direction (m being an integer of 2 or more and n being an integer of 1 or more), a page selection... Agent:
20150036425 - Memory cell and memory cell array having an electrically floating body transistor, and methods of operating same: Techniques are disclosed for writing, programming, holding, maintaining, sampling, sensing, reading and/or determining a data state of a memory cell of a memory cell array, such as a memory cell array having a plurality of memory cells each comprising an electrically floating body transistor. In one aspect, the techniques are... Agent: Micron Technology, Inc.
20150036427 - Incrementally programmable non-volatile memory: An array of programmable non-volatile devices, such as a nominal OTP cell, is adapted such that a Vt representing a particular binary logic state can be changed over time. This allows for re-programming and emulating a few times or multi-time programmable device.... Agent:
20150036428 - Method of operating incrementally programmable non-volatile memory: An array of programmable non-volatile devices, such as a nominal OTP cell, is operated such that a Vt representing a particular binary logic state is changed over time. This allows for re-programming and emulating a few times or multi-time programmable device.... Agent:
20150036426 - Nonvolatile memory device and method of program verifying the same: A program method of a three-dimensional nonvolatile memory device is provided which includes executing at least one program loop including an operation of programming selected memory cells of a selected string turned on by a selected string selection transistor and an operation of verifying whether programming of the memory cells... Agent:
20150036429 - Semiconductor memory device: A semiconductor memory device includes a memory block including memory strings formed between bit lines and a source line, wherein the bit lines and the source line are formed on a substrate, each of the memory strings includes a superordinate cell string connected between the bit line and pipe transistors... Agent: Sk Hynix Inc.
20150036430 - Semiconductor memory device: A controller controls a memory including first and second strings. The first and second strings configure first and second string groups, respectively. In each string group, a set of memory cell transistors each from each string configures a unit. The controller is configured to: sequentially write, in the first string... Agent: Kabushiki Kaisha Toshiba
20150036432 - Method and apparatus for improving data integrity using threshold voltage recalibration: A non-volatile (“NV”) memory device is able to enhance data integrity using threshold voltage (“Vt”) recalibration based on a selected scheme. Upon receiving a command for reading a data page, the process, in one embodiment, identifies a reference page which is located at a predefined location in a block of... Agent: Cnexlabs, Inc.
20150036431 - Operating method of nonvolatile memory device and operating method of memory controller controlling the nonvolatile memory device: An operating method of a memory controller controlling a nonvolatile memory device including a plurality of pages includes receiving a read request and a logical address from an additional device; determining a program state of an upper unselected word line of a selected word line corresponding to the received logical... Agent: Samsung Electronics Co., Ltd.
20150036433 - Semiconductor memory device and methods of operating the same: A semiconductor memory device comprises a memory cell array including a plurality of memory blocks each including a plurality of pages, wherein each of the plurality of pages includes at least one flag cell indicating whether data is in a corresponding page, and a peripheral circuit configured to read data... Agent:
20150036434 - Semiconductor memory device: According to one embodiment, a semiconductor memory device reads data in units of page. The device includes: a memory cell array; a plurality of latch circuits; and an arithmetic operation circuit. The memory cell array holds data multiplexed in at least three pages. The latch circuits read and hold the... Agent: Kabushiki Kaisha Toshiba
20150036435 - Nonvolatile memory device, memory system including the same, and method of operating nonvolatile memory device: A non-volatile memory device includes a non-volatile memory cell array including a plurality of word lines, a voltage generator configured to generate a first high-voltage using a supply voltage and a second high-voltage using an external voltage which is higher than the supply voltage, and a word line selection circuit... Agent:
20150036436 - Method and apparatus for reducing erase time of memory by using partial pre-programming: Memory cells of a nonvolatile memory array are characterized by one of multiple threshold voltage ranges including at least an erased threshold voltage range and a programmed threshold voltage range. Responsive to an erase command to erase a group of memory cells of the nonvolatile memory array, a plurality of... Agent: Macronix International Co., Ltd.
20150036437 - Flash memory cell with capacitive coupling between a metal floating gate and a metal control gate: An apparatus includes a storage transistor. The storage transistor includes a floating gate configured to store electrical charge and a control gate. The floating gate is coupled to the control gate via capacitive coupling. The floating gate and the control gate are metal. The apparatus also includes an access transistor... Agent: Qualcomm Incorporated
20150036438 - Semiconductor apparatus: A semiconductor apparatus includes an input buffer configured to buffer and output data inputted from a data input/output pad; a data input control unit configured to transfer data outputted from the input buffer; a data output control unit configured to transfer inputted data to an output buffer; the output buffer... Agent: Sk Hynix Inc.
20150036439 - Semiconductor device: A semiconductor device includes a command combination circuit suitable for generating a combined level signal driven in synchronization with a write command and an internal write command; and a column selection circuit suitable for generating a pulse signal which includes a pulse generated at a level transition time of the... Agent: Sk Hynix Inc.
20150036440 - Semiconductor devices and semiconductor systems including the same: Semiconductor devices are provided. The semiconductor device includes a counter configured to output a first internal address signal counted in synchronization with a refresh clock signal during a refresh operation, an address transmitter configured to output a first external signal as a second internal address signal in response to a... Agent: Sk Hynix Inc.
20150036441 - Current generation circuit and semiconductor device having the same: A current generation circuit includes a mirroring circuit suitable for being charged by using a bias voltage, wherein a voltage level of the charged voltage varies corresponding to changes in a voltage level of a power voltage, a comparison circuit suitable for comparing the charged voltage with a feedback voltage,... Agent: Sk Hynix Inc.
20150036442 - Apparatuses and methods for driving a voltage of a wordline of a memory: Apparatuses, global and local wordline drivers, and methods for driving a wordline voltage in a memory is described. An example apparatus includes a memory array including a plurality of sub-arrays. The plurality of sub arrays are coupled to a wordline. The memory array further including a plurality of local wordline... Agent: Micron Technology, Inc.
20150036443 - Semiconductor memory device, method of controlling read preamble signal thereof, and data transmission system: A system, includes a controller comprising a plurality of first external terminals configured to supply a command and an address, and communicate a data, and communicate a strobe signal related to the data; and a semiconductor memory device including a plurality of second external terminals corresponding to the plurality of... Agent:
20150036444 - Sensor amplifier, memory device comprising same, and related method of operation: A sense amplifier comprises a sense amplifying unit configured to be connected to a bitline and a complimentary bitline of a memory device, to sense a voltage change of the bitline in response to first and second control signals, and to control voltages of a sensing bitline and a complimentary... Agent: Samsung Electronics Co., Ltd.
20150036445 - Semiconductor device: Disclosed herein is a semiconductor device that includes: a memory cell array including a plurality of memory groups each having a plurality of memory cells, the memory groups being selected by mutually different addresses; a first control circuit periodically executing a refresh operation on the memory groups in response to... Agent:
20150036446 - Dual supply memory: According to one general aspect, an apparatus may include a first power supply configured to generate a first power signal having one of a plurality of voltages, and a second power supply configured to generate a second power signal that includes a voltage equal to or higher than a voltage... Agent:
20150036447 - Flip-flop with zero-delay bypass mux: Exemplary embodiments may disclose a flip-flop circuit for inserting a zero-delay bypass mux including a master circuit which is configured to receive a data input, an input clock signal, and a bypass signal, and output an intermediate signal to a first node; and a slave circuit which is configured to... Agent:
20150036448 - Output circuit for implementing high speed data transmition: An output circuit includes first and second output drivers. The first output driver is configured to transfer a first data signal directly to an output pad in synchronization with a clock signal. The second output driver is configured to transfer a second data signal directly to the output pad in... Agent:01/29/2015 > 36 patent applications in 26 patent subcategories.
20150029773 - Context protection for a column interleaved memory: A semiconductor memory cell includes a set of circuit structures, each having column input/output circuits. The semiconductor memory cell further includes a set of replicas corresponding to the column input/output circuits. The set of replicas are non-functional and fills an empty space next to the column input/output circuits and hence,... Agent: Texas Instruments Incorporated
20150029774 - Stacked device identification assignment: Some embodiments include apparatus and methods having dice arranged in a stack. The dice include at least a first die and a second die, and a connection coupled to the dice. The connection may be configured to transfer control information to the first die during an assignment of a first... Agent:
20150029775 - Memory cell array structures and methods of forming the same: The present disclosure includes memory cell array structures and methods of forming the same. One such array includes a stack structure comprising a memory cell between a first conductive material and a second conductive material. The memory cell can include a select element and a memory element. The array can... Agent: Micron Technology, Inc.
20150029777 - Circuit and system of using junction diode of mos as program selector for programmable resistive devices: A programmable resistive device cell using at least one MOS device as selector can be programmed or read by turning on a source junction diode of the MOS or a channel of the MOS. A programmable resistive device cell can include at least one programmable resistive element and at least... Agent:
20150029776 - Semiconductor device having a reduced area and enhanced yield: A device includes a first power supply line supplying a first voltage, first, second, and third nodes, a selection circuit connected between the first power supply line and the first node, a first anti-fuse connected between the first node and the second node, and a second anti-fuse connected between the... Agent:
20150029778 - Mask-programmed read only memory with enhanced security: A mask-programmed read-only memory (MROM) has a plurality of column line pairs, each having a bit line and a complement bit line. The MROM includes a plurality of memory cells corresponding to a plurality of intersections between the column line pairs and a plurality of word liens. Each memory cell... Agent: Qualcomm Incorporated
20150029779 - Electronic device and method for fabricating the same: This technology provides an electronic device and a method of fabricating the same. An electronic device in accordance with an implementation of this document includes semiconductor memory, and the semiconductor memory includes a lower electrode, a variable resistance element over the lower electrode, an upper electrode disposed over the variable... Agent: Sk Hynix Inc.
20150029780 - Two-terminal reversibly switchable memory device: A memory using mixed valence conductive oxides is disclosed. The memory includes a mixed valence conductive oxide that is less conductive in its oxygen deficient state and a mixed electronic ionic conductor that is an electrolyte to oxygen and promotes an electric field effective to cause oxygen ionic motion.... Agent:
20150029781 - Method and apparatus for sensing in a memory: A method and a memory for sensing a state of a memory cell while the memory cell capacitor is isolated from a data line are described. An activation device of the memory cell can be enabled to couple the memory cell capacitor to a parasitic capacitance of the active data... Agent: Micron Technology, Inc.
20150029783 - Method of detecting transistors mismatch in a sram cell: The present invention provides a method of detecting the transistor mismatch in a SRAM cell. The SRAM cell comprises two pass-gate transistors and a bi-stable circuit including two pull up transistors and two pull down transistors. The method comprises: providing two measuring transistors, whose gates are connected to a second... Agent: Shanghai Huali Microelectronics Corporation
20150029785 - Methods for operating a finfet sram array: A method of operating an SRAM array may include: providing a plurality of bit cells, each of the plurality of bit cells comprising a cross coupled inverter pair; a first pass gate; and a second pass gate. A word line voltage may be applied to the first pass gate and... Agent:
20150029784 - Semiconductor integrated circuit device: There is provided a semiconductor integrated circuit device that can generate a unique ID with the suppression of overhead. When a unique ID is generated, the potential of a word line of a memory cell in an SRAM is raised above the power supply voltage of the SRAM, and then... Agent: Renesas Electronics Corporation
20150029782 - Wide range multiport bitcell: A multiport bitcell including a pair of cross-coupled inverters is provided with increased write speed and enhanced operating voltage range by the selective isolation of a first one of the cross-coupled inverters from a power supply and ground during a write operation. The write operation occurs through a write port... Agent: Qualcomm Incorporated
20150029786 - Self-referenced sense amplifier for spin torque mram: Circuitry and a method provide a plurality of timed control and bias voltages to sense amplifiers and write drivers of a spin-torque magnetoresistive random access memory array for improved power supply noise rejection, increased sensing speed with immunity for bank-to-bank noise coupling, and reduced leakage from off word line select... Agent:
20150029787 - Non-volatile resistance-switching thin film devices: Disclosed herein are resistive switching devices having, e.g., an amorphous layer comprised of an insulating aluminum-based or silicon-based material and a conducting material. The amorphous layer may be disposed between two or more electrodes and be capable of switching between at least two resistance states. Circuits and memory devices including... Agent:
20150029788 - Methods of programming memory devices: Methods of programming memory devices include biasing each data line of a plurality of data lines to a program inhibit voltage; discharging a first portion of data lines of the plurality of data lines, wherein the first portion of data lines of the plurality of data lines are coupled to... Agent: Micron Technology, Inc.
20150029789 - Nonvolatile memory device including memory cell array with upper and lower word line groups: A nonvolatile memory device includes a memory cell array having multiple memory blocks. Each memory block includes memory cells arranged at intersections of multiple word lines and multiple bit lines. At least one word line of the multiple word lines is included in an upper word line group and at... Agent:
20150029790 - Nonvolatile memory and erasing method thereof: An erase method of a nonvolatile memory includes supplying an erase voltage to a substrate, supplying a selection word line voltage to word lines connected with a selected sub-block within a memory block of the nonvolatile memory, supplying a non-selection word line voltage to word lines connected with an unselected... Agent:
20150029791 - Nonvolatile semiconductor memory device: A control circuit is configured to execute an erasing operation on a selected cell unit in a selected memory block. In the erasing operation, the control circuit raises the voltage of the bodies of the first memory transistors included in the selected cell unit to a first voltage, sets the... Agent: Kabushiki Kaisha Toshiba
20150029793 - Nonvolatile semiconductor memory device: A nonvolatile semiconductor memory device including: a memory cell array including NAND strings; a plurality of word lines; a plurality of bit lines; a source line; and a control circuit configured to execute a write operation. The control circuit is configured to, when charging an unselected memory string prior to... Agent: Kabushiki Kaisha Toshiba
20150029792 - Semiconductor memory device and method of operating the same: A semiconductor memory device and a method of operating the same are provided. When threshold voltages of memory cells are boosted to use the memory cells as a selection transistor, a threshold voltage of an outermost memory cell may be boosted to the highest level so that a leakage current... Agent: Sk Hynix Inc.
20150029794 - Differential current sensing scheme for magnetic random access memory: A circuit for a differential current sensing scheme includes first and second cell segments, first and second reference cells, and first and second current sense amplifiers. The first and second reference cells are configured to store opposite logic values. The first and second current sense amplifiers are each configured with... Agent: Taiwan Semiconductor Manufacturing Company Ltd.
20150029795 - Selective dual cycle write operation for a self-timed memory: A write is performed to a first cell of a memory at a first row and column during a first memory access cycle. A memory access operation is made to a second cell at a second row and column during an immediately following second memory access cycle. If the memory... Agent: Stmicroelectronics International N.v.
20150029796 - Memory device, memory system, and method of controlling read voltage of the memory device: A memory device includes a memory cell array having a plurality of memory cells, and a page buffer unit including a plurality of page buffers configured to store a plurality of pieces of data sequentially read from some of the plurality of memory cells at different read voltage levels, respectively,... Agent:
20150029797 - Memory macro with a voltage keeper: A memory macro comprises a data line, a first interface circuit comprising a first node coupled to the data line, and a voltage keeper configured to control a voltage level at the first node, and a second interface circuit comprising a second node coupled with the data line, wherein the... Agent: Taiwan Semiconductor Manufacturing Company Ltd.
20150029798 - Apparatuses and methods for performing compare operations using sensing circuitry: The present disclosure includes apparatuses and methods related to performing compare and/or report operations using sensing circuitry. An example method can include charging an input/output (IO) line of a memory array to a voltage. The method can include determining whether data stored in the memory array matches a compare value.... Agent: Micron Technology, Inc.
20150029799 - Canary circuit with passgate transistor variation: A canary circuit with passgate transistor variation is described herein. The canary circuit includes a memory canary circuit that has a plurality of bitcells. Each bitcell has at least a passgate transistor that is driven by a wordline voltage. The canary circuit further includes a regulator circuit that outputs a... Agent: Advanced Micro Devices, Inc.
20150029800 - Semiconductor device: An interface circuit provided in a semiconductor device supplies an operation clock to an external memory device based on a clock signal and receives a data signal and a strobe signal from the external memory device. The interface circuit includes a delay circuit delaying the received strobe signal. The delay... Agent: Renesas Electronics Corporation
20150029801 - Device and method for memory repair using test logic: A device for repairing a memory device using a test-bypass register associated with the memory device may include a comparator configured to compare a current address of the memory device with a faulty address and to generate a match signal when the current address matches the faulty address. A logic... Agent: Broadcom Corporation
20150029802 - Apparatuses, integrated circuits, and methods for measuring leakage current: Methods, apparatuses, and integrated circuits for measuring leakage current are disclosed. In one such example method, a word line is charged to a first voltage, and a measurement node is charged to a second voltage, the second voltage being less than the first voltage. The measurement node is proportionally coupled... Agent:
20150029803 - Single-ended low-swing power-savings mechanism with process compensation: A single-ended low-swing power-savings mechanism is provided. The mechanism comprises a precharge device that turns off in an evaluation phase and a first biasing device is always on. Within the mechanism, a strength of a keeper device is changed to a first level in response to an input of the... Agent: International Business Machines Corporation
20150029804 - Apparatuses and methods for adjusting deactivation voltages: Apparatuses and methods for adjusting deactivation voltages are described herein. An example apparatus may include a voltage control circuit. The voltage control circuit may be configured to receive an address and to adjust a deactivation voltage of an access line associated with a target group of memory cells from a... Agent: Micron Technology, Inc.
20150029807 - Memory device and method for putting a memory cell into a state with a reduced leakage current consumption: In various embodiments, a memory device includes at least one memory cell and at least one virtual supply line coupled to the at least one memory cell. The memory device is designed in such a way that a voltage potential present on the virtual supply line is altered after an... Agent:
20150029805 - Semiconductor memory device: A semiconductor memory device includes a plurality of first regions formed in a line-type and extending in a first direction, and a plurality of second regions and a plurality of third regions arranged between adjacent first regions in a zigzag manner.... Agent: Sk Hynix Inc.
20150029806 - Voltage control integrated circuit devices: Voltage control in integrated circuits include a first voltage divider coupled to receive a reference voltage and having an output providing an adjusted reference voltage; an operational amplifier having a first input coupled to receive the output of the first voltage divider, a second input coupled to receive a feedback... Agent:
20150029808 - Power fail protection and recovery using low power states in a data storage device/system: Systems and methods for early warnings of power loss in solid state storage drives are disclosed. Early warnings of power loss can be used to power the drive to force the drive into a low power states before the energy in backup power sources, such as backup capacitors, is used.... Agent: Western Digital Technologies, Inc.01/22/2015 > 38 patent applications in 28 patent subcategories.
20150023085 - Semiconductor storage device: A semiconductor storage device according to the present embodiment includes a plurality of bit lines, a plurality of word lines, and a plurality of memory cells each including a storage element and a switching element which are connected in series between adjacently paired ones of the bit lines. Gates of... Agent:
20150023086 - Multiport memory cell having improved density area: A mutltiport memory cell having improved density area is disclosed. The memory cell includes a data storing component, a first memory access component coupled to a first side of the data storing component, a second memory access component coupled to a second side of the data storing component, first and... Agent: Soft Machines, Inc.
20150023087 - Semiconductor memory: A semiconductor memory includes a memory cell array having a plurality of memory cells, a plurality of bit line pairs which are disposed corresponding to respective columns of the memory cell array, and a sense amplifiers which are disposed in plurality corresponding to the plurality of bit line pairs for... Agent:
20150023088 - Apparatuses and methods for sensing fuse states: Apparatuses and methods for sensing fuse states are disclosed herein. An apparatus may include an array having a plurality of sense lines. A plurality of cells may be coupled to a sense line of the plurality of sense lines. A fuse sense circuit may coupled to the sense line of... Agent:
20150023089 - Resistance variable element methods and apparatuses: Apparatus and methods are disclosed, including a method that performs a first operation on a first resistance variable element using a common source voltage, a first data line voltage and a first control gate voltage, and then performs a second operation on a second resistance variable element using the common... Agent: Micron Technology, Inc.
20150023090 - Semiconductor memory device: To increase a storage capacity of a memory module per unit area, and to provide a memory module with low power consumption, a transistor formed using an oxide semiconductor film, a silicon carbide film, a gallium nitride film, or the like, which is highly purified and has a wide band... Agent:
20150023091 - Semiconductor device having timing control for read-write memory access operations: A semiconductor device avoids the disturb problem and the collision between write and read operations in a DP-SRAM cell or a 2P-SRAM cell. The semiconductor device 1 includes a write word line WLA and a read word line WLB each coupled to memory cells 3. A read operation activates the... Agent: Renesas Electronics Corporation
20150023093 - Method of writing to a spin torque magnetic random access memory: Circuitry and a method provide an increased tunnel barrier endurance (lifetime) previously shortened by dielectric breakdown by providing a pulse of opposite polarity associated with a write pulse. The pulse of opposite polarity may comprise equal or less width and amplitude than that of the write pulse, may be applied... Agent: Everspin Technologies Inc.
20150023092 - Ring-shaped magnetoresistive memory device and writing method thereof: A ring-shaped magnetoresistive memory device includes a ring-shaped magnetoresistive memory cell, a first conductor, and a second conductor. The first conductor is positioned on a first surface of the ring-shaped magnetoresistive memory cell for generating a first magnetic field pulse. The second conductor is positioned on a second surface of... Agent: National Yunlin University Of Science And Technology
20150023095 - Apparatuses including current compliance circuits and methods: Apparatus, devices, systems, and methods are described that include variable state material data storage. Example devices include current compliance circuits that are configured to dynamically adjust a current passing through a variable resistance material during a memory operation. Some configurations utilize components within an array of memory cells to form... Agent:
20150023094 - Drift mitigation for multi-bits phase change memory: An RC-based sensing method and computer program product to effectively sense the cell resistance of a programmed Phase Change Material (PCM) memory cell. The sensing method ensures the same physical configuration of each cell (after programming): same amorphous volume, same trap density/distribution, etc. The sensing method is based on a... Agent:
20150023096 - Counterbalanced-switch mram: A magnetic memory cell is provided. The cell comprises first and second free layers; and an intermediate layer separating the first and second free layers, wherein the first and second free layers are magnetostatically coupled.... Agent: Magsil Corporation
20150023099 - Direct multi-level cell programming: A method is performed in a data storage device that includes a controller coupled to a non-volatile memory. The non-volatile memory includes a group of storage elements. Each storage element is configured to store multiple data bits. Data is sent from the controller to the non-volatile memory and first bits... Agent: Sandisk Technologies Inc.
20150023098 - Operation method of multi-level memory: An operation method of a multi-level memory is provided. A first read voltage lower than a standard read voltage is applied to a doped region in a substrate at one side of a control gate of the memory, so as to determine whether a first storage position and a second... Agent:
20150023097 - Partial reprogramming of solid-state non-volatile memory cells: Method and apparatus for managing data in a memory, such as a flash memory array. In accordance with some embodiments, data are written to a set of solid-state non-volatile memory cells so that each memory cell in the set is written to an associated initial programmed state. Drift in the... Agent: Seagate Technology LLC
20150023100 - Dynamic regulation of memory array source line: To maintain stability of memory array operations, a current source supplies a common source line of a memory. The magnitude of the regulation current from the source is dynamically determined based on the amount of current from the array itself through use of a feedback control signal provided by a... Agent:
20150023101 - Memory system and method of controlling memory system: According to one embodiment, a low power direction received from a host device is delayed for a first predetermined time and is output as a first signal, and an internal state is caused to transition to a low power consumption mode that corresponds to the low power direction when a... Agent: Kabushiki Kaisha Toshiba
20150023102 - Nonvolatile semiconductor memory device: In a writing operation, a control circuit raises the voltage of a writing-prohibited bit line among a plurality of bit lines to a first voltage, and thereafter brings the writing-prohibited bit line into a floating state. Then, the control circuit raises the voltage of a writing bit line other than... Agent: Kabushiki Kaisha Toshiba
20150023103 - Semiconductor device and method of operating the same: A semiconductor device includes first memory blocks arranged in a longitudinal direction, and including a plurality of strings, wherein the strings are formed along a vertical direction, and the strings adjacent to each other share bit lines or source lines with each other, each string including a drain selection transistor... Agent: Sk Hynix Inc.
20150023104 - Apparatuses and methods for measuring an electrical characteristic of a model signal line and providing measurement information: Apparatuses and methods for measuring an electrical characteristic of a model signal line and providing measurement information based at least in part on the measurement of the electrical characteristic. An example apparatus includes a signal line model including a model signal line configured to model electrical characteristics of a signal... Agent:
20150023105 - Memory cell comprising first and second transistors and methods of operating: Semiconductor memory cells, array and methods of operating are disclosed. In one instance, a memory cell includes a bi-stable floating body transistor and an access device; wherein the bi-stable floating body transistor and the access device are electrically connected in series.... Agent:
20150023106 - Adaptive erase recovery for non-volatile memory (nvm) systems: Methods and systems are disclosed for adaptive erase recovery of non-volatile memory (NVM) cells within NVM systems. The adaptive erase recovery embodiments adaptively adjust the erase recovery discharge rate and/or discharge time based upon the size of NVM block(s) being erased and operating temperature. In one example embodiment, the erase... Agent:
20150023107 - Nonvolatile semiconductor memory device: A first non-selected word line including a word line adjacent to a selected word line is applied with a first write pass voltage. Furthermore, a second non-selected word line which is a non-selected word line excluding the first non-selected word line is applied with a second write pass voltage smaller... Agent: Kabushiki Kaisha Toshiba
20150023108 - Nonvolatile memory device and related programming method: A nonvolatile memory device comprises a memory cell array comprising multiple memory cells disposed at intersections of corresponding word lines and bitlines, and multiple page buffers connected to the bitlines, respectively, and performing consecutive verify read operations on selected memory cells programmed in first to N-th logic states (N>2), wherein,... Agent: Samsung Electronics Co., Ltd.
20150023109 - Nonvolatile semiconductor memory device: A nonvolatile semiconductor memory device comprises a memory cell array, a staircase voltage generator, and a decode and level shift circuit. The memory cell array comprises a plurality of memory cells and a plurality of bit lines coupled to the plurality of memory cells. The staircase voltage generator generates a... Agent: Elite Semiconductor Memory Technology Inc.
20150023110 - Inferring threshold voltage distributions associated with memory cells via interpolation: The present disclosure includes apparatuses and methods for inferring threshold voltage distributions associated with memory cells via interpolation. A number of embodiments include determining soft data for a group of memory cells each programmed to one of a number of data states, wherein the soft data comprises a number of... Agent:
20150023111 - Nonvolatile semiconductor memory device: A nonvolatile semiconductor memory device of an embodiment includes a p-type semiconductor substrate, a first P-well formed in the semiconductor substrate, and on which a plurality of memory cells is formed, an first N-well surrounding the first P-well and electrically separating the first P-well from the semiconductor substrate, a first... Agent: Kabushiki Kaisha Toshiba
20150023115 - Compensation scheme for non-volatile memory: Methods for performing parallel voltage and current compensation during reading and/or writing of memory cells in a memory array are described. In some embodiments, the compensation may include adjusting a bit line voltage and/or bit line reference current applied to a memory cell based on a memory array zone, a... Agent:
20150023114 - Semiconductor device and method for driving the same: One of a source and a drain of a first oxide semiconductor (OS) transistor is connected to a gate of a second OS transistor and one electrode of a first capacitor. One of a source and a drain of the second OS transistor is connected to one electrode of a... Agent:
20150023112 - Integrated circuit and data input method: An integrated circuit includes a data input such as a data pad for receiving an external data signal input and an on-die termination (ODT) information input for receiving ODT information from an external device. An ODT circuit selectively couples a termination resistor to the data pad based on the ODT... Agent: Samsung Electronics Co., Ltd.
20150023113 - Compensation scheme for non-volatile memory: Methods for performing parallel voltage and current compensation during reading and/or writing of memory cells in a memory array are described. In some embodiments, the compensation may include adjusting a bit line voltage and/or bit line reference current applied to a memory cell based on a memory array zone, a... Agent:
20150023116 - Non-volatile memory and method with peak current control: A non-volatile memory with multiple memory dice manages simultaneous operations so as to not exceed a system power capacity. A load signal bus is pulled up with a strength proportional to the system power capacity. Each die has a driver to pull down the bus by an amount corresponding to... Agent:
20150023117 - Methods for sensing memory elements in semiconductor devices: A memory device that, in certain embodiments, includes a plurality of memory elements connected to a bit-line and a delta-sigma modulator with a digital output and an analog input, which may be connected to the bit-line. In some embodiments, the delta-sigma modulator includes a circuit with first and second inputs... Agent:
20150023118 - Reconfigurable memory system data strobes: In a reconfigurable data strobe-based memory system, data strobes may be re-tasked in different modes of operation. For example, in one mode of operation a differential data strobe may be used as a timing reference for a given set of data signals. In a second mode of operation, one of... Agent:
20150023120 - Memory device and read operation method thereof: A read operation for a memory device is provided. A selected word line, first and second global bit line groups and a selected first bit line group are precharged. A first cell current flowing through the selected word line, the first and the selected first bit line groups is generated.... Agent:
20150023119 - Semiconductor device and semiconductor system having the same: A semiconductor device includes a column command generation unit suitable for generating a column command delayed by a first delay time from a source command, in response to a first control signal and the source command, a bank address generation unit suitable for generating a bank address delayed by the... Agent: Sk Hynix Inc.
20150023121 - Memory refresh methods, memory section control circuits, and apparatuses: Apparatuses, memory section control circuits, and methods of refreshing memory are disclosed. An example apparatus includes a plurality of memory sections and a plurality of memory section control circuits. Each memory section control circuit is coupled to a respective one of the plurality of memory sections and includes a plurality... Agent:
20150023122 - Method and apparatus for memory power and/or area reduction: A method and apparatus for memory power and/or area reduction. An array of memory cells may be scanned to detect faulty memory cells, if any, in the array. A supply voltage Vmem applied to the array of memory cells may be controlled based on a result of the scan, and... Agent:01/15/2015 > 36 patent applications in 24 patent subcategories.
20150016172 - Query operations for stacked-die memory device: An integrated circuit (IC) package includes a stacked-die memory device. The stacked-die memory device includes a set of one or more stacked memory dies implementing memory cell circuitry. The stacked-die memory device further includes a set of one or more logic dies electrically coupled to the memory cell circuitry. The... Agent:
20150016173 - Rom chip manufacturing structures: An integrated circuit (IC) chip embodiment includes first and second ROM cells arranged in a same row of a ROM array. The first and second ROM cells include first portions of first and second gate structures, respectively. The IC chip further includes a strap cell disposed between the first and... Agent:
20150016174 - Integrated circuits with programmable electrical connections and methods for fabricating the same: Methods and apparatus are provided for an integrated circuit with a programmable electrical connection. The apparatus includes an inactive area with a memory line passing over the inactive area. The memory line includes a programmable layer. An interlayer dielectric is positioned over the memory line and the inactive area, and... Agent:
20150016175 - Cmos analog memories utilizing ferroelectric capacitors: A memory cell and memories constructed from that memory cell are disclosed. A memory according to the present invention includes a ferroelectric capacitor, a charge source and a read circuit. The charge source receives a data value to be stored in the ferroelectric capacitor. The charge source converts the data... Agent: Radiant Technologies, Inc.
20150016178 - All around electrode for novel 3d rram applications: A resistive switching memory device can include three or more electrodes interfacing a switching layer, including a top electrode, a bottom electrode, and a side electrode. The top and bottom electrodes can be used for forming conductive filaments and for reading the memory device. The side electrode can be used... Agent: Intermolecular Inc.
20150016176 - Memory storage circuit and method of driving memory storage circuit: A memory storage circuit includes a volatile memory portion, a control portion, and a non-volatile memory portion. The volatile memory portion includes a first node and a second node to store a pair of complementary logic data. The control portion includes a first transistor and a second transistor. Gate electrodes... Agent:
20150016177 - Nonvolatile semiconductor memory device: A nonvolatile semiconductor memory device according to an embodiment comprises: a memory cell array including a plurality of memory cells provided one at each of intersections of a plurality of first lines and a plurality of second lines and each storing data by a data storing state of a filament;... Agent: Kabushiki Kaisha Toshiba
20150016180 - Memory architectures having dense layouts: Some embodiments relate to a memory cell to store one or more bits of data. The memory cell includes a capacitor including first and second capacitor plates which are separated from one another by a dielectric. The first capacitor plate corresponds to a doped region disposed in a semiconductor substrate,... Agent:
20150016179 - Memory circuit: While the supply of power is stopped, a data signal that has been held in a volatile memory section can be held in a nonvolatile memory section. In the nonvolatile memory section, a transistor having an extremely low off-state current allows a data signal to be held in the capacitor... Agent:
20150016181 - Memory device and driving method of the memory device: A memory device which can reduce power consumption and a driving method thereof are disclosed. In a memory element including an inverter and the like, a capacitor for holding data and a capacitor switching element for controlling store and release of charge in the capacitor are provided. The capacitor switching... Agent:
20150016182 - Sram memory card and voltage monitoring circuit: An SRAM memory card includes a monitoring unit that monitors, via a contact, a power supply voltage generated by a battery, set an ON value in an alarm signal when electric potential at the contact is lower than a threshold and set an OFF value in the alarm signal when... Agent: Mitsubishi Electric Corporation
20150016183 - Sense amplifier with transistor threshold compensation: One embodiment provides, in a sense amplifier for an electronic memory array in which a selected memory cell drives a developing voltage differential according to a logic state of the memory cell, a method to store the logic state. The method includes poising source voltages of first and second transistors... Agent:
20150016184 - Magnetic field sensing using magnetoresistive random access memory (mram) cells: A magnetic field sensing system includes one or more magnetoresistive random access memory (MRAM) cells, and may be configured to determine one or more of a presence, a magnitude, and a polarity of an external magnetic field incident upon an MRAM cell. In some examples, a control module of the... Agent:
20150016185 - Electro-mechanical diode non-volatile memory cell for cross-point memory arrays: A non-volatile electro-mechanical diode memory cell is described for implementation of compact (4F2) cross-point memory arrays. The electro-mechanical diode memory cells operate with relatively low set/reset voltages and excellent retention characteristics, and are multi-time programmable. Due to its simplicity, this electro-mechanical diode memory cell is attractive for implementation of three-dimensional... Agent: The Regents Of The University Of California
20150016187 - Asymmetric log-likelihood ratio for flash channel: Disclosed is a system and method for reading a flash memory cell with an adjusted read level. A current read level is set to a new read level associated with increasing a first error rate to decrease a second error rate. The first error rate is associated with determining that... Agent:
20150016186 - Methods and apparatuses for determining threshold voltage shift: Apparatuses and methods for determining threshold voltage shift are described. A number of methods for determining threshold voltage shift in memory cells include determining changes in threshold voltage for memory cells at each data state of a first number of data states by searching threshold voltage data of memory cells... Agent:
20150016188 - Method for managing the operation of a memory device having a sram memory plane and a non volatile memory plane, and corresponding memory device: A method can be used for managing the operation of a memory cell that includes an SRAM elementary memory cell and a non-volatile elementary memory cell coupled to one another. A data bit is transferred between the SRAM elementary memory cell and the non-volatile elementary memory cell. A control datum... Agent:
20150016189 - Semiconductor memory device and method of operating the same: Disclosed are a semiconductor memory device and an operating method thereof. The semiconductor memory device includes a memory cell block including a plurality of memory cells, a voltage providing unit suitable for providing a pass voltage or a read voltage to word lines coupled with the memory cells and a... Agent: Sk Hynix Inc.
20150016190 - Nonvolatile semiconductor memory device: A nonvolatile semiconductor memory device comprises multiple memory strings each including a plurality of first and second groups of serially connected memory cells, and a back gate transistor serially connected between the first and second groups of memory cells, a plurality of word lines, each word line being connected to... Agent:
20150016191 - Data storage device and flash memory control method: An overclocking process for a data storage device using a flash memory. A controller for the flash memory tests the flash memory using test clocks with various frequencies to determine at least one clock signal suitable to the flash memory. The clock candidates suitable to the flash memory are selected... Agent:
20150016192 - Method of using non-volatile memories for on-dimm memory address list storage: An integrated circuit device. The device includes an address input(s) configured to receive address information from an address stream from an address command bus coupled to a host controller and an address output(s) configured to drive address information, and is coupled to a plurality of memory (DRAM) devices provided on... Agent:
20150016193 - Circuit configuration and operating method for same: A circuit configuration is described including a first input for inputting a first set of digital input data, an output for outputting digital output data, and a control input for receiving a control signal. At least two register units are provided and the circuit configuration is designed to write, as... Agent: Robert Bosch Gmbh
20150016195 - Compensation circuit for use with input buffer and method of operating the same: A compensation circuit for use with an input buffer includes an input buffer configured to amplify an input signal and output a compensated signal. A process detector includes a replica of the input buffer. The process detector is configured to output at least one comparison signal indicating a variation in... Agent:
20150016196 - Data input circuit: A data input circuit includes a clock sampling unit, a final clock generation unit, and a write latch signal generation unit. The sampling unit is configured to generate a shifting signal including a pulse generated after a write latency is elapsed, and generate a sampling clock by sampling an internal... Agent:
20150016194 - Semiconductor memory device and memory system including the same: A semiconductor memory device and a memory system including the same are provided. The semiconductor memory device includes a first memory unit and a plurality of second memory unit, each including a plurality of memory cells and page buffers corresponding to the memory cells, and a redundancy memory unit including... Agent: Sk Hynix Inc.
20150016198 - Multiple power domain circuit and related method: A method comprises providing a trigger signal, generating an input pulse according to the trigger signal, inverting the input pulse to generate an inverted input pulse and pulling down an output voltage using the inverted input pulse, wherein the inverted pulse is applied to a transistor of a high threshold... Agent:
20150016197 - Semiconductor memory device that does not require a sense amplifier: A semiconductor memory device that does not require a sense amplifier includes a memory cell group having at least one memory cell, a buffer unit, and a bias voltage unit. The buffer unit includes a tri-state buffer that has an input terminal coupled to the memory cell group, and an... Agent:
20150016199 - Bit line equalizing circuit: There is provided a bit line equalizing circuit including: an active region; a first bit line disposed on the active region in a first direction; a second bit line disposed on the active region in the first direction; a gate pattern including a first pattern disposed on the active region... Agent: Samsung Electronics Co., Ltd.
20150016200 - Memory device for masking read data and a method of testing the same: A memory device includes a memory array, a plurality of input/output pins, a mask signal generator, an input/output block. The memory array is configured to output read data including a plurality of data bits. The mask signal generator is configured to generate at least one data mask signal. The input/output... Agent:
20150016201 - Semiconductor device: A semiconductor device includes first and second bank groups coupled to first and second data lines which are electrically isolated from each other. The semiconductor device includes a register unit suitable for providing predetermined data to the second data line in a specific mode, a data transfer and output unit... Agent: Sk Hynix Inc.
20150016202 - Memory devices, systems and methods employing command/address calibration: During a command/address calibration mode, a memory controller may transmit multiple cycles of test patterns as signals to a memory device. Each cycle of test pattern signals may be transmitted at an adjusted relative phase with respect to a clock also transmitted to the memory device. The memory device may... Agent:
20150016203 - Dram sub-array level autonomic refresh memory controller optimization: A method of refreshing a dynamic random access memory (DRAM) includes detecting an open page of the DRAM at a row of a DRAM bank within an open sub-array of the DRAM bank. The method also includes delaying issuance of a refresh command to a target refresh row of the... Agent: Qualcomm Incorporated
20150016204 - Insertion-override counter to support multiple memory refresh rates: A memory refresh method includes determining positions at which to insert refresh operations of weak rows of a memory block among regularly scheduled refresh operations of normal rows of the memory block. The refresh operations occur at a substantially constant refresh rate. The positions at which to insert are based... Agent: Qualcomm Incorporated
20150016205 - Semiconductor circuit: A semiconductor circuit includes a first input section into which a first input signal is inputted, a second input section into which a second input signal is inputted, an output generation circuit which is connected to the first and second input sections and generates an output signal based on the... Agent: Kabushiki Kaisha Toshiba
20150016206 - Apparatus and method to measure energy capacity of a backup power supply without compromising power delivery: A device includes a backup power supply configured to provide power to an external system upon loss of primary system power. The backup power provided by at least one capacitor. While the capacitor is available as a backup power supply to the external system, a transient elevation of the capacitor's... Agent:
20150016207 - Systems and methods for reducing standby power in floating body memory devices: Methods, devices, arrays and systems for reducing standby power for a floating body memory array. One method includes counting bits of data before data enters the array, wherein the counting includes counting at least one of: a total number of bits at state 1 and a total number of all... Agent:Previous industry: Electric power conversion systems
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