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Static information storage and retrieval

Below are recently published patent applications awaiting approval from the USPTO. Recent week's RSS XML file available below.
Listing for abstract view: USPTO application #, Title, Abstract excerpt,Patent Agent. Listing format for list view: USPTO National Class full category number, title of the patent application.
  
04/23/2015 > 36 patent applications in 26 patent subcategories.

20150109840 - Semiconductor device and method for operating the same: A semiconductor device employs a technology for improving data retention characteristics of a cell array storing data regarding conditions for controlling internal operations of the semiconductor device. The semiconductor device includes a content addressable memory (CAM) cell array configured to store CAM data regarding conditions for controlling the internal operations,... Agent: Sk Hynix Inc.

20150109841 - Semiconductor device and method for operating the same: A semiconductor device comprises a memory block having a content addressable memory (CAM) cell array storing data for internal operation conditions, and a memory cell array. The semiconductor device also comprises a page buffer to program data in the memory block or read the data programmed in the memory block;... Agent: Sk Hynix Inc.

20150109842 - Semiconductor storage device: A semiconductor storage device 1 includes: an input controller (3); and a content-addressable memory block (2) connected to the input controller (3). Each word circuit (4) of the content-addressable memory block (2) includes: a k-bit 1st-stage sub word (4a) connected to search line 1 (SL1) of the input controller (3);... Agent: Tohoku University

20150109843 - Monolithic three dimensional (3d) integrated circuits (ics) (3dics) with vertical memory components, related systems and methods: Monolithic three dimensional (3D) integrated circuits (ICs) (3DICs) with vertical memory components are disclosed. A 3D memory crossbar architecture with tight-pitched vertical monolithic intertier vias (MIVs) for inter-block routing and multiplexers at each tier for block access is used to shorten overall conductor length and reduce resistive-capacitive (RC) delay. Elimination... Agent: Qualcomm Incorporated

20150109844 - Integrated circuit and operating method for the same: An integrated circuit and an operating method for the same are provided. The integrated circuit comprises a stacked structure and a conductive structure. The stacked structure comprises a conductive strip. The conductive structure is disposed above the stacked structure and electrically connected to the conductive strip. The conductive structure and... Agent: Macronix International Co., Ltd.

20150109845 - Signal timing alignment based on a common data strobe in memory devices configured for stacked arrangements: Disclosed are various embodiments related to stacked memory devices, such as DRAMs, SRAMs, EEPROMs, ReRAMs, and CAMs. For example, stack position identifiers (SPIDs) are assigned or otherwise determined, and are used by each memory device to make a number of adjustments. In one embodiment, a self-refresh rate of a DRAM... Agent:

20150109846 - Memory apparatus and memory device: A memory apparatus includes a memory device at least including a memory layer, a magnetic fixed layer, and an intermediate layer made of a non-magnetic body disposed between the memory layer and the magnetic fixed layer; current being capable of flowing in a lamination direction; a wiring for supplying current... Agent:

20150109847 - Apparatus and method for integrated circuit bit line sharing: A memory array includes a first memory column having a first bit line, a first word line and a second bit line. The memory array also includes a second memory column having the second bit line, a second word line and a third bit line. The first memory column and... Agent: Taiwan Semiconductor Manufacturing Company, Ltd.

20150109848 - Mechanisms for built-in self test and repair for memory devices: A method of storing repair data of a memory array in a one-time programming memory (OTPM) includes performing a first test and repair of the memory array using a built-in self-test-and-repair (BISTR) module to determine first repair data. The method includes loading the first repair data in a repair memory... Agent:

20150109849 - Device and method for setting resistive random access memory cell: A device and method for setting a resistive random access memory cell are provided. An exemplary method includes: providing a set current to a bit line of the RRAM cell by a current source. An exemplary device includes: a first RRAM cell and a current source. The first RRAM cell... Agent: Taiwan Semiconductor Manufacturing Company Limited

20150109851 - Memory device and access method: A memory device includes multiple bit lines extending in a first direction, multiple word lines extending in a second direction crossing the first direction, and multiple memory cells each coupled to corresponding two word lines and corresponding two bit lines. Each memory cell includes a memory element configured to store... Agent:

20150109850 - Memory devices: A device is disclosed that includes an I/O memory block. The I/O memory block includes memory cells, bit lines and a source line. The number of the formed bit lines is at least 4. The bit lines and the source line are electrically connected to the memory cells. In the... Agent: Taiwan Semiconductor Manufacturing Co., Ltd.

20150109852 - Data-controlled auxiliary branches for sram cell: A circuit includes a first inverter, a second inverter, a first auxiliary branch and a second auxiliary branch. The first and second inverters are cross-coupled to form a first storage node and a second storage node. The first auxiliary branch is coupled to the first storage node and configured to... Agent: Taiwan Semiconductor Manufacturing Company, Ltd.

20150109853 - Magnetoresistance effect element and magnetic memory: A magnetoresistance effect element including a recording layer of high thermal stability to perform perpendicular magnetic recording within a film surface, and a magnetic memory using the element. The element includes: a first ferromagnetic layer of an invariable magnetization direction; a second ferromagnetic layer of a variable magnetization direction; a... Agent: Tohoku University

20150109854 - Method for writing to a magnetic tunnel junction device: A method of applying a write current to a magnetic tunnel junction device minimizes sub-threshold leakage. NMOS- and PMOS-follower circuits are used in applying the write current, and bias signals for the follower circuits are isolated from global bias signals before the write current is applied.... Agent:

20150109855 - Semiconductor memory device: According to one embodiment, a semiconductor memory device includes a memory cell array, a buffer configured to hold data input to an input/output circuit and to hold data read from the memory cell array, and a controller configured to receive a first command and an address from the outside and... Agent:

20150109857 - Immunity of phase change material to disturb in the amorphous phase: Disturb from the reset to the set state may be reduced by creating an amorphous phase that is substantially free of crystal nuclei when programming the reset state in a phase change memory. In some embodiments, this can be achieved by using a current or a voltage to program that... Agent:

20150109856 - Semiconductor memory apparatus and temperature control method thereof: A semiconductor memory apparatus and a temperature control method thereof are provided. The semiconductor memory apparatus includes a temperature adjustment unit suitable for adjusting a temperature of a memory cell, and a temperature control unit suitable for sensing a temperature of the temperature adjustment unit, comparing a sensed temperature with... Agent: Sk Hynix Inc.

20150109858 - Memory device and column decoder for reducing capacitive coupling effect on adjacent memory cells: A memory device includes a memory cell array and a column decoder. The memory cell array includes a plurality of even local bit lines and a plurality of odd local bit lines. The column decoder includes a plurality of even pass transistors and a plurality of odd pass transistors. Each... Agent: Winbond Electronics Corp.

20150109859 - Electronic device with solid state drive and associated control method: An electronic device with a solid state drive and associated control method are provided. The electronic device includes: a host; a power supply component, for providing electric power to the host and the solid state drive; and the solid state drive including a control unit electrically connected to the host... Agent: Lite-on It Corporation

20150109860 - Semiconductor memory having volatile and multi-bit non-volatile functionality and method of operating: A semiconductor memory cell, semiconductor memory devices comprising a plurality of the semiconductor memory cells, and methods of using the semiconductor memory cell and devices are described. A semiconductor memory cell includes a substrate having a first conductivity type; a first region embedded in the substrate at a first location... Agent:

20150109861 - Secure memory which reduces degradation of data: A method for managing a non-volatile memory may include a first phase of writing data to a first bank of a memory plane of the non-volatile memory, and then a second phase of writing the same data to a second bank of the same memory plane of the non-volatile memory... Agent:

20150109862 - Nonvolatile semiconductor memory device: A nonvolatile semiconductor memory device includes first and second word line groups, each including a plurality of stacked word lines above a substrate, a first memory string including a first memory column through the first word line group, a second memory column through the second word line group, and a... Agent:

20150109863 - Semiconductor memory device for storing multivalued data: Data storage circuits are connected to the bit lines in a one-to-one correspondence. A write circuit writes the data on a first page into a plurality of 5 first memory cells selected simultaneously by a word line. Thereafter, the write circuit writes the data on a second page into the... Agent: Kabushiki Kaisha Toshiba

20150109864 - Integrated circuit and method for manufacturing and operating the same: An integrated circuit and methods for manufacturing and operating the same are provided. The integrated circuit comprises a fork architecture and a first conductive structure. The fork architecture comprises a handle portion and prong portions extending from the handle portion. The fork architecture comprises a stacked structure and a dielectric... Agent: Macronix International Co., Ltd.

20150109866 - Data paths using a first signal to capture data and a second signal to output data and methods for providing data: Data paths, memories, and methods for providing data from memory are disclosed. An example read data path includes a delay path, and a clocked data register. The data path has a data propagation delay and is configured to receive data and propagate the data therethrough. The delay path is configured... Agent:

20150109865 - High frequency pseudo dual port memory: A pseudo dual port (PDP) memory is disclosed having a write driver that selectively precharges only one of a bit line and a complement bit line in a bit line pair responsive to a bit value to be written into an accessed bitcell while discharging a remaining one of the... Agent: Qualcomm Incorporated

20150109867 - Leakage measurement systems: Described examples include leakage measurement systems and methods for measuring leakage current between a word line at a boosted voltage and a word line at a supply voltage. The boosted voltage may be generated by charge pump circuitry. Examples of leakage measurement systems described herein may be included in memory... Agent:

20150109868 - Nonvolatile semiconductor memory device: A nonvolatile semiconductor memory device according to the embodiment includes a memory cell array including memory cells; and a data write unit, the memory cells including a first selected memory cell defined for a memory cell targeted to data write, a second selected memory cell defined for a memory cell... Agent: Kabushiki Kaisha Toshiba

20150109869 - Memory with termination circuit: Provided is a semiconductor integrated circuit according to an exemplary aspect of the present invention including first and second transmitter-receivers that execute transmission and reception of data through a signal line. The first transmitter-receiver includes a first termination circuit that includes a first resistor and a first switch, the first... Agent: Renesas Electronics Corporation

20150109870 - Arithmetic processing unit and driving method thereof: An arithmetic processing unit including an SRAM with low power consumption and performing backup and recovery operation with no burden on circuits. One embodiment is a memory device including a plurality of memory cells. The memory cells include inverters in which capacitors for backing up data are provided. When data... Agent:

20150109872 - Device performing refresh operations of memory areas: Disclosed heroin is a device that includes a plurality of memory circuits and a refresh control circuit configured to generate a plurality of refresh initiation signals such that one of the refresh initiation signals takes an active level. Each of the memory circuits comprises a memory cell array including a... Agent: Ps4 Luxco S.a.r.i.

20150109871 - Row hammer monitoring based on stored row hammer threshold value: Detection logic of a memory subsystem obtains a threshold for a memory device that indicates a number of accesses within a time window that causes risk of data corruption on a physically adjacent row. The detection logic obtains the threshold from a register that stores configuration information for the memory... Agent:

20150109873 - Regulated power gating for growable memory: A circuit for an integrated circuit power gating system includes a header device connected to a bank of a segmented memory array. The circuit is structured and arranged to: apply a ground input to a gate of the header device to activate the bank, and apply a regulated voltage to... Agent: International Business Machines Corporation

20150109874 - Implementing memory device with sub-bank architecture: A method, system and memory controller are provided for implementing memory devices with sub-bank architecture in a computer system. An array is divided into sub-blocks having odd bit lines and even bit lines. The sub-blocks are alternated with rows of sense amplifiers; wherein a particular row of sense amplifiers connects... Agent: International Business Machines Corporation

20150109875 - Semiconductor memory device: A semiconductor memory device includes a memory cell array, a word line decoder, a time determination signal generation circuit, and a timing circuit. The memory cell array is configured to include a plurality of memory cells, and the word line decoder is configured to control selection and a voltage level... Agent:

  
04/16/2015 > 38 patent applications in 27 patent subcategories.

20150103576 - Memory arrangement: Among other things, techniques and systems are provided for activating a memory cell of a memory arrangement in preparation for at least one of a read operation or write operation. The memory arrangement comprises a word-line driver comprising at least a first input terminal and a second input terminal. The... Agent: Taiwan Semiconductor Manufacturing Company Limited

20150103577 - Semiconductor memory with sense amplifier: In an exemplary aspect, the present invention provides a semiconductor memory device including sense amplifiers that drive bit lines to which memory cells are connected, and driver transistors that supply a power supply to the sense amplifiers, wherein the sense amplifiers are arranged in rows and constitutes a first sense-amplifier... Agent:

20150103578 - Systems with memory segmentation and systems with biasing lines to receive same voltages during accessing: Memory devices, memory arrays, and methods of operation of memory arrays with segmentation. Segmentation elements can scale with the memory cells, and may be uni-directional or bi-directional diodes. Biasing lines in the array allow biasing of selected and unselected select devices and segmentation elements with any desired bias, and may... Agent: Micron Technology, Inc.

20150103579 - Memory device, writing method, and reading method: A memory device includes a memory cell which has one cell selection section and a storage section which is connected in series with respect to the cell selection section and which is selected as an access target for writing or reading by the cell selection section, in which the storage... Agent:

20150103580 - Data holding device and logic operation circuit using the same: A data holding device includes a loop structure unit configured to hold data using a plurality of logic gates connected in a loop shape, a nonvolatile storage unit including a plurality of ferroelectric elements, the nonvolatile storage unit configured to store the data held in the loop structure unit in... Agent:

20150103581 - Memory device, method of controlling memory device, and memory system: A memory device according to an embodiment comprises a data processing circuit that includes: a data write pre-processing circuit that processes input data to generate first intermediate data; a data write processing circuit that sequentially sets a voltage difference between a selected row line and a selected global bit line... Agent: Kabushiki Kaisha Toshiba

20150103582 - Semiconductor memory device: This semiconductor memory device comprises a memory cell array that includes: a plurality of first lines; a plurality of second lines intersecting the plurality of first lines; a plurality of memory cells each disposed at an intersection of the plurality of first lines and the plurality of second lines and... Agent: Kabushiki Kaisha Toshiba

20150103583 - Variable resistance element, semiconductor device having variable resistance element, semiconductor device manufacturing method, and programming method using variable resistance element: This variable resistance element is provided with a variable resistance film, a first electrode, which is disposed in contact with one surface of the variable resistance film, and a second electrode, which is disposed in contact with the other surface of the variable resistance film. The first and the second... Agent: Nec Corporation

20150103584 - Configurable delay circuit and method of clock buffering: A configurable delay circuit and a method of clock buffering. One embodiment of the configurable delay circuit includes: (1) a first delay stage electrically couplable in series to a second delay stage, the first delay stage and the second delay stage each having an input port electrically coupled to a... Agent: Nvidia Corporation

20150103585 - High stability static random access memory cell: A Static Random Access Memory (SRAM) cell is a latch circuit formed with two inverters each formed with a PMOS transistor and an NMOS transistor. The latch circuit is coupled to a capacitor through a switch. When the switch is switched on, the stability of data stored in the SRAM... Agent: United Microelectronics Corp.

20150103587 - Electronic device and method for driving the same: In an electronic device including a semiconductor memory, the semiconductor memory may include a unit storage cell including a variable resistor having a resistance value that is changed according to current flowing through both terminals of the variable resistor and a selection element that is electrically coupled to one terminal... Agent:

20150103586 - Write driver and program driver for otp (one-time programmable) memory with magnetic tunneling junction cells: A one-time programmable (OTP) memory having a plurality of cells, each cell having a magnetic tunnel junction (MTJ) device; and the OTP memory further including a write driver to drive each MTJ device to an anti-parallel state, and a program driver to drive a subset of the MTJ devices to... Agent: Qualcomm Incorporated

20150103590 - Memories and methods of operating memories having memory cells sharing a resistance variable material: Memories and methods of operating memories having memory cells sharing a resistance variable material.... Agent: Micron Technology, Inc.

20150103589 - Resistive memory apparatus, operation method thereof, and system having the same: A resistive memory apparatus includes a memory cell array including a plurality of resistive memory cells, an address decoder suitable for decoding an address signal, and accessing the memory cell array, a read/write control circuit suitable for programming data in the memory cell array or reading out data from the... Agent: Sk Hynix Inc.

20150103588 - Variable resistance memory apparatus, manufacturing method thereof: A variable resistance memory apparatus and a method of manufacturing the same are provided. The variable resistance memory apparatus includes a plurality of memory cells. Each of the memory cells includes a plurality of data storage regions. The plurality of data storage regions have different widths from each other.... Agent: Sk Hynix Inc.

20150103591 - Semiconductor memory with integrated biologic element: A memory includes cytokines, such as macromolecule proteins, as a poly-state data storage. Each fold state of multiple fold states of a protein are associated with a data value. Current flow through the protein is associated with a resistance of the protein associated with its current fold state. Application of... Agent: Toshiba America Electronic Components, Inc.

20150103594 - Inter-cell interference cancellation: A read module reads memory cells along a first word line by applying a plurality of threshold voltages to the first word line; generates first information about a first memory cell located along the first word line and a first bit line indicating a location of a threshold voltage distribution... Agent:

20150103593 - Method of writing data in non-volatile memory and non-volatile storage device using the same: A method of writing data in a non-volatile memory includes writing data from a first memory unit to a second memory unit of the non-volatile memory; checking a health of the second memory unit to generate a health result; and reserving the data in the first memory unit and mapping... Agent: Skymedi Corporation

20150103592 - Programming time improvement for non-volatile memory: Disclosed herein are techniques for providing a programming voltage to a selected word line in a non-volatile memory array. This may be a 3D NAND, 2D NAND, or another type of memory array. The programming voltage may be quickly ramped up on the selected word line, without the need for... Agent:

20150103595 - Bit line and compare voltage modulation for sensing nonvolatile storage elements: In a block of non-volatile memory, bit line current increases with bit line voltage. For current sensing memory systems, average bit line current during a sensing operation need only exceed a certain threshold amount in order to produce a correct result. For the first word lines being programmed in a... Agent: Sandisk Technologies, Inc.

20150103596 - Coding method and decoding method in memory system: Provided are a coding/decoding method for use in a multi-level memory system. The coding method includes searching for a set of symbols that may generate a forbidden pattern that is set initially from an input data stream, and sticking at least one bit included in the searched set of the... Agent:

20150103597 - Nonvolatile memory device, nonvolatile memory system including nonvolatile memory device and operating method of nonvolatile memory system: An method of operating a memory system including a plurality of memory cells includes changing an operation mode at least some of the memory cells which operate based on a first operation mode to operate based on a second operation mode; and performing a change erase operation on the memory... Agent:

20150103598 - Protection against side-channel attacks on non-volatile memory: A non-volatile memory (NVM) device includes an NVM array, which is configured to store data, and control logic. The control logic is configured to receive data values for storage in the NVM array, and to write at least some of the received data values to the NVM array and simultaneously... Agent:

20150103599 - Method of operating memory device assuring reliability and memory system: A method of operating a memory device to guarantee program reliability and a memory system using the same are provided. The method includes backing up data stored in the memory cells connected to a first word line, performing a dummy program operation on memory cells connected to a second word... Agent:

20150103600 - Nonvolatile semiconductor memory device: A non-volatile memory device, comprising: a substrate; a plurality of string stacks disposed over the substrate, each string stack comprising a long axis and a short axis in a plane parallel to the substrate, the long axis extending along a y-direction and the short axis extending along an x-direction, each... Agent:

20150103601 - Multi-pass soft programming: Disclosed herein are system, method and computer program product embodiments for utilizing soft programming a nonvolatile memory. An embodiment operates by sequentially applying a single soft programming voltage pulse to all memory cells along each word line in the nonvolatile memory that fail soft programming verification in a first phase.... Agent: Spansion LLC

20150103602 - Sector-based regulation of program voltages for non-volatile memory (nvm) systems: Methods and systems are disclosed for sector-based regulation of program voltages for non-volatile memory (NVM) systems. The disclosed embodiments regulate program voltages for NVM cells based upon feedback signals generated from sector return voltages that are associated with program voltage drivers that are driving program voltages to NVM cells within... Agent:

20150103603 - Methods for erasing, reading and programming flash memories: The present invention relates to semiconductor technology, and provides methods for erasing, reading and programming a flash memory. In the present invention, when an erase operation is performed on the flash memory, for a sector selected for the erase operation, its N-type well is applied with a voltage of 8V˜12V,... Agent:

20150103605 - Dram sense amplifier that supports low memory-cell capacitance: The disclosed embodiments provide a sense amplifier for a dynamic random-access memory (DRAM). This sense amplifier includes a bit line to be coupled to a cell to be sensed in the DRAM, and a complement bit line which carries a complement of a signal on the bit line. The sense... Agent: Rambus Inc.

20150103604 - Memory array architectures having memory cells with shared write assist circuitry: A memory device includes a memory array having a plurality of memory cells each having first and second power supply nodes, first and second virtual power supply nodes, a latch circuit, and a write assist circuit. The latch circuit includes a first and second inverters in a cross-coupled inverter configuration.... Agent: Lsi Corporation

20150103606 - Semiconductor device: A semiconductor device includes a data output circuit suitable for transferring an output data to an external data line during a data output operation, and a controller suitable for generating control signals for controlling the data output circuit during the data output operation, wherein the data output circuit senses a... Agent: Sk Hynix Inc.

20150103607 - Driver circuit: A method of operation in a memory controller includes operating pull-up and pull-down drivers driven by separate pre-drivers between different voltage rails. Data signals driving the pull-up driver and the pull-down driver are synchronized, and the pull-up driver and the pull-down driver are coupled together to produce an output signal... Agent:

20150103608 - Semiconductor device and information processing system including the same: A device including input and output nodes, first and second input circuits coupled in parallel to each other between the input and output nodes. The first input circuit includes a first circuit unit coupled between the input and output nodes, the first circuit unit is configured to be activated when... Agent:

20150103609 - Semiconductor devices: A semiconductor device including a control signal generator and an internal refresh signal generator is provided. The control signal generator generates first and second control signals, one of which is selectively enabled in response to temperature code signals and mode set signals after a pulse of an internal refresh signal... Agent: Sk Hynix Inc.

20150103610 - Protocol for memory power-mode control: In one embodiment, a memory device includes a memory core and input receivers to receive commands and data. The memory device also includes a register to store a value that indicates whether a subset of the input receivers are powered down in response to a control signal. A memory controller... Agent:

20150103611 - Method for driving arithmetic processing unit: In a memory cell including an inverter, a capacitor is provided. When the memory cell is not accessed, data stored in the memory cell is copied to the capacitor and then power supply to the inverter is stopped. When the memory cell needs to be accessed, the data is returned... Agent:

20150103612 - Semiconductor device: Disclosed is a semiconductor device which is intended to reduce the total number of storage element blocks that constitute a desired logic circuit. The semiconductor device includes N address lines (N is an integer equal to two or more), N data lines, and a plurality of storage sections. Each of... Agent: Taiyo Yuden Co., Ltd.

20150103613 - Memory devices and methods of operating the same: The present disclosure includes memory devices and methods of operating the same. One such device includes an array of groups of memory cells, a group selector configured to select a particular group of memory cells from within the array, and a cell selector configured to select a particular memory cell... Agent: Micron Technology, Inc.

  
04/09/2015 > 38 patent applications in 28 patent subcategories.

20150098260 - Semiconductor memory device having main word lines and sub-word lines: A plurality of memory mats classified into groups selected by bits of a row address, a main word driver for selecting a main word line based on bits of the row address, an FX driver for selecting a word driver selecting line based on bits regardless of the bits of... Agent:

20150098261 - Nonvolatile semiconductor memory device: A nonvolatile semiconductor memory device comprises: a memory cell array including first interconnections, second interconnections intersecting the first interconnections, and memory cells having a variable resistance element and being provided at respective intersections of the first interconnections and the second interconnections, the memory cell array being divided into bays including... Agent: Kabushiki Kaisha Toshiba

20150098262 - Semiconductor memory device having ray detector, and electronic device including the same, and operating method thereof: A semiconductor memory device includes a first memory region, a second memory region suitable for storing the same data as the first memory region, and a ray detection circuit suitable for detecting an incident ray to the first memory region, wherein a data stored in the second memory region is... Agent: Sk Hynix Inc.

20150098263 - Ferroelectric memory device: A ferroelectric memory device includes a memory array including a plurality of ferroelectric memory cells, a code generating circuit configured to multiply write data and a parity generator matrix to generate check bits, thereby producing a Hamming code having information bits and the check bits arranged therein, the information bits... Agent:

20150098265 - Nonvolatile semiconductor memory device: A nonvolatile semiconductor memory device according to an embodiment includes a control circuit configured to cause data to be stored in a memory cell by setting the memory cell to be included in one of resistance value distributions. The control circuit is configured to set a first resistance value distribution... Agent: Kabushiki Kaisha Toshiba

20150098264 - Resistive memory apparatus, operating method thereof, and system having the same: A resistive memory apparatus includes a memory unit including a resistive memory cell array, a voltage generation unit suitable for receiving a radio frequency (RF) signal, and converting the RF signal into a direct current (DC) voltage, and a control unit suitable for controlling a refresh operation to be performed... Agent: Sk Hynix Inc.

20150098266 - Mechanisms for preventing leakage currents in memory cells: Memory cells and operation methods thereof are provided. A memory device includes a number of memory cells. Each of the memory cells includes a first transistor, a switch and a capacitor. The first transistor has a drain connected to a corresponding bit-line. The switch has a first terminal connected to... Agent: Taiwan Semiconductor Manufacturing Co., Ltd.

20150098267 - Method and circuit to enable wide supply voltage difference in multi-supply memory: A method and apparatus for operating a memory device with wider difference in array and periphery voltage is presented. The memory device includes a bit line, a complementary bit line, a memory cell, a first pre-charge circuit, and a second pre-charge circuit. The memory cell, the first pre-charge circuit, and... Agent: Stmicroelectronics International N.v.

20150098268 - Semiconductor memory: The disclosed invention provides an SRAM capable of stably generating a PUF-ID without having to be powered on/off under control. The SRAM including a plurality of write ports is provided with a plurality of word lines, each transferring write data from each of the write ports to one memory cell.... Agent:

20150098269 - Read distribution management for phase change memory: Subject matter disclosed herein relates to a memory device, and more particularly to write performance of a phase change memory.... Agent:

20150098270 - System and method of programming a memory cell: An apparatus includes a semiconductor transistor structure. The semiconductor transistor structure includes dielectric material, a channel region, a gate, a source overlap region, and a drain overlap region. The source overlap region is biasable to cause a first voltage difference between the source overlap region and the gate to exceed... Agent:

20150098273 - Non-volatile semiconductor memory device capable of improving failure-relief efficiency: According to one embodiment, a non-volatile semiconductor memory device includes a memory cell array and a row decoder. The memory cell array has NAND strings as a physical block, and word lines respectively connected to memory cells included in the NAND strings. The row decoder includes latch circuits and a... Agent: Kabushiki Kaisha Toshiba

20150098272 - Programmable peak-current control in non-volatile memory devices: A method includes, in a memory device, receiving a command that specifies a peak power consumption that is not to be exceeded by the memory device. A memory of the memory device is configured in accordance with the peak power consumption specified in the command. A data storage operation in... Agent:

20150098271 - System and method of storing data in a data storage device: A method that may be performed in a data storage device includes selecting a writing order for data to be written to a set of word lines of a block of a non-volatile memory. The data is organized in pages that are ordered according to a logical page address order.... Agent: Sandisk Technologies Inc.

20150098274 - Cell array with a manufacturable select gate for a nonvolatile semiconductor memory device: A three-dimensional integrated circuit non-volatile memory array includes a memory array with first and second NAND memory cell string stacks having opposite orientations, where each NAND memory cell string includes a plurality of transistors and a source line contact connected in series between a bit line and string extension region... Agent: ConversantIPManagement Inc.

20150098275 - Flash memory based on storage devices and methods of operation: A method transfers read data from a flash memory to a controller synchronously with respect to a data strobe signal during a read data transfer period. During an initial control period of the read data transfer period, the cycle of the data strobe signal is expanded such that a pulse... Agent:

20150098276 - Memory and sense parameter determination methods: Memory devices and methods for operating a memory include filtering a histogram of sensed data of the memory, and adjusting a parameter used to sense the memory using the filtered histogram. Filtering can be accomplished by averaging or summing, and may include weighting the sums or averages.... Agent: Micron Technology, Inc.

20150098277 - Data strobe generation: In an embodiment, a method of generating strobe signals includes generating a first strobe signal in a first mode by operating a multiplexer with a clock signal to select between a first input signal and a second input signal, the first input signal having a static first signal level and... Agent: Cavium, Inc.

20150098278 - Non-volatile memory apparatus and data verification method thereof: A non-volatile memory apparatus and a data verification method thereof are provided. The non-volatile memory apparatus includes a plurality of memory cells, a page buffer, a write circuit, a sense amplifier, and a sense and compare circuit. The page buffer stores a plurality of buffered data and programs the plurality... Agent: Ememory Technology Inc.

20150098279 - Sensing amplifier and sensing method thereof: A sensing amplifier comprising a clamp circuit is provided. The clamp circuit is coupled between a first node and a second node. The clamp circuit comprises a first P-type transistor having a first terminal, a second terminal and a control terminal receiving a first bias signal, the first terminal and... Agent: Macronix International Co., Ltd.

20150098280 - Tracking bit cell: A method includes determining a plurality of first current values of a first current to be sunk by a tracking cell of a tracking circuit in response to a plurality of first voltage values of a first voltage applied to the tracking cell. Each first current value of the plurality... Agent:

20150098281 - Semiconductor chip and semiconductor integrated circuit including the same: A semiconductor chip includes an internal voltage generation circuit suitable for generating an internal voltage having a predetermined level, a target internal circuit suitable for performing a predetermined operation using the internal voltage, and a control circuit suitable for checking operating speed of the target internal circuit based on an... Agent: Sk Hynix Inc.

20150098283 - Semiconductor device and semiconductor system including the same: A semiconductor device includes a pipe latch suitable for sequentially latching data in response to a pipe input control signal and sequentially outputting data in response to a pipe output control signal, a pipe latch control unit suitable for generating the pipe input/output control signals in response to a command... Agent: Sk Hynix Inc.

20150098284 - Semiconductor memory device and memory system including the same: A semiconductor memory device may include: a memory cell array; a first address controller configured to receive a first command and a first address and generate a first control signal in response to the first command; and a second address controller configured to receive a second address and a second... Agent:

20150098282 - Semiconductor memory device and semiconductor system including the same: Disclosed herein is a semiconductor memory device using a pre-fetch method and a semiconductor system including the same. The semiconductor memory device may include a memory bank having an odd-numbered array region suitable for inputting/outputting data through N first local lines in response to an odd-numbered column address, and an... Agent: Sk Hynix Inc.

20150098285 - On-die termination apparatuses and methods: Apparatuses and methods are disclosed herein, including those, performed by a memory die, that operate to detect that a command on a bus connected to the memory die is addressed to another memory die responsive to a chip select signal, and to change the impedance of an on-die termination circuit... Agent: Micron Technology, Inc.

20150098287 - Memory device and operation method of memory device and memory system: An operation method of a memory device includes entering a repair mode, changing an input path of setting data from a set path to a repair path in response to the entering of the repair mode, receiving the setting data together with a setting command, ending the repair mode after... Agent: Sk Hynix Inc.

20150098286 - Semiconductor memory device: A semiconductor memory device includes: a memory cell array region having a plurality of normal cell lines and a plurality of repair cell lines; a plurality of normal cell line selection units suitable for selecting the plurality of normal cell lines, respectively, in response to a local address; a plurality... Agent: Sk Hynix Inc.

20150098288 - Electronic device including semiconductor memory and operation method of the same: An electronic device includes a semiconductor memory. The semiconductor memory includes a cell array including first to Nth word lines, where the N is an integer equal to or larger than 2, first to Nth memory sets respectively corresponding to the first to Nth word lines, and an activation number... Agent: Sk Hynix Inc.

20150098289 - Semiconductor device: A semiconductor device includes a plurality of memory cells, an access circuit configured to perform a data read operation, a data write operation and a data refresh operation on the memory cells, the access circuit to operate in a selected one of a first mode that is ready to perform... Agent:

20150098290 - Methods circuits apparatuses and systems for providing current to a non-volatile memory array and non-volatile memory devices produced accordingly: Disclosed are methods, circuits, apparatuses and systems for providing power to a dynamic load such as a non-volatile memory array. According to embodiments, a voltage source may be adapted to generate and output a supply current at substantially a target voltage through a regulating transistor whose channel is in series... Agent: Spansion LLC

20150098291 - Power consumption control: The present disclosure includes apparatuses and methods for power consumption control. A number of embodiments include determining power consumption information for each phase in a combination of phases of a command, and authorizing execution of at least one of the phases in the combination based, at least partially, on the... Agent:

20150098292 - Methods and systems for addressing memory with variable density: Embodiments relate to systems and methods for simplified addressing of a memory device whose total memory capacity is extendible by an additional memory capacity or a factor to a total extended memory capacity, the method comprising dividing the additional memory capacity into a set of binary memory fractions of the... Agent:

20150098293 - Semiconductor integrated circuit: A semiconductor integrated circuit includes a plurality of semiconductor chips. Each of the plurality of semiconductor chips includes a chip selection unit suitable for generating an internal chip selection signal in response to one or more selective chip selection signals and transferring the selective chip selection signals to an adjacent... Agent: Sk Hynix Inc.

20150098294 - Counter circuit and semiconductor device including the same: A counter circuit includes a lower count signal generation unit suitable for generating a lower bit, an upper count signal generation unit suitable for generating an upper bit, and a control unit suitable for determining a counting route in response to a control signal and controlling the lower and upper... Agent: Sk Hynix Inc.

20150098295 - Apparatuses and methods including selectively providing a single or separate chip select signals: Apparatus and methods are disclosed herein, including those that operate to initialize registers of a first memory device and a second memory device of a single-rank memory module by providing separate chip select signals to separately select a first memory device and a second memory device. A method may further... Agent: Micron Technology, Inc.

20150098296 - Semiconductor device and semiconductor system with the same: A semiconductor device includes a first internal clock generation unit suitable for generating a first internal clock for synchronizing a first signal in response to a first external clock; a second internal clock generation unit suitable for generating a second internal clock for synchronizing a second signal in response to... Agent: Sk Hynix Inc.

20150098297 - Timing-drift calibration: The disclosed embodiments relate to components of a memory system that support timing-drift calibration. In specific embodiments, this memory system contains a memory device (or multiple devices) which includes a clock distribution circuit and an oscillator circuit which can generate a frequency, wherein a change in the frequency is indicative... Agent:

  
04/02/2015 > 43 patent applications in 23 patent subcategories.

20150092468 - Nonvolatile semiconductor memory device: This nonvolatile semiconductor memory device comprises a memory cell array configured having a plurality of memory mats arranged therein, each of the memory mats having a memory cell disposed therein at an intersection of a first line and a second line, the memory cell including a first variable resistance element.... Agent: Kabushiki Kaisha Toshiba

20150092470 - Configurable reference current generation for non volatile memory: This disclosure relates to generating a reference current for a memory device. In one aspect, a non-volatile memory device, such as a phase change memory device, can determine a value of a data digit, such as a bit, stored in a non-volatile memory cell based at least partly on the... Agent: Micron Technology, Inc.

20150092472 - Electronic devices having semiconductor memories: Provided is an electronic device including a semiconductor memory which includes a cell array region having a first variable resistance element and a peripheral circuit region having a decoupling capacitor, the decoupling capacitor including a bottom electrode, a dielectric layer pattern, and a top electrode. The cell array region may... Agent: Sk Hynix Inc.

20150092471 - Memory cells breakdown protection: A method is disclosed that includes the operations outlined below. A first voltage is applied to a gate of an access transistor of each of a row of memory cells during a reset operation, wherein a first source/drain of the access transistor is electrically connected to a first electrode of... Agent: Taiwan Semiconductor Manufacturing Co., Ltd.

20150092474 - Resistive memory device, method of fabricating the same, and memory apparatus and data processing system having the same: A resistive memory device capable of implementing a multi-level cell, a method of fabricating the same, and a memory apparatus and data processing system including the same are provided. The resistive memory device includes a lower electrode, a first phase-change material layer formed over the lower electrode, a second phase-change... Agent: Sk Hynix Inc.

20150092473 - Semiconductor memory device: A semiconductor memory device according to an embodiment includes: a memory cell array including a plurality of first lines, a plurality of second lines, and memory cells disposed at each of intersections of the first lines and the second lines; and a control circuit configured to apply a first voltage... Agent: Kabushiki Kaisha Toshiba

20150092469 - System and method to trim reference levels in a resistive memory: A system and method to trim reference levels in a resistive memory is disclosed. In a particular embodiment, a resistive memory includes multiple sets of reference cells. The resistive memory also includes a reference resistance measurement circuit. A first set of reference cells is accessible by the reference resistance measurement... Agent:

20150092477 - Adaptive data-retention-voltage regulating system for sram: An adaptive data-retention-voltage regulating system for static random-access memory (SRAMs) is revealed. The system includes a power supply unit, a data-retention-voltage (DRV) monitor cell for monitoring static noise margin (SNM) of SRAM, a data loss detector for generating a data loss signal, and a dynamic regulating controller that receives the... Agent:

20150092476 - Dual port sram with dummy read recovery: An integrated includes a dual port memory cell such as a SRAM cell. A first port dummy read recovery block couples the first port complementary bit line to a high voltage supply node during a write logic low operation to the data node through the second port bit line, and... Agent: Taiwan Semiconductor Manufacturing Co., Ltd.

20150092475 - Pseudo retention till access mode enabled memory: A memory configurable to be used in an RTA mode includes an input latch configured to receive an input address bus and to generate a latched address bus that corresponds to a memory location. An address flop is configured to save the latched address and to generate a flopped address.... Agent: Texas Instruments Incorporated

20150092478 - Distributed current clock for nano-magnetic element array: A nano-magnetic element array having a conductive line adjacent to a group of nano-magnetic elements and a multi-level current driver connected to an input node on the conductive line. The current driver is controlled by a pair of voltage clock signals and a voltage reference so as to selectively change... Agent: International Business Machines Corporation

20150092481 - Electronic device and method for fabricating the same: An electronic device includes a semiconductor memory, wherein the semiconductor memory includes: a variable resistance element having a stacked structure of a first magnetic layer, a tunnel barrier layer, and a second magnetic layer; and a protection layer including a pillar-shaped magnetic compensation layer and a non-magnetic layer, which are... Agent:

20150092480 - Electronic device and method of fabricating the same: An electronic device includes a semiconductor memory, wherein the semiconductor memory includes: a seed layer including conductive hafnium silicate; a first magnetic layer formed over the seed layer; a tunnel barrier layer formed over the first magnetic layer; and a second magnetic layer formed over the tunnel barrier layer.... Agent: Sk Hynix Inc.

20150092479 - Resistance-based memory cells with multiple source lines: In a particular embodiment, a device includes a resistance-based memory cell having multiple source lines and multiple access transistors. A coupling configuration of the multiple access transistors to multiple source lines encodes a data value.... Agent: Qualcomm Incorporated

20150092482 - Electronic device and method of fabricating the same: An electronic device includes a semiconductor memory, wherein the semiconductor memory includes a variable resistance element formed over a substrate, and a multi-layer passivation layer positioned over sidewalls of the variable resistance element and having two or more insulating layers formed over the sidewalls of the variable resistance element.... Agent: Sk Hynix Inc.

20150092483 - Modified reset state for enhanced read margin of phase change memory: Subject matter disclosed herein relates to techniques involving a structural relaxation (SR) phenomenon for increasing resistance of a Reset state of phase change memory.... Agent:

20150092484 - Semiconductor integrated circuit: A plurality of memory blocks; and a control block configured to independently operate a part of the plurality of memory banks as a first sub-channel and a remainder of the plurality of memory banks as a second sub-channel according to whether a sub-channel is set.... Agent: Sk Hynix Inc.

20150092486 - Dual-port semiconductor memory and first in first out (fifo) memory having electrically floating body transistor: Multi-port semiconductor memory cells including a common floating body region configured to be charged to a level indicative of a memory state of the memory cell. The multi-port semiconductor memory cells include a plurality of gates and conductive regions interfacing with said floating body region. Arrays of memory cells and... Agent:

20150092485 - Two transistor ternary random access memory: A two transistor ternary random access memory (TTTRAM) circuit includes an voltage/current input, an input/output switch, a first transistor, a first pull up resistor, a second transistor, and a second pull up resistor. The first transistor has a first emitter, a first collector connected to the input/output switch, and a... Agent:

20150092489 - Flash memory reference voltage detection with tracking of cross-points of cell voltage distributions using histograms: Cross-points of flash memory cell voltage distributions are determined by reading data from a portion of the flash memory two or more times using two or more different candidate reference voltages and determining corresponding decision patterns. The frequency of occurrence of the decision patterns in the data read from the... Agent: Lsi Corporation

20150092488 - Flash memory system endurance improvement using temperature based nand settings: Methods and apparatus to improve flash memory system endurance using temperature based flash memory settings are described. In one embodiment, memory controller logic applies one of a first trim profile or a second trim profile to a flash memory storage device based at least partially on a comparison of a... Agent:

20150092487 - Solving mlc nand paired page program using reduced spatial redundancy: Reduced spatial redundancy of lower bits data can provide data protection for a flash memory having MLC NAND devices operated in page mode. An interrupted write operation of most significant bit pages can corrupt previously written data in lower bit pages. The lower bits redundant memory can assist in restoring... Agent: Virtium Technology, Inc.

20150092490 - Semiconductor device: The present invention has an object of providing a high-speed, low-cost, and user-friendly information processing system that can ensure scalability of memory capacity. The information processing system is configured to include an information processing device, a volatile memory, and a nonvolatile memory. By serially connecting the information processing device, the... Agent:

20150092493 - Pseudo block operation mode in 3d nand: A 3D NAND stacked non-volatile memory device, comprising: a string comprising a plurality of non-volatile storage elements, the string comprises a channel and extends vertically through layers of the 3D stacked non-volatile memory device, and the plurality of storage elements are subdivided into different groups based on group assignments, each... Agent: Sandisk Technologies Inc.

20150092492 - Semiconductor device and method of searching for erasure count in semiconductor memory: In response to a search start instruction, a read address signal including address sequences for blocks is generated and the read address signal is provided to a block management memory to successively read sequences of erasure count data pieces corresponding to the blocks from the block management memory. Thereafter, when... Agent: Lapis Semiconductor Co., Ltd.

20150092491 - Semiconductor memory device and erasing method: A reliable semiconductor memory device and an erasing method for erasing data in a reliable manner are provided. The erasing method is applied to erase a semiconductor memory device having a memory array, and the memory array has an NAND string. A predetermined voltage is applied to a gate of... Agent: Winbond Electronics Corp.

20150092495 - Semiconductor memory device and method of operating the same: A semiconductor memory device includes a memory cell array configured to store data; peripheral circuits configured to perform program verifying operation, read operation, and erase verifying operation on the memory cell array; and a control circuit configured to control the peripheral circuits, wherein the control circuit is configured to control... Agent: Sk Hynix Inc.

20150092494 - Vertical gate stacked nand and row decoder for erase operation: A three-dimensional integrated circuit non-volatile memory array includes a memory array with multiple vertical gate NAND memory cell strings formed in a different vertical layers over a substrate which share a common set of word lines, where different groupings of NAND memory cell strings formed between dedicated pairings of source... Agent: Mosaid Technologies Incorporated

20150092496 - Dynamic bit line bias for programming non-volatile memory: A program operation for a set of non-volatile storage elements. A count is maintained of a number of program pulses which are applied to an individual storage element in a slow programming mode, and an associated bit line voltage is adjusted based on the count. Different bit line voltages can... Agent: Sandisk Technologies Inc.

20150092497 - Bias generator for flash memory and control method thereof: A bias voltage generator for providing a control voltage and a source line voltage to a memory array includes a reference voltage generating circuit and a voltage converting circuit. The reference voltage generating circuit receives a program signal or an erase signal, and generates a reference voltage. If the program... Agent: Ememory Technology Inc.

20150092498 - Non-volatile memory for high rewrite cycles application: A non-volatile memory has an array of non-volatile memory cells. Each of the non-volatile memory cells includes a coupling device formed on a first well, a read device, a floating gate device formed on a second well and coupled to the coupling device, a program device formed on the second... Agent: Ememory Technology Inc.

20150092499 - Slew rate modulation: Apparatus and methods may operate so that arrival times of a data signal at gates of transistors are controlled to switch the transistors at different times to modulate the slew rate of a signal on a node. Additional embodiments are also described.... Agent:

20150092500 - Semiconductor memory apparatus: A semiconductor memory apparatus includes a first data storage region configured to be supplied with a driving voltage via a first voltage line, a second data storage region configured to be supplied with a driving voltage via a second voltage line and a switch configured to one of electrically couple... Agent: Sk Hynix Inc.

20150092501 - Driver for a semiconductor memory and method thereof: A driver for semiconductor memory, comprising: a storage unit configured to match and store a memory cell address and bucket charge current data corresponding to the memory cell address; a selection controller configured to receive the memory cell address and a target charge current data, and output a bucket charge... Agent:

20150092502 - Circuit to generate a sense amplifier enable signal: A circuit includes a tracking bit line, a tracking unit connected to the tracking bit line and a detection unit. The tracking unit is configured to receive a first control signal and configured to selectively charge or discharge a voltage on the tracking bit line in response to the first... Agent: Taiwan Semiconductor Manufacturing Company, Ltd.

20150092503 - Method and apparatus for memory command input and control: Memories containing command decoder, chip enable, and signal truncation circuits are disclosed. One such command decoder circuit may include command decoder logic configured to receive command signals and output a decoded command to an interconnect bus responsive to a chip select signal having an active state. Decoder circuits may also... Agent:

20150092505 - Semiconductor device including plural chips stacked to each other: A method for reading data from a plurality of DRAM devices connected to common command, address, and data busses. A clock signal is provided to the plurality of DRAM devices. A read command and address to the plurality of DRAM devices on the command and address busses in synchronization with... Agent:

20150092504 - Semiconductor devices: Semiconductor devices are provided. The semiconductor device includes a charge controller, a delay unit and a discharger. The charge controller controls an amount of electric charges on a first node to output a drive signal through the first node. The delay unit includes a capacitor coupled to the first node... Agent: Sk Hynix Inc.

20150092506 - Method and apparatus for testing memory: A method and an apparatus for testing a memory are provided, and the method is adapted for an electronic apparatus to test the memory. In the method, a left edge and a right edge of a first waveform of a clock signal for testing the memory are scanned to obtain... Agent: Wistron Corporation

20150092507 - Memory having a voltage switch circuit with one bias voltage changed in each state of conditioning: A voltage switch circuit includes four transistors. The four transistors may be transistors used to build logic gates. The operation of the voltage switch circuit may include precharging the output terminal of the voltage switch circuit, conditioning of the voltage switch circuit and boosting the voltage of the output terminal.... Agent:

20150092508 - Directed per bank refresh command: A memory device includes a per bank refresh counter applicable to multiple banks in a group. The memory device increments a row address counter only when the per bank refresh counter is reset. The memory device receives a per bank refresh command from an associated memory controller, and performs a... Agent:

20150092509 - Semiconductor apparatus and chip id generation method thereof: Provided is a semiconductor apparatus including a plurality of memory chips which are sequentially stacked. Each of the memory chips includes: a temperature sensor configured to sense the temperature of the memory chip; and a chip ID output unit configured to generate a chip ID for the memory chip based... Agent: Sk Hynix Inc.

20150092510 - Method and apparatus for amplifier offset calibration: According to at least one example embodiment, a method and corresponding system for calibrating an amplifier offset include applying an input value to both input leads of an amplifier. The amplifier includes one or more digital-to-analog converters (DACs) used to calibrate an offset of the amplifier. A digital value, provided... Agent: Cavium, Inc.

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