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Static information storage and retrieval March listing by industry category 03/13

20130077373 - Nonvolatile memory device and operation method thereof: In a method of operating a nonvolatile memory device, at least one among memory cell blocks of the nonvolatile memory device is designated as a content addressable memory (CAM) block which includes a plurality of CAM cells coupled to respective word lines of the nonvolatile memory device. Chip information for... Agent: Hynix Semiconductor Inc.

20130077374 - Stacked semiconductor apparatus, system and method of fabrication: A stacked semiconductor apparatus and method of fabricating same are disclosed. The apparatus includes upper and lower semiconductor devices having a similar pattern of connection elements. When stacked connected the resulting plurality of semiconductor devices includes a serial connection path traversing the stack, and may also include parallel connection paths,... Agent:

20130077375 - Layout for semiconductor memories: A semiconductor memory includes a first conductive layer including a first pair of bit lines coupled to a first bit cell and a second conductive layer including a second pair of bit lines coupled to the first bit cell. The first and second conductive layers are vertically separated from each... Agent: Taiwan Semiconductor Manufacturing Co., Ltd.

20130077376 - Semiconductor device with otp memory cell: A semiconductor device with OTP memory cell includes a first switching unit for transferring a first bias voltage, a first MOS transistor having a first gate coupled to a first gate signal and a first terminal coupled to the first bias voltage by the first switching unit, and a second... Agent: Sk Hynix Inc.

20130077377 - Semiconductor device with otp memory cell: A semiconductor device includes a one-time programmable (OTP) memory cell includes a first MOS transistor having a gate coupled to a bit line, a first switching device, coupled to one side of a source/drain of the first MOS transistor, configured to provide a current path for a current supplied to... Agent: Sk Hynix Inc.

20130077378 - Spin torque transfer memory cell structures and methods: Spin Torque Transfer (STT) memory cell structures and methods are described herein. One or more STT memory cell structures include a tunneling barrier material positioned between a ferromagnetic storage material and a pinned ferromagnetic material in contact with an antiferromagnetic material. The tunneling barrier material is a multiferroic material and... Agent: Micron Technology, Inc.

20130077384 - Cross point variable resistance nonvolatile memory device and method of reading thereby: A cross point variable resistance nonvolatile memory device including: a cross point memory cell array having memory cells each of which is placed at a different one of cross points of bit lines and word lines; a word line decoder circuit that selects at least one of the memory cells... Agent:

20130077381 - Highly integrated programmable non-volatile memory and manufacturing method thereof: A highly integrated programmable non-volatile memory and a manufacturing method thereof are provided. More particularly, a memory device including an antifuse and a diode, or a variable resistor and a diode, an operation method thereof, and a manufacturing method of a plurality of memory cells capable of increasing the integration... Agent:

20130077382 - Hybrid memory device, system including the same, and method of reading and writing data in the hybrid memory device: A hybrid memory device is provided. The hybrid memory device includes a DRAM, a non-volatile memory and a control circuit. The control circuit selects one of output data of the DRAM and output data of the non-volatile memory according to a mode selecting signal and output the selected data. The... Agent: Samsung Electronics Co., Ltd.

20130077380 - Nonvolatile semiconductor memory device: A nonvolatile semiconductor memory device includes a memory cell array including cells provided at each of intersections of first and second lines and each having a variable resistance element and a first diode connected in series; a first line control circuit for supplying voltages to the first lines; and a... Agent: Kabushiki Kaisha Toshiba

20130077379 - Semiconductor memory device, semiconductor device and method of manufacturing semiconductor memory device: In a case where a DRAM and a ReRAM are mounted together, a manufacturing cost thereof is reduced while maintaining performance of a capacitance element and a variable resistance element. A semiconductor memory device includes a variable resistance element and a capacitance element. The variable resistance element has a cylinder... Agent: Renesas Electronics Corporation

20130077383 - Writing circuit for a resistive memory cell arrangement and a memory cell arrangement: A writing circuit for a resistive memory cell arrangement is provided, the resistive memory cell arrangement including a plurality of resistive memory cells. The writing circuit includes a controlled voltage source including a plurality of pass transistors, wherein each pass transistor includes a first source/drain terminal, a second source/drain terminal... Agent: Agency For Science, Technology And Research

20130077385 - Semiconductor device: An object of the present invention is to provide a semiconductor device combining transistors integrating on a same substrate transistors including an oxide semiconductor in their channel formation region and transistors including non-oxide semiconductor in their channel formation region. An application of the present invention is to realize substantially non-volatile... Agent: Semiconductor Energy Laboratory Co., Ltd.

20130077386 - Semiconductor device and driving method of the same: An object is to provide a semiconductor device with a novel structure in which stored data can be held even when power is not supplied, and the number of times of writing is not limited. The semiconductor device is formed using a wide gap semiconductor and includes a potential change... Agent: Semiconductor Energy Laboratory Co., Ltd.

20130077387 - Semiconductor device: There is provided, for example, a write assist circuit for controlling the voltage level of a memory cell power supply line coupled to an SRAM memory cell to be written in the write operation. The write assist circuit reduces the voltage level of the memory cell power supply line to... Agent: Renesas Electronics Corporation

20130077388 - Magnetic memory element, magnetic memory device, spin transistor, and integrated circuit: One embodiment provides a magnetic memory element, including: a first ferromagnetic layer whose magnetization is variable; a second ferromagnetic layer which has a first band split into a valence band and a conduction band and a second band being continuous at least from the valence band to the conduction band;... Agent: Kabushiki Kaisha Toshiba

20130077390 - Magnetic random access memory (mram) cell, method for writing and reading the mram cell using a self-referenced read operation: The present disclosure concerns a magnetic random access memory (MRAM) cell comprising a magnetic tunnel junction comprising a synthetic storage layer; a sense layer having a sense magnetization that is reversible; and a tunnel barrier layer between the sense layer and the storage layer; wherein a net local magnetic stray... Agent: Crocus Technology Sa

20130077389 - Magnetic random access memory using magnetoresistive element, diode, and transistor: A magnetic memory according to an embodiment includes: a magnetoresistive element including a first magnetic layer having a magnetization direction not to be changed by spin-injection writing, a second magnetic layer having a magnetization direction to be changeable by the spin-injection writing, and a tunnel barrier layer provided between the... Agent: Kabushiki Kaisha Toshiba

20130077391 - Magnetoresistive device and a writing method for a magnetoresistive device: According to embodiments of the present invention, a magnetoresistive device is provided. The magnetoresistive device includes at least two ferromagnetic soft layers, wherein the at least two ferromagnetic soft layers have different ranges of magnetization switching frequencies. Further embodiments provide a magnetoresistive device including at least two oscillating ferromagnetic structures,... Agent: Agency For Science, Technology And Research

20130077394 - Multilevel programming of phase change memory: A method and device for performing a program operation of a phase change memory (PCM) cell. The method includes the steps of applying one or more programming pulses according to a predefined programming scheme to achieve a target resistance level of the PCM cell, wherein the programming scheme is operable... Agent: International Business Machines Corporation

20130077392 - Semiconductor integrated circuit system and method for driving the same: A semiconductor integrated circuit system includes a phase-change line including a first phase-change area constituting a first memory cell and a second phase-change area constituting a second memory cell, a write current providing unit configured to phase-change a selected one of the first and second phase-change areas, and a phase-change... Agent:

20130077393 - Timing violation handling in a synchronous interface memory: A Phase-Change Memory (PCM) that allows an Activate command to start and all following Activate commands are ignored until a time tRC has elapsed.... Agent:

20130077395 - Magnetic memory device: A magnetic memory device comprises a magnetic wire extending in a first direction, a pair of first electrodes operable to pass a current through the magnetic wire in the first direction or in an opposite direction to the first direction, a first insulating layer provided on the magnetic wire in... Agent: Kabushiki Kaisha Toshiba

20130077396 - Magnetic memory element and magnetic memory apparatus: A magnetic memory element includes a first magnetic layer, a second magnetic layer, a first intermediate layer, a first magnetic wire, a first input unit, and a first detection unit. The first magnetic layer has magnetization fixed. The second magnetic layer has magnetization which is variable. The first intermediate layer... Agent: Kabushiki Kaisha Toshiba

20130077398 - Nonvolatile semiconductor memory device and programming method: A nonvolatile semiconductor memory device of the charge trap type is initialized by reading the memory cells in the device to determine which charge traps hold less than a predetermined minimum charge and injecting charge into these charge traps until all of the charge traps in the device hold at... Agent: Lapis Semiconductor Co., Ltd.

20130077397 - Semiconductor device: A semiconductor device according to an embodiment includes: a first transistor including a gate connected to a first interconnection, a first source, and a first drain, one of the first source and the first drain being connected to a second interconnection; and a second transistor including a gate structure, a... Agent: Kabushiki Kaisha Toshiba

20130077400 - Memory device and control method of memory device: A memory card includes: a plurality of memory cells; a CPU core; and an ECC unit configured to perform soft decision decoding. If decoding based on an LLR acquired from a first LLR table fails, the memory card measures a threshold voltage distribution centered on a first HB read voltage... Agent: Kabushiki Kaisha Toshiba

20130077401 - Semiconductor memory device: A plurality of address conversion circuits are provided for memory cores respectively, and convert logical address data supplied from outside to physical address data. In an interleave operation, the address conversion circuits output the logical address data as the physical address data without converting the logical address data when a... Agent: Kabushiki Kaisha Toshiba

20130077403 - Memory and program method thereof: A method of programming a nonvolatile memory includes: applying a common program pulse to program cells within each page of a memory region including two or more pages; applying one or more different program pulses to the program cells within each page of the memory region, according to target threshold... Agent: Sk Hynix Inc.

20130077402 - Non-volatile semiconductor memory device and method of writing data therein: A non-volatile semiconductor memory device includes a plurality of cell units and a data writing unit. The cell unit includes first and second select gate transistors and a memory string including a plurality of memory cells. The data writing unit sequentially writes lower page data and upper page data corresponding... Agent: Kabushiki Kaisha Toshiba

20130077404 - Nonvolatile semiconductor memory device: A nonvolatile semiconductor memory device according to one embodiment includes: memory cells; word lines connected to the memory cells; and a control circuit configured to control a data read operation. When controlling the data read operation, the control circuit applies one of read voltages to a selected word line, applies... Agent: Kabushiki Kaisha Toshiba

20130077406 - Flash memory device: A flash memory device is provided. The flash memory device includes a memory cell array and a pre-charge unit. The pre-charge unit, coupled to a plurality of bit lines corresponding with the memory cell array, pre-charges the bit lines to a predetermined voltage during a pre-charge stage. The pre-charge unit... Agent: Grace Semiconductor Manufacturing Corporation

20130077405 - Nonvolatile semiconductor memory device: A nonvolatile semiconductor memory device in an embodiment includes a semiconductor layer, a memory cell array, word lines, bit lines, a source line, and a control circuit. The memory cell array has memory strings, each of the memory strings having memory cells. The word lines are connected to the control... Agent: Kabushiki Kaisha Toshiba

20130077399 - System, semiconductor memory device and operating method thereof: A method for operating a semiconductor memory device including a memory block constituted by first memory cells used as main memory cells and second memory cells includes reading out an erase count of the memory block stored in the second memory cells, erasing the memory block, increasing the read-out erase... Agent: Hynix Semiconductor Inc.

20130077410 - Clock synchronized non-volatile memory device: A nonvolatile memory apparatus including a control circuit, plural terminals having clock, command and other terminals, data and command registers, and plural nonvolatile memory cells. The clock terminal receives a clock signal and the command terminal receives commands including read and program commands. The data register receives from and outputs... Agent:

20130077407 - Nonvolatile memory device, program method thereof, and data processing system including the same: A program method of a nonvolatile memory device includes a pre-program verify step for verifying a threshold voltage of a selected memory cell; a step of setting a bit line voltage of the selected memory cell according to the threshold voltage of the selected memory cell which is determined through... Agent: Hynix Semiconductor Inc.

20130077408 - Nonvolatile semiconductor memory device: A nonvolatile semiconductor memory device according to the embodiment comprises a memory cell array including plural memory cells operative to store data nonvolatilely in accordance with plural different threshold voltages; and a control unit operative to, in data write to the memory cell, execute write loops having a program operation... Agent: Kabushiki Kaisha Toshiba

20130077409 - Nonvolatile semiconductor storage device: A nonvolatile semiconductor storage device according to an embodiment includes: a memory cell array including plural memory cells; and a control circuit that repeatedly performs a write loop including a program operation and a verify operation in data write performed to the memory cell, the verify operation including a preverify... Agent: Kabushiki Kaisha Toshiba

20130077411 - Dynamic switching approach to reduce area and power consumption of high voltage charge pumps: A charge pump system uses a dynamic switching approach, where the pump connections are independent of the load for each output. One large pump is designed to be shared between all of the outputs for use during the ramp up during recovery, with each output level also have one designated... Agent:

20130077412 - Row driver circuit for nand memories including a decoupling inverter: Devices and circuits for row driver architectures that can improve an existing row driver circuit including a boosting capacitor and a level shifter circuit. For example, the improvement can include a decoupling inverter that decouples the level shifter from the boosting capacitor, which can reduce the time for the row... Agent: Elpida Memory, Inc.

20130077413 - Semiconductor memory device: A flash memory 100 capable of reducing electric fields applied to the word lines on a memory array and reducing a chip area, includes a memory array 110, a word line decoder 120 disposed at an end of the memory array on the row direction, selecting a predetermined memory block... Agent:

20130077414 - Memory apparatus: A memory apparatus includes a mimic redundant device comparator, a reference delay signal generator, and a signal comparison controller. The mimic redundant device comparator is configured to receive an input signal and to delay the input signal according to a mimic delay, so as to generate a comparison signal. The... Agent: Nanya Technology Corporation

20130077415 - Circuit for memory cell recovery: An apparatus and method for combating the effects of bias temperature instability (BTI) in a memory cell. Bit lines connecting to a memory cell contain two alternate paths criss-crossing to connect a lower portion of a first bit line to an upper portion of a second bit line, and to... Agent: International Business Machines Corporation

20130077416 - Memory device and method of performing a read operation within a memory device: A memory device includes an array of memory cells arranged in rows and columns, each memory cell being configured to connect to separate write and read paths. The memory cells within each column form a plurality of memory cell groups and are coupled to the read data output circuitry by... Agent:

20130077417 - Control of inputs to a memory device: A memory device includes a command decoder and control interface logic. One or more external inputs, such as row and column address strobes, communicate with the command decoder through the control interface logic. A control signal is also in communication with the control interface logic. During operation of a drowsy... Agent: Micron Technology, Inc.

20130077418 - Dll circuit, frequency-multiplication circuit, and semiconductor memory device: According to one embodiment, there is provided a DLL circuit including a delay chain, a plurality of phase comparators, and a controller. The plurality of phase comparators receive the reference clocks individually and receive respectively the clocks from the delay elements in mutually different stages, among the delay elements of... Agent: Kabushiki Kaisha Toshiba

20130077419 - Data generation apparatus: An apparatus according to an embodiment comprises a first storage, a second storage, an input unit, a shift number determining unit, and an output unit. The first storage stores identification information of sectors and defective information indicating a presence of defect on the data line, while associating the identification information... Agent: Kabushiki Kaisha Toshiba

20130077420 - Semiconductor memory device and defective cell relieving method: A memory cell array of a first semiconductor chip includes a normal cell array and a spare cell array. A first defect address data storage circuit outputs first defect address data indicating an address of a defective memory cell in the memory cell array. A first comparison circuit compares address... Agent: Kabushiki Kaisha Toshiba

20130077421 - Failure diagnosis circuit: A failure diagnosis circuit includes a multiplexer and a controller. The multiplexer receives address signals, and selectively outputs one of the address signals to an addressable module in response to a selecting signal. The controller generates a first one of address signals and the selecting signal. A built-in self-test circuit... Agent: Stmicroelectronics S.r.l.

20130077422 - Integrated solution for identifying malfunctioning components within memory devices: A method for testing a memory device. The memory device includes a matrix of memory cells having a plurality of rows and columns; the matrix includes a plurality of rows of operative memory cells each one for storing a variable value and at least one row of auxiliary memory cells... Agent: Stmicoelectronics S.r.l.

20130077423 - Refresh method and apparatus for a semiconductor memory device: A semiconductor memory device includes a bit line sense amplifier configured to sense and amplify data of a first bit line coupled to a first memory cell of a first cell block when a refresh operation is performed on the first cell block, and sense and amplify data of a... Agent: Hynix Semiconductor Inc.

20130077424 - Semiconductor memory circuit and control method for reading data: A semiconductor memory device includes a first memory circuits connecting to a first bit line, a second bit line and a word line, a first pre-charge control circuit connecting to a first pre-charge control line, the first bit line and the second bit line and that pre-charges the first bit... Agent: Fujitsu Limited

20130077425 - Techniques for providing a direct injection semiconductor memory device: Techniques for providing a direct injection semiconductor memory device are disclosed. In one exemplary embodiment, the techniques may be realized as a direct injection semiconductor memory device including a plurality of memory cells arranged in an array of rows and columns. At least one of the plurality of memory cells... Agent: Micron Technology Inc.

20130077426 - Semiconductor storage apparatus and semiconductor integrated circuit: In a semiconductor storage apparatus, an internal address generation unit generates, when receiving successive first and second external addresses, from the second external address an internal address for selecting any of the memory cells connected to bit lines and word lines except the bit line and word line connected to... Agent: Fujitsu Limited

20130077427 - Semiconductor device having cal latency function: Disclosed herein is a semiconductor device that includes a command receiver receiving the command signal to generate a first internal command signal, and a latency control circuit activating a second internal chip select signal after elapse of first cycles of a clock signal since a first internal chip select signal... Agent: Elpida Memory, Inc.

20130077428 - Semiconductor device having pda function: Disclosed herein is a semiconductor device that includes a command decoder activating a first mode register setting signal in response to a mode register setting command supplied from outside, a first latency shifter activating a second mode register setting signal after elapse of predetermined cycles of a clock signal since... Agent: Elpida Memory, Inc.

20130077429 - Semiconductor device verifying signal supplied from outside: Disclosed herein is a semiconductor device that includes an access control circuit generating an internal command based on a verification result signal and an external command. The external command indicates at least one of a first command that enables the access control circuit to access a first circuit and a... Agent: Elpida Memory, Inc.

20130077430 - Semiconductor system: A semiconductor system includes a first clock channel and a second clock channel. The first clock channel transmits a first clock signal from a controller to a memory. The second clock channel transmits a second clock signal with a phase difference of 90° from the first clock signal, from the... Agent:

20130070506 - Semiconductor device having stacked layers: A semiconductor device is disclosed in which there are provided a first substrate including memory cells and at least one bit line electrically coupled to the memory cells, and a second substrate including a sense amplifier. Each of the memory cells includes a first transistor, and the sense amplifier includes... Agent: Elpida Memory Inc.

20130070507 - Semiconductor memory device: A memory device is provided. The memory device includes a first semiconductor chip including a memory element and a peripheral circuit configured to write or read data in or from the memory element; and a second semiconductor chip configured to perform an input/output function of data or signals exchanged between... Agent:

20130070509 - Memory device having data paths: Apparatus and methods are disclosed, such as those involving array/port consolidation and/or swapping. One such apparatus includes a plurality of port pads including a plurality of contacts; a plurality of memory arrays; and a plurality of master data lines. Each of the master data lines extends in a space between... Agent: Micron Technology, Inc.

20130070508 - Semiconductor device and method for manufacturing same: According to an embodiment, a method of manufacturing a semiconductor device including a memory array provided on a substrate, and a control circuit provided on a surface of the substrate between the substrate and the memory array, includes steps of forming, in an insulating layer covering a p-type semiconductor region... Agent: Kabushiki Kaisha Toshiba

20130070510 - Method for reading a holographic memory on a data medium: a photonic crystal configured, firstly, to filter the light received from a broad-spectrum light source in order to select a frequency band of the said spectrum and secondly, to guide the light corresponding to the said selected frequency band so as to light the said holographic memory in a predefined... Agent: Gemalto Sa

20130070514 - Integrated circuit with on-die distributed programmable passive variable resistance fuse array and method of making same: An integrated circuit employs a plurality of functional blocks, such as but not limited to, processors (e.g., cores), and an on-die distributed programmable passive variable resistance memory array configured to provide configuration information for each of the plurality of functional blocks. A corresponding sub-portion of the on-die distributed programmable passive... Agent: Advanced Micro Devices, Inc.

20130070515 - Method and apparatus for controlling state information retention in an apparatus: A method and apparatus for controlling state information retention determines at least a state information save or restore condition for at least one processing circuit such as one or more CPU or GPU cores or pipelines, in an integrated circuit. In response to determining the state information save or restore... Agent: Advanced Micro Devices, Inc.

20130070513 - Method and apparatus for direct backup of memory circuits: An integrated circuit employs at least one active memory circuit and at least one memory state backup circuit wherein the at least one memory state backup circuit includes at least one passive variable resistance memory cell and at least one passive variable resistance memory cell interface that are used to... Agent: Advanced Micro Devices, Inc.

20130070512 - Non-volatile memory device: A non-volatile memory device includes a memory cell including a resistance variable device and a switching unit for controlling a current flowing through the resistance variable device; a read reference voltage generator configured to generate a reference voltage according to a skew occurring in the switching unit; and a sense... Agent:

20130070517 - Resistance change memory: A resistance change memory includes a first conductive line extending in a first direction, a second conductive line extending in a second direction which is crossed to the first direction, a cell unit including a memory element and a rectifying element connected in series between the first and second conductive... Agent:

20130070511 - Select devices for memory cell applications: Select devices for memory cell applications and methods of forming the same are described herein. As an example, one or more memory cells comprise a a select device structure including a two terminal select device having a current-voltage (I-V) profile associated therewith, and a non-ohmic device in series with the... Agent: Micron Technology, Inc.

20130070516 - Variable resistance nonvolatile memory device and driving method thereof: A variable resistance nonvolatile memory device includes a memory cell array, a memory cell selection circuit, a write circuit, and a read circuit. The read circuit determines that a selected memory cell has a short-circuit fault when a current higher than or equal to a predetermined current passes through the... Agent:

20130070518 - Antiferromagnetic storage device: An antiferromagnetic nanostructure according to one embodiment includes an array of at least two antiferromagnetically coupled magnetic atoms having at least two magnetic states that are stable for at least one picosecond even in the absence of interaction with an external structure, the array having a net magnetic moment of... Agent: International Business Machines Corporation

20130070521 - Magnetic random access memory devices including heating straps: A memory device includes at least one magnetic random access memory cell, which includes: (1) a magnetic tunnel junction having a first end and a second end; and (2) a strap electrically coupled to the second end of the magnetic tunnel junction. The memory device also includes a bit line... Agent:

20130070520 - Magnetic random access memory devices including shared heating straps: A memory device includes: (1) multiple magnetic random access memory (“MRAM”) cells each including a first end and a second end; (2) a bit line electrically coupled to the first end of at least one of the MRAM cells; and (3) a strap electrically coupled to the second end of... Agent:

20130070519 - Read architecture for mram: A read architecture for reading random access memory (RAM) cells includes a multi-level sense amplifier, the multi-level sense amplifier including a plurality of sense amplifiers, each sense amplifier having a respective sense threshold and a respective sense output, and a storage module coupled to the multi-level sense amplifier for storing... Agent: Taiwan Semiconductor Manufacturing Co., Ltd.

20130070523 - Magnetic memory element and nonvolatile memory device: According to one embodiment, a magnetic memory element includes a stacked body including first and second stacked units. The first stacked unit includes first and second ferromagnetic layers and a first nonmagnetic layer. A magnetization of the first ferromagnetic layer is fixed in a direction perpendicular to the first ferromagnetic... Agent: Kabushiki Kaisha Toshiba

20130070522 - Nonvolatile memory device: According to one embodiment, a nonvolatile memory device includes a magnetic memory element and a control unit. The magnetic memory element includes a stacked body including first and second stacked units. The first stacked unit includes a first ferromagnetic layer having a magnetization fixed, a second ferromagnetic layer having a... Agent: Kabushiki Kaisha Toshiba

20130070526 - Flash memory and reading method of flash memory: A reading method of a flash memory, the reading method including: sensing hard data of a first target page by using a first hard read voltage; and generating soft data of the first target page by using at least one pair of, that is, two, first soft read voltages whose... Agent:

20130070525 - Nonvolatile semiconductor memory device: A nonvolatile semiconductor memory device according to an embodiment includes a control circuit controlling a read operation of applying a read voltage to a selected memory cell to read data, and a write verify operation of applying a verify voltage to the selected memory cell. In a first case, the... Agent: Kabushiki Kaisha Toshiba

20130070524 - On chip dynamic read for non-volatile storage: Dynamically determining read levels on chip (e.g., memory die) is disclosed herein. One method comprises reading a group of non-volatile storage elements on a memory die at a first set of read levels. Results of the two most recent of the read levels are stored on the memory die. A... Agent:

20130070530 - High endurance non-volatile storage: A non-volatile storage system is disclosed that includes non-volatile memory cells designed for high endurance and lower retention than other non-volatile memory cells.... Agent: Sandisk Technologies Inc.

20130070529 - Semiconductor device and operating method thereof: A method of operating a semiconductor device includes programming one of a drain dummy cell and a source dummy cell which are included in a cell string; and coupling a bit line to the cell string in response to program states of the drain dummy cell and the source dummy... Agent:

20130070528 - Semiconductor memory device: According to one embodiment, a semiconductor memory device includes a memory cell array, a bit line, a source line, and a sense circuit. The memory cell array includes memory strings which include memory cells connected in series and stacked above a semiconductor substrate. The bit line is coupled to one... Agent:

20130070527 - System and method for managing erase operations in a non-volatile memory: Embodiments of the invention are directed to managing a memory component. A method may include performing a first erase operation according to a first set of erase parameters, determining a result of the first erase operation, modifying the first set erase parameters based on the result to produce a second... Agent:

20130070531 - Substrate bias during program of non-volatile storage: A programming technique which reduces program disturb in a non-volatile storage system is disclosed. A positive voltage may be applied to a substrate (e.g., p-well) during programming. Biasing the substrate may improve boosting of channels of unselected NAND strings, which may reduce program disturb. The substrate may be charged up... Agent:

20130070532 - Nonvolatile semiconductor memory device: A nonvolatile semiconductor memory device according to an embodiment includes a control unit configured to perform a control of repeating a program operation, and a step-up operation, the program operation being an operation of applying a program pulse voltage to a selected memory cell and applying an intermediate voltage less... Agent: Kabushiki Kaisha Toshiba

20130070533 - Semiconductor memory device: A semiconductor memory device according to an embodiment includes a memory cell array including memory cells each formed from a transistor formed over an active area of a well and disposed at intersections of a word line and a bit line group, the memory cell having different connection states including... Agent: Kabushiki Kaisha Toshiba

20130070539 - Dynamic random access memory with fully independent partial array refresh function: A dynamic random access memory device includes a plurality of memory subblocks. Each subblock has a plurality of wordlines whereto a plurality of data store cells are connected. Partial array self-refresh (PASR) configuration settings are independently made. In accordance with the PASR settings, the memory subblocks are addressed for refreshing.... Agent: Mosaid Technologies Incorporated

20130070535 - Nonvolatile memory device and method of operating the same: A nonvolatile memory device includes a control logic configured to generate an internal command in response to an internal clock, a finite state machine configured to generate a plurality of current state signals in a program pulse and verify pulse setup operation for a program operation and a program verify... Agent:

20130070534 - Programmable current-limited voltage buffer, integrated-circuit device and method for current-limiting a memory element: A programmable current-limited voltage buffer 130-1. The programmable current-limited voltage buffer 130-1 includes at least one current-bias circuit 230-1, an inverter 230-2, a write-current set control circuit 230-3, and an adaptive current limiter 230-4. The inverter 230-2 is coupled to the current-bias circuit 230-1 and a reference-voltage source 178, and... Agent:

20130070536 - Semiconductor device latching data signal in response to strobe signal and information processing system including the same: Disclosed herein is a device including a timing control circuit that receives a strobe signal supplied from outside to generate an internal strobe signal that is used as a timing signal to latch a data signal. An operation state of the timing control circuit is changed according to temperature change... Agent:

20130070537 - Semiconductor device operates on external and internal power supply voltages and data processing system including the same: The semiconductor device including an output terminal; and an output unit coupled to the output terminal. The output unit includes an output buffer coupled to the output terminal and operating on a first power supply voltage, a first control circuit operating on a second power supply voltage, receiving an impedance... Agent: Elpida Memory, Inc.

20130070538 - Semiconductor memory device and data reading method: A semiconductor memory device includes two memory cell arrays, a sense amplifier shared by the two memory cell arrays; and a control circuit configured to control data readout from the two memory cell arrays. Each memory cell array includes word lines, two or more bit lines, a dummy word line,... Agent: Fujitsu Semiconductor Limited

20130070540 - Voltage regulation for 3d packages and method of manufacturing same: Disclosed herein are structures and related processes for effectively regulating power among slave chips in a 3D memory multichip package that employs TSVs for interlevel chip connections. The disclosed techniques employ individual voltage regulators on one or more of the slave chips for accurate level control of internal voltages, for... Agent: Mosaid Technologies Incorporated

20130070541 - Nonvolatile memory device: A nonvolatile memory device includes a plurality of memory blocks vertically arranged, first and second row decoder groups configured to couple first and second local global word lines and the word lines of upper memory blocks among the plurality of memory blocks, third and fourth row decoder groups configured to... Agent:

20130070542 - Replica circuit and it's applications: A replica circuit includes: a first conductivity type first transistor; a first current path including a first conductivity type second transistor and a second conductivity type third transistor; a second current path including a first conductivity type fourth transistor configured so that current equivalent to a current flowing through the... Agent: Genusion, Inc.

20130070543 - Semiconductor memory device including data transfer bus and data transfer method of the device: According to one embodiment, a semiconductor memory device includes a memory cell array, a data bus, a transfer controller, column blocks, and a column selector. The data bus is divided into stages. The transfer controller serially transfers data such that the data are respectively allocated to the stages. The column... Agent:

20130070544 - Memory interface circuit and timing adjusting method: A memory interface circuit, which controls capture timing of data provided from a memory according to a strobe signal provided from the memory, includes a control unit that controls an activation timing of an internal strobe gate signal, which masks the strobe signal when being deactivated, by delaying the internal... Agent: Fujitsu Semiconductor Limited

20130070547 - Memory system with a layer comprising a dedicated redundancy area: Systems and methods are disclosed that may include a first layer comprising a first redundant memory element, an input/output interface, a first layer fuse box, and a fuse blowing control. These systems and methods also may include a second layer coupled to the first layer through a first connection comprising... Agent: Mosaid Technologies Incorporated

20130070546 - Nonvolatile semiconductor memory device: A nonvolatile semiconductor memory device according to the embodiment comprises a memory cell array including plural blocks arranged in a first direction, each block containing plural memory cells operative to store data; a row decoder including a faulty block information holder circuit operative to store faulty block information indicative that... Agent: Kabushiki Kaisha Toshiba

20130070545 - Semiconductor integrated circuit: The built-in self-test (BIST) circuit includes an address generating circuit. The BIST circuit includes a data generating circuit. The BIST circuit includes a chip enable signal generating circuit. The BIST circuit includes a control signal generating circuit. The memory block circuit includes the multiple memories. The memory block circuit includes... Agent: Kabushiki Kaisha Toshiba

20130070548 - Semiconductor memory device correcting fuse data and method of operating the same: A semiconductor memory device and method of operating same are described. The semiconductor memory device includes a first anti-fuse array having a plurality of first anti-fuse elements that store first fuse data, a second anti-fuse array having a plurality of second anti-fuse elements that store error correction code (ECC) data... Agent: Samsung Electronics Co., Ltd.

20130070550 - Adaptive write bit line and word line adjusting mechanism for memory: A memory including a capacitor coupled to a write bit line or a word line and an initializer configured to initialize a voltage level at a first node between the capacitor and the write bit line or the word line. The memory further includes a controllable initial level adjuster configured... Agent: Taiwan Semiconductor Manufacturing Company, Ltd.

20130070549 - Single-ended sense amplifier with read-assist: A sense amplifier is provided that comprises, responsive to receiving a set signal to turn on a set device and a precharged voltage level read bit line signal, a keeper device that turns on responsive to receiving a LOW signal from an inverting amplifier and pulls up the voltage at... Agent: International Business Machines Corporation

20130070551 - Percolation tamper protection circuit for electronic devices: An integrated circuit employing a percolation tamper protection device includes a circuit housing with a die disposed in circuit housing. The die includes a volatile memory. A percolation tamper protection device that is connected to the volatile memory and also disposed in the circuit housing. The percolation tamper protection device... Agent: Qortek, Inc.

20130070552 - Non-volatile memory device: A non-volatile memory device includes a plurality of memory blocks, first block switches configured to correspond to the respective odd-numbered memory blocks of the plurality of memory blocks and couple the word lines of the odd-numbered memory blocks and first local lines, second block switches configured to correspond to the... Agent: Sk Hynix Inc.

20130070553 - Semiconductor device having charge pump circuit and information processing apparatus including the same: Disclosed herein is a device that includes a capacitor, a pumping circuit supplying a pumping signal changed between first and second potential to a first electrode of the capacitor, and an output circuit precharging a second electrode of the capacitor to a third potential different from the first and second... Agent: Elpida Menory, Inc.

20130063997 - High-resolution readout of analog memory cells: A method includes storing data in an analog memory cell by writing an analog value into the memory cell. After storing the data, the data stored in the memory cell is read by discharging electrical current to flow through the memory cell, during a predefined time interval, while applying a... Agent:

20130063998 - System and memory module: A system includes: a controller, a first memory module connected to the controller through a first data bus, and a second memory module connected to the controller through a second data bus, wherein the first memory module includes: first and second memory chips; a first data terminal connected to the... Agent: Elpida Memory, Inc.

20130063999 - Electronic device including a nonvolatile memory structure having an antifuse component and a process of using the same: An electronic device can include a nonvolatile memory cell, wherein the nonvolatile memory cell can include an antifuse component, a switch, and a read transistor having a control electrode. Within the nonvolatile memory cell, the switch can be coupled to the antifuse component, and the control electrode of the read... Agent:

20130064001 - Resistance change nonvolatile memory device, semiconductor device, and method of manufacturing resistance change nonvolatile memory device: To provide a resistance change nonvolatile memory device performing a stable switching operation at a low cost. The resistance change nonvolatile memory device has a first wiring, an interlayer insulating layer formed thereon, a second wiring formed thereon, and a resistance change element formed between the first wiring and the... Agent: Renesas Electronics Corporation

20130064002 - Resistance change nonvolatile memory device, semiconductor device, and method of operating resistance change nonvolatile memory device: A resistance change nonvolatile memory device includes with a first electrode, a resistance change portion provided on the first electrode, and a second electrode provided on the resistance change portion. The resistance change portion is equipped with a resistance change layer provided on the first electrode and undergoing a change... Agent: Renesas Electronics Corporation

20130064000 - Semiconductor storage device including memory cells capable of holding data: According to one embodiment, a semiconductor storage device includes first cells, first bit and first word, and first sense. The first cells are capable of holding 2-level or higher-level data. The first bit and first word are capable of selecting the first cells. The first sense detects a first current.... Agent:

20130064006 - Apparatus for selective word-line boost on a memory cell: Systems and methods for selectively boosting word-line (WL) voltage in a memory cell array. The method relies several embodiments to minimize energy costs associated with WL boost scheme. One embodiment generates a transient voltage boost rather than supply a DC voltage boost. The transient boost generation may be controlled on... Agent: Qualcomm Incorporated

20130064003 - Dual port static random access memory cell: An SRAM has at least two sets of pass transistors for coupling at least two sets of bit lines to true and complement data nodes of an SRAM cell based on the assertion of at least two word lines. The cell includes two pull up transistors and two pull down... Agent:

20130064004 - Sram cell writability: Systems and methods for detecting and improving writeability of a static random access memory (SRAM) cell. A bias voltage value corresponding to an operating condition, such as, a process, a voltage, or a temperature operation condition that indicates a cell write failure condition of an external SRAM array comprising the... Agent: Qualcomm Incorporated

20130064005 - Tunnel transistor, logical gate comprising the transistor, static random-access memory using the logical gate and method for making such a tunnel transistor: A tunnel transistor is provided comprising a drain, a source and at least a first gate for controlling current between the drain and the source, wherein the first sides of respectively the first and the second gate dielectric material are positioned substantially along and substantially contact respectively the first and... Agent: Imec

20130064007 - Disturb-free static random access memory cell: A solid-state memory in which each memory cell includes a cross-point addressable write element. Each memory cell includes a storage element, such as a pair of cross-coupled inverters, and a read buffer for coupling one of the storage nodes to a read bit line for the column containing the cell.... Agent: Texas Instruments Incorporated

20130064008 - Data read circuit, nonvolatile memory device comprising data read circuit, and method of reading data from nonvolatile memory device: A nonvolatile memory device comprises a nonvolatile cell array comprising a memory cell and a reference cell, a clamping circuit electrically connected to the memory cell and configured to clamp a voltage applied to a data sensing line during a read operation, and a clamping voltage generation unit configured to... Agent: Samsung Electronics Co., Ltd.

20130064009 - Size-reduced magnetic memory cell: A semiconductor device includes: a first memory cell, a second memory cell adjacent to the first memory cell, first and second write bitlines and a common bitline. The first memory cell includes: a first magnetization fixed layer, a first magnetic recording layer, a first reference layer, a first tunnel barrier... Agent:

20130064010 - Memory cell having nonmagnetic filament contact and methods of operating and fabricating the same: A magnetic cell structure including a nonmagnetic filament contact, and methods of fabricating the structure are provided. The magnetic cell structure includes a free layer, a pinned layer, an insulative layer between the free and pinned layers, and a nonmagnetic filament contact in the insulative layer which electrically connects the... Agent: Micron Technology, Inc.

20130064011 - Stt-mram cell structure incorporating piezoelectric stress material: A magnetic memory cell including a piezoelectric material, and methods of operating the memory cell are provided. The memory cell includes a stack, and the piezoelectric material may be formed as a layer in the stack or adjacent the layers of the cell stack. The piezoelectric material may be used... Agent: Micron Technology, Inc.

20130064012 - Semiconductor device and method of manufacturing semiconductor device: A semiconductor device includes a first transistor, formed in a substrate, that includes a first gate insulating film, a source and a drain region, a first gate electrode, and a first sidewall, and a second transistor that includes a second gate insulating film, a second gate electrode, a source and... Agent: Renesas Electronics Corporation

20130064013 - Non-volatile multi-level memory device and data read method: A non-volatile memory device, a data read method thereof and a recording medium are provided. The method includes receiving a data read command for a first word line in a memory cell array, reading data from a second word line adjacent to the first word line, and reading data from... Agent:

20130064014 - Eeprom memory protected against breakdown of control gate transistors: The disclosure relates to an electrically erasable and programmable memory comprising at least one word of memory cells with first and second control gate transistors in parallel to apply a control gate voltage to the memory cells of the word. The memory also comprises s first control circuit to supply... Agent: Stmicroelectronics (rousset) Sas

20130064015 - Method of burn-in test of eeprom or flash memories: The disclosure relates to a method for testing an integrated circuit, comprising in a burn-in test mode, two steps during which gate oxides of conductive high voltage MOS transistors of the integrated circuit are subjected to a first test voltage, and blocked high voltage MOS transistors of the integrated circuit... Agent: Stmicroelectronics (rousset) Sas

20130064016 - Semiconductor device and control method of the same: The present invention provides a semiconductor memory and a control method therefor, the semiconductor device including a first current-voltage conversion circuit connected to a core cell provided in a nonvolatile memory cell array, a second current-voltage conversion circuit connected to a reference cell through a reference cell data line, a... Agent:

20130064017 - Concurrent operation of plural flash memories: A device comprises an address storage device. A first circuit includes a first flash memory, configured to sequentially receive first and second addresses and store the first address in the address storage device. The first circuit has a first set of control inputs for causing the first circuit to perform... Agent: Taiwan Semiconductor Manufacturing Co., Ltd.

20130064022 - Method and apparatus for memory access: An interleaver or deinterleaver comprises a memory having M logical memory units arranged in groups of N memory units such that accesses to memory units within a group are faster after a first access to a memory in that group using first access. An address generator is arranged to write... Agent: British Broadcasting Corporation

20130064018 - Memory access circuit for double data/single data rate applications: A memory access circuit includes a write data circuit and a first write switch circuit. The write data circuit is used for receiving double data rate data or single data rate data, and outputting odd term data and even term data of adjusted double data rate data or adjusted single... Agent:

20130064019 - Data storage circuit that retains state during precharge: A data storage circuit for receiving and holding a data value includes an input stage configured to receive a data value in response to the precharge phase changing to an evaluation phase and to hold the data value during the evaluation phase. An output stage has an output latching element... Agent: Arm Limited

20130064020 - Semiconductor memory apparatus: A semiconductor memory apparatus includes a first data input/output line configured to transmit data from a first memory bank; a second data input/output line configured to transmit the data from the first memory bank; a first data output section configured to align and output data transmitted through the first data... Agent: Sk Hynix Inc.

20130064021 - Sense amplifier with fast bitline precharge means: The disclosure relates to a sense amplifier comprising a cascode transistor and means for biasing the cascode transistor, supplying a control voltage to a gate terminal of the cascode transistor. The means for biasing the cascode transistor comprise means for isolating the gate terminal of the cascode transistor from the... Agent: Stmicroelectronics (rousset) Sas

20130064023 - Memory systems and methods for dynamically phase adjusting a write strobe and data to account for receive-clock drift: A memory system includes a memory controller that writes data to and reads data from a memory device. A write data strobe accompanying the write data indicates to the memory device when the write data is valid, whereas a read strobe accompanying data from the memory device indicates to the... Agent: Rambus Inc.

20130064024 - Semiconductor device and method for controlling: A semiconductor device is disclosed. The semiconductor device includes a plurality of memory cells provided in a matrix and having a charge storage layer, a plurality of word lines provided on the charge storage layer, and an application section. When reading data from a selected memory cell selected from the... Agent:

20130064025 - Dynamic data strobe detection: Techniques are disclosed relating to determining when a data strobe signal is valid for capturing data. In one embodiment, an apparatus is disclosed that includes a memory interface circuit configured to determine an initial time value for capturing data from a memory based on a data strobe signal. In some... Agent:

20130064026 - Technology of memory repair after stacking of three-dimensional integrated circuit: A three-dimensional integrated circuit (3-D IC) includes a controller chip and at least one memory chip, in which, besides an original storage capacity, the memory chip further includes multiple spare memory cells and an address translation circuit with an external activation/enablement function. After the memory chip and the controller chip... Agent: Industrial Technology Research Institute

20130064027 - Memory and method of adjusting operating voltage thereof: By adjusting an operating voltage of a memory cell in a memory according to a measured capacitance result indicating capacitance of an under-test capacitor of the memory cell, an appropriate operating voltage for the memory cell can always be determined according to the measured capacitance result. The measured capacitance result... Agent:

20130064029 - Semiconductor memory device and operating method thereof: An operating method of a semiconductor memory device includes precharging a channel region of a program-inhibited cell of first memory cells coupled to a first word line, selected from a first one of word line groups between a drain select line and a source select line, to a first level... Agent: Sk Hynix Inc.

20130064028 - Semiconductor memory device and sense amplifier: A semiconductor memory device comprises a memory cell; a first bit line and a second bit line connected to the memory cell; and a sense amplifier operative to amplify the voltage between the first and second bit lines. The sense amplifier includes a first and a second drive transistor configuring... Agent: Kabushiki Kaisha Toshiba

20130064030 - Semiconductor devices, methods of operating semiconductor devices, and systems having the same: A semiconductor device includes a selection circuit and a phase detector. The selection circuit, in response to a first selection signal output from a controller, outputs as a timing signal a first clock signal output from the controller or an output signal of a PLL using the first clock signal... Agent: Samsung Electronics Co., Ltd.

20130064031 - Adaptive read wordline voltage boosting apparatus and method for multi-port sram: Embodiments of the invention are directed to systems and methods for adaptively boosting the supply voltage to an SRAM (Static Random Access Memory) in response to process-voltage-temperature variations when needed. Embodiments include a critical path that simulates a typical memory cell and read-out circuit in the SRAM. Applying a trigger... Agent: Qualcomm Incorporated

20130064032 - Semiconductor storage device and electronic apparatus: A semiconductor storage device includes a plurality of memory macros including a plurality of memory cell arrays; a low-potential power supply boosting circuit coupling the low-potential power supply to the ground in a normal mode and coupling the low-potential power supply to a voltage higher than a ground voltage in... Agent: Fujitsu Semiconductor Limited

20130058145 - Memory system: A semiconductor device includes a first memory region including a plurality of memory cells; a test unit configured to test the first memory region, and detect a weak bit from among the plurality of memory cells; and a second memory region configured to store a weak bit address (WBA) of... Agent: Samsung Electronics Co., Ltd.

20130058146 - Three-dimensional offset-printed memory: The present invention discloses a three-dimensional offset-printed memory (3D-oP). Compared with a conventional three-dimensional mask-programmed read-only memory (3D-MPROM), it has a lower data-mask count and thereby a lower data-mask cost. The mask-patterns for different memory levels/bits-in-a-cell are merged onto a multi-region data-mask. At different printing steps, a wafer is offset... Agent: Chengdu HaicunIPTechnology LLC

20130058147 - Three-dimensional writable printed memory: The present invention discloses a three-dimensional writable printed memory (3D-wP). It comprises at least a printed memory array and a writable memory array. The printed memory array stores contents data, which are recorded with a printing means; the writable memory array stores custom data, which are recorded with a writing... Agent: Chengdu HaicunIPTechnology LLC

20130058148 - High density memory modules: Solid state memory modules are disclosed having increased density for module size/footprint. Different embodiments also provide for improved interconnect arrangements between the memory modules and the corresponding field programmable gate array (FPGA), micro-processor (μP), or application-specific integrated circuit (ASIC). These interconnects can provide for greater module interconnect flexibility, operating speed... Agent: Interconnect Systems, Inc.

20130058149 - Memory devices, methods of storing and reading data, smm junctions, and methods of preparing alumina substrates: Various aspects of the invention provide memory devices, methods of storing and reading data, and silver/molecular-layer/metal (SMM) junctions. One aspect of the invention provides a memory device including a plurality of SMM junctions and an electrical structure configured to permit application of electricity across one or more of the plurality... Agent: University Of Memphis Research Foundation

20130058151 - Non-volatile memory with split write and read bitlines: Read and write operations of a non-volatile memory (NVM) bitcell have different optimum parameters resulting in a conflict during design of the NVM bitcell. A single bitline in the NVM bitcell prevents optimum read performance. Read performance may be improved by splitting the read path and the write path in... Agent: Qualcomm Incorporated

20130058150 - Otp memory: The present invention provides an OTP memory having higher confidentiality. A memory cell has a memory transistor forming a current path between first and second nodes, a selection transistor forming a current path between third and fourth nodes, the third node being coupled to the gate of the memory transistor... Agent: Renesas Electronics Corporation

20130058152 - Method, system, and device for phase change memory switch wall cell with approximately horizontal electrode contact: Embodiments disclosed herein may include depositing a storage component material over and/or in a trench in a dielectric material, including depositing the storage component material on approximately vertical walls of the trench and a bottom of the trench. Embodiments may also include etching the storage component material so that at... Agent: Micron Technology, Inc.

20130058154 - Semiconductor device and method of manufacturing the same: A semiconductor device includes a plurality of first memory cells, at least one of second memory cells, and a control circuit. The plurality of first memory cells are accessed during normal operation, wherein the first memory cell includes a first variable resistance element. The second memory cell is not accessed... Agent: Elpida Memory, Inc.

20130058153 - Semiconductor devices including variable resistance elements and methods of operating semiconductor devices: In a method of operating a semiconductor device, a resistance value of a variable resistance element is changed from a first resistance value to a second resistance value by applying a first voltage to the variable resistance element; and a first current that flows through the variable resistance element is... Agent: Samsung Electronics Co., Ltd.

20130058155 - Sram dimensioned to provide beta ratio supporting read stability and reduced write time: A 6T SRAM includes two inverters connected in antiparallel, and two access transistors, each connected between a bit line and a common node of the inverters. Each inverter includes a pullup transistor and a pulldown transistor. A product formed by a ratio of the pulldown transistor gate width to the... Agent: Stmicroelectronics (crolles 2) Sas

20130058156 - Magnetic memory cell and magnetic random access memory: A relation between a drive current of a selection transistor of a magnetic memory and a threshold magnetization switching current of the magnetoresistance effect element is optimized. In order to optimize the relation between the drive current of the selection transistor and the threshold magnetization switching current of the magnetoresistance... Agent:

20130058157 - Magnetic random access memory device: The present invention proposes an electronic memory device comprising a memory line including a memory domain. The memory line may contain a number of memory domains and a number of fixed domains, wherein each memory domain stores a single binary bit value. A multiferroic element may be disposed proximate to... Agent: University Of Virginia Patent Foundation, D/b/a University Of Virginia Licensing & Ventures Group

20130058159 - Method of operating phase-change memory: One or more embodiments may be related to a method of operating a phase-change memory element, comprising: providing the phase-change memory element, the phase-change memory element having a first terminal and a second terminal; causing a first current through the memory element from the first terminal to the second terminal;... Agent:

20130058158 - Method, system, and device for l-shaped memory component: Embodiments disclosed herein may relate to forming reduced size storage components in a cross-point memory array. In an embodiment, a storage cell comprising an L-shaped storage component having an approximately vertical portion extending from a first electrode positioned below the storage material to a second electrode positioned above and/or on... Agent: Micron Technology, Inc.

20130058160 - Phase change memory device and computing system having the same: A phase change memory device includes a memory cell array, a register unit and a control unit. The memory cell array includes a plurality of phase change memory cells. The register unit includes a circular queue. The control unit receives a write address and a write data in a write... Agent:

20130058161 - Memory device and method for manufacturing the same: According to one embodiment, a memory device includes: a first signal line; a second signal line; a transistor; a first memory region; and a second memory region. The transistor controls a conduction of each of a current flowing between the first and the second signal lines and an opposite current.... Agent: Kabushiki Kaisha Toshiba

20130058162 - Memory device and method for manufacturing the same: According to one embodiment, a memory device includes: a first signal line; a second signal line; a transistor; a memory region; and a conductive region. The transistor controls a conduction of each of a current in a first direction flowing between the first line and the second line and a... Agent: Kabushiki Kaisha Toshiba

20130058163 - Semiconductor memory device: According to one embodiment, a semiconductor memory device includes a stacked body, a semiconductor pillar, a charge storage layer, a tunneling layer, a dividing trench and a first heating unit. The stacked body includes a plurality of first insulating films stacked alternately with a plurality of electrode films. The semiconductor... Agent: Kabushiki Kaisha Toshiba

20130058164 - Memory apparatus, systems, and methods: Threshold voltages in a charge storage memory are controlled by threshold voltage placement, such as to provide more reliable operation and to reduce the influence of factors such as neighboring charge storage elements and parasitic coupling. Pre-compensation or post-compensation of threshold voltage for neighboring programmed aggressor memory cells reduces the... Agent:

20130058165 - Semiconductor memory device: According to one embodiment, a semiconductor memory device includes a memory cells, a selection transistor, a memory string, a block, and a transfer circuit. The memory cells are stacked on a semiconductor substrate. In the memory string, the memory cells and the selection transistor are connected in series. The block... Agent:

20130058168 - Methods, devices, and systems for dealing with threshold voltage change in memory devices: The present disclosure includes methods, devices, and systems for dealing with threshold voltage change in memory devices. A number of embodiments include an array of memory cells and control circuitry having sense circuitry coupled to the array. The control circuitry is configured to determine changes in threshold voltages (Vts) associated... Agent: Micron Technology, Inc.

20130058167 - Semiconductor device using charge pump circuit: A semiconductor device including a plurality of capacitance units connected in parallel between a first voltage and a second voltage. Each of the plurality of capacitance units includes: a capacitance element connected with the first voltage; and a capacitance disconnecting circuit connected between the second voltage and the capacitance element.... Agent: Renesas Electronics Corporation

20130058166 - Semiconductor memory device: According to one embodiment, a semiconductor memory device includes memory cells, word lines, a driver circuit, and a control circuit. The memory cells are stacked above a semiconductor substrate, and each includes a charge accumulation layer and control gate. The word lines are coupled to the control gates. The driver... Agent:

20130058169 - Non-volatile memory systems: In a non-volatile memory system, a plurality of main memory cells for storing data is arranged in a data cell array and a plurality of reference memory cells is arranged in a reference cell array. The reference cell array includes first reference word lines connected to first reference memory cells... Agent: Samsung Electronics Co., Ltd.

20130058170 - Nonvolatile semiconductor storage device: A nonvolatile semiconductor storage device according to an embodiment includes a drive circuit. A voltage applied to a dummy wire connected to a first dummy cell adjacent to a memory string is defined as a first dummy wire voltage, a voltage applied to a selection wire connected to a first... Agent: Kabushiki Kaisha Toshiba

20130058171 - Semiconductor storage device: n

20130058173 - Semiconductor apparatus: A semiconductor apparatus according to an aspect of the present invention includes first and second bus-interface circuits, a mode information storage unit that stores first and second mode information, the first and second mode information being able to be set through the first bus-interface circuit, a first memory core that... Agent:

20130058172 - Code-based differential charging of bit lines of a sense amplifier: A circuit includes a plurality of capacitors responsive to a plurality of latches that store a test code. A first bit line is coupled to a bit cell and coupled to a sense amplifier. A second bit line is coupled to the bit cell and coupled to the sense amplifier.... Agent: Qualcomm Incorporated

20130058174 - Controller and access method for ddr psram and operating method thereof: A controller for a DDR PSRAM is provided. The controller includes a single rate processing unit, a double rate processing unit and a selector. The signal rate processing unit obtains a single data rate data according to a first data and a first clock. The double rate processing unit obtains... Agent: Mediatek Inc.

20130058175 - Ddr psram and data writing and reading methods thereof: A double data rate pseudo SRAM (DDR PSRAM) is provided. The DDR PSRAM includes a data receiver, a memory and an address decoder. The data receiver receives a first single data rate data from a controller via a common bus according to a clock, and receives a double data rate... Agent: Mediatek Inc.

20130058176 - Determining fusebay storage element usage: Used fusebay storage elements are counted so that storage of data may begin at a first unused storage element. Repair register length and a number of previous passes are stored in a fuse header of a fusebay. When a bit of data is sent to the repair register, a repair... Agent: International Business Machines Corporation

20130058177 - Method of screening static random access memory cells for positive bias temperature instability: A method of screening complementary metal-oxide-semiconductor CMOS integrated circuits, such as integrated circuits including CMOS static random access memory (SRAM) cells, for n-channel transistors susceptible to transistor characteristic shifts over operating time. For the example of SRAM cells formed of cross-coupled CMOS inverters, static noise margin and writeability (Vtrip) screens... Agent: Texas Instruments Incorporated

20130058178 - System and method for testing integrated circuits by determining the solid timing window: Systems and methods are provided to determine a solid operating timing window for an integrated circuit device, the solid timing window used to determine a key timing index. The key timing index provides an indication of the quality of an integrated circuit over a range of operating conditions. In at... Agent: Kingtiger Technology (canada) Inc.

20130058179 - System and method for increasing ddr memory bandwidth in ddr sdram modules: A system and method for increasing DDR memory bandwidth in DDR SDRAM modules are provided. DDR memory has an inherent feature called the Variable Early Read command, where the read command is issued on CAS latency before the completion of the ongoing data burst and the effect of the CAS... Agent: Ocz Technology Group, Inc.

20130058180 - Semiconductor device having hierarchically structured bit lines and system including the same: A system includes a first circuit and a second circuit that are constituted by a semiconductor device, the second circuit controlling the first circuit. The first circuit includes an interface unit that performs communication with the second circuit, a plurality of sense amplifiers including a first sense amplifier, each of... Agent: Elpida Memory, Inc.

20130058181 - Memory with temperature compensation: A memory element in which the temperature coefficient of a memory cell substantially matches the temperature coefficient of a reference cell and tuning either the temperature coefficient of a memory cell to substantially match the temperature coefficient of the reference cell provides for improved precision of sensing or reading memory... Agent: Macronix International Co., Ltd.

20130058182 - Method and apparatus for programming an anti-fuse element in a high-voltage integrated circuit: A method for programming a programmable block of a power IC device includes selecting an anti-fuse element of the programmable block to be programmed. The anti-fuse element includes first and second capacitive plates separated by a dielectric layer. A voltage pulse is then applied to a pin of the power... Agent: Power Integrations, Inc.