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Static information storage and retrieval February patent applications/inventions, industry category 02/13

20130051109 - Method of reading a ferroelectric memory cell: A method of reading a memory cell is disclosed. The method includes the step of connecting (708) a reference voltage generator (600) to a first bitline (/BL). The first bitline is charged to a reference voltage (VREF) from the reference voltage generator. The reference voltage generator is disconnected (RFWL_A/B low... Agent:

20130051110 - Semiconductor apparatus: A semiconductor apparatus according to an aspect of the present invention includes first and second bus-interface circuits, a first memory core connected to the first bus-interface circuit through a first data bus, the first memory core being connected to a first access control signal output from the first bus-interface circuit,... Agent: Renesas Electronics Corporation

20130051111 - Anti-fuse circuit and integrated circuit including the same: An anti-fuse circuit and an integrated circuit (IC) including the same are disclosed, which are applied to a technology for use in all kinds of semiconductor devices or system ICs, each of which includes an anti-fuse circuit using the breakdown phenomenon of a gate oxide, so as to prevent the... Agent: Hynix Semiconductor Inc.

20130051112 - Finfet based one-time programmable device and related method: According to one embodiment, a one-time programmable (OTP) device comprises a memory FinFET in parallel with a sensing FinFET. The memory FinFET and the sensing FinFET share a common source region, a common drain region, and a common channel region. The memory FinFET is programmed by having a ruptured gate... Agent: Broadcom Corporation

20130051113 - Programmable non-volatile memory: A programmable non-volatile memory including a memory cell includes a transistor acting as an anti-fuse and two diodes for access. The memory cell that can store two bits and includes a transistor acting as an anti-fuse and two diodes for access, wherein the cell transistor includes: the source electrode formed... Agent:

20130051114 - Data read circuit, a non-volatile memory device having the same, and a method of reading data from the non-volatile memory device: A non-volatile memory device including a cell array, which includes a plurality of memory cells, and a sense amplification circuit. The sense amplification circuit is configured to receive a data voltage of a memory cell, a first reference voltage and a second reference voltage during a data read operation of... Agent:

20130051120 - Circuit for generating write signal, variable resistance memory device, and method for programming variable resistance memory: A circuit for generating a write signal includes a pre-emphasis signal generator that receives location information of a to-be-programmed memory cell and generates a pre-emphasis signal depending on the location information of the to-be-programmed memory cell, and a write driver that generates a program signal corresponding to data to be... Agent: Samsung Electronics Co., Ltd.

20130051115 - Integrated circuit with backside passive variable resistance memory and method for making the same: In one example, an integrated circuit includes memory control logic (e.g., CMOS logic circuit) on the front side of the integrated circuit die and passive variable resistance memory on the back side of the integrated circuit die. The passive variable resistance memory, also known as resistive non-volatile memory, may be... Agent: Advanced Micro Devices, Inc.

20130051116 - Integrated circuit with face-to-face bonded passive variable resistance memory and method for making the same: In one example, an integrated circuit includes two integrated circuit dies that are face-to-face mounted together. The first integrated circuit die includes passive variable resistance memory and the second integrated circuit die includes memory control logic (e.g., CMOS logic circuit). The passive variable resistance memory, also known as resistive non-volatile... Agent: Advanced Micro Devices, Inc.

20130051117 - Integrated circuit with vertically integrated passive variable resistance memory and method for making the same: In one example, an integrated circuit includes memory control logic (e.g., CMOS logic circuit) and passive variable resistance memory disposed above the memory control logic. The passive variable resistance memory, also known as resistive non-volatile memory, may be for example memristors, phase-change memory, or magnetoresistive memory. Each memory cell of... Agent: Advanced Micro Devices, Inc.

20130051125 - Method of operating semiconductor device including variable resistance device: According to an example embodiment, a method of operating a semiconductor device having a variable resistance device includes: applying a first voltage to the variable resistance device to change a resistance value of the variable resistance device from a first resistance value to a second resistance value that is different... Agent: Samsung Electronics Co., Ltd.

20130051123 - Resistance change memory device and current trimming method thereof: A resistance change memory device includes an array of resistance change memory cells, and a writing circuit configured to reset a selected memory cell to a high resistance state by supplying a RESET current to the selected memory cell in the array of resistance change memory cells in a program... Agent:

20130051119 - Resistive memory and program verification method thereof: A resistive memory including a transistor and a variable resistor is disclosed. The transistor includes a gate, a source and a drain. The variable resistor is coupled between the drain and a node. During a setting period, the gate receives a first gate voltage, the source receives a first source... Agent:

20130051124 - Resistive memory device and test systems and methods for testing the same: A resistive memory device and a system and method for testing the resistive memory device are provided. The resistive memory device includes a plurality of bit lines comprising at least one dummy bit line to which a plurality of resistive memory cells are connected, a conducting wire connected to the... Agent: Samsung Electronics Co., Ltd.

20130051118 - Single layer complementary memory cell: A single layer complementary memory cell includes a conductive base layer, a memristive matrix layer disposed onto the base layer, the memristive matrix comprising distinct memristive devices formed within. The memory cell further includes conductive lines disposed onto the memristive matrix that connect to the distinct memristive devices such that... Agent:

20130051121 - Switchable two-terminal devices with diffusion/drift species: Various embodiments of the present invention are directed to nanoscale electronic devices that provide nonvolatile memristive switching. In one aspect, a two-terminal device (600) comprises a first electrode (602), a second electrode (604), and an active region (606) disposed between the first electrode and the second electrode. The active region... Agent:

20130051122 - Variable-resistance memory device and driving method thereof: A variable-resistance memory device includes a memory array section including a main memory cell employing a storage element having a resistance increasing and decreasing in a reversible manner in accordance with application of a signal set at one of different polarities to the opposite ends of the storage element, and... Agent: Sony Corporation

20130051126 - Capacitors, apparatus including a capacitor and methods for forming a capacitor: Capacitors, apparatus including a capacitor, and methods for forming a capacitor are provided. One such capacitor may include a first conductor a second conductor above the first conductor, and a dielectric between the first conductor and the second conductor. The dielectric does not cover a portion of the first conductor;... Agent: Micron Technology, Inc.

20130051127 - Dram security erase: In a method of erasing data, a wordline of the DRAM array is set active, and signals develop on bitlines according to flows of charge between memory cells coupled to the wordline and the respective bitlines. Sense amplifiers connected to the respective bitlines can remain off such that the sense... Agent: Tessera, Inc.

20130051128 - Fly-over conductor segments in integrated circuits with successive load devices along a signal path: The propagation delay of a signal through multiple load devices coupled sequentially along a conductor is improved by separating a subset of the load devices that is more distant from the signal source, and coupling the more distant subset to the signal through a fly-over conductor that bypasses the subset... Agent: Taiwan Semiconductor Manufacturing Co., Ltd.

20130051129 - Memory device and systems including the same: The memory device includes a memory cell array, an access control circuit configured to access the memory cell array, a control signal generation circuit configured to generate a control signal for controlling an operation of the access control circuit, and a variable delay circuit configured to generate a delay signal... Agent: Samsung Electronics Co., Ltd.

20130051130 - Weak bit compensation for static random access memory: A static random access memory (SRAM) is provided. The SRAM includes a data line, a data line bar, and a current path block. The current path block includes at least two transistors configured to provide a current path for the data line in transition from a first logic voltage to... Agent: Taiwan Semiconductor Manufacturing Company, Ltd.

20130051131 - Sram read-write memory cell having ten transistors: A device and a method for controlling an SRAM-type device, including: a bistable circuit and two switching circuits respectively connecting two access terminals of the bistable circuit to two complementary bit lines in a first direction, each switching circuit including a first switch and a second switch in series between... Agent: St Microelectronics S.a.

20130051133 - Anti-fuse circuit using mtj breakdwon and semiconductor device including same: An anti-fuse circuit includes an array of anti-fuses. Each anti-fuse has a tunneling magneto-resistance (TMR) element series connected with a transistor, such that breakdown of a magnetic tunnel junction (MTJ) in response to an applied first voltage stores fuse information. A sensing circuit senses and amplifies respective output signals provided... Agent: Samsung Electronics Co., Ltd.

20130051135 - Compound cell spin-torque magnetic random access memory: A compound magnetic data storage cell, applicable to spin-torque random access memory (ST-RAM), is disclosed. A magnetic data storage cell includes a magnetic storage element and two terminals communicatively connected to the magnetic storage element. The magnetic storage element is configured to yield any of at least three distinct magnetoresistance... Agent: Seagate Technology LLC

20130051132 - Non-volatile semiconductor memory device: A non-volatile semiconductor memory device includes: a power supply unit; a memory cell array powered on or off by the power supply unit; and a read unit for reading data recorded on the memory cell array, wherein the data recorded on the memory cell array is not read in response... Agent: Samsung Electronics Co., Ltd.

20130051134 - Semiconductor recording device: The disclosed semiconductor recording device achieves multi-valued reading and writing using a spin-injection magnetization-reversal tunneling magnetoresistive element (TMR element). A first current that has at least the same value as that of the element requiring the highest current to reverse the magnetization thereof among a plurality of TMR elements is,... Agent:

20130051136 - Methods, apparatuses, and circuits for programming a memory device: Subject matter described pertains to methods, apparatuses, and circuits for programming a memory device.... Agent: Micron Technology, Inc.

20130051138 - Phase change memory: A phase change memory device including a voltage generator that generates an operating voltage by generating at least one modified clock signal, a pulse width of which is maintained constant for at least one clock cycle in response to a pump enable signal being enabled, from at least one reference... Agent: Samsung Electronics Co., Ltd.

20130051139 - Resetting phase change memory bits: After determining that a reset pulse has reached its programmed threshold voltage level, a lower voltage verify can be conducted. This can be followed by another program step to increase the programmed threshold voltage. By avoiding the need for subsequent verification after the cell has reached its desired threshold level,... Agent:

20130051137 - Tile-level snapback detection through coupling capacitor in a cross point array: Embodiments of the present disclosure describe methods, apparatus, and system configurations for tile-level snapback detection through a coupling capacitor in a phase-change memory array. Other embodiments may be described and claimed.... Agent:

20130051140 - Clock circuits and methods: Integrated circuits, apparatuses and methods are disclosed, such as a method that includes generating an internal clock signal, receiving an external clock signal, and providing a mixed clock signal at an output. The mixed clock signal has a frequency ranging from a defined maximum frequency of the external clock signal... Agent:

20130051141 - Threshold voltage compensation in a multilevel memory: Threshold voltages in a charge storage memory are controlled by threshold voltage placement, such as to provide more reliable operation and to reduce the influence of factors such as neighboring charge storage elements and parasitic coupling. Pre-compensation or post-compensation of threshold voltage for neighboring programmed “aggressor” memory cells reduces the... Agent: Micron Technology, Inc.

20130051142 - Memory with three transistor memory cell device: Memory, memory devices, and a method for a backup sequence are disclosed. In one such memory device, sense circuitry and page buffers are coupled between a three transistor memory cell device and a non-volatile memory device. Enable/disable gates enable selective access to the sense circuitry and page buffers by either... Agent: Micron Technology, Inc.

20130051143 - Memory cell coupling compensation: Methods for memory cell coupling compensation and apparatuses configured to perform the same are described. One or more methods for memory cell coupling compensation includes determining a state of a memory cell using a voltage that is changed in accordance with a first memory cell coupling compensation voltage, performing an... Agent: Micron Technology, Inc.

20130051145 - Semiconductor memory device and method of operating the same: A semiconductor memory device includes memory blocks that each include memory cells coupled to bit lines, a column masking circuit configured to output data change signals in response to an address signal indicating bit lines of selected columns among a plurality of columns, and an operation circuit configured to store... Agent:

20130051144 - Semiconductor storage device comprising electrically rewritable nonvolatile semiconductor memory: A semiconductor storage apparatus stores management information comprising, for each block of a nonvolatile semiconductor memory, information denoting at least one of a recent programming time, which is a time at which data is recently programmed to a block, and a recent erase time, which is a time at which... Agent: Hitachi, Ltd.

20130051146 - Three dimensional semiconductor memory device: A three-dimensional (3D) semiconductor memory device comprises memory cell strings each comprising at least one selection transistor and at least one memory cell, a first pass transistor group sharing a first well region and comprising a first selection line pass transistor connected to the selection transistor and a first world... Agent:

20130051147 - Nonvolatile semiconductor memory device: A nonvolatile semiconductor memory device includes bit lines, word lines, NAND strings, source lines, first and second select gate transistors, and a controller. After giving a first potential to the second select gate transistors, the controller gives a second potential lower than the first potential to the second select gate... Agent: Kabushiki Kaisha Toshiba

20130051149 - Apparatuses and methods of reprogramming memory cells: Apparatuses and methods for reprogramming memory cells are described. One or more methods for memory cell operation includes programming a number of memory cells such that each of the number of memory cells are at either a first program state or a second program state, the second program state having... Agent: Micron Technology, Inc.

20130051153 - Floating addressing of an eeprom memory page: A method for electrically programming a non-volatile memory in which a programming cycle includes prior addressing of memory cells from an initial address corresponding to a first row and a column of a memory plane. The method may include addressing the memory cells in a second consecutive row when the... Agent: Stmicroelectronics (rousset) Sas

20130051151 - Power circuit, flash memory system provided with the power circuit, and power supply method: A power circuit configured to supply an operating voltage to a memory controller configured to control a flash memory and an access to the flash memory, comprises an input side charging unit that is a charging unit configured to be charged by an input voltage that is supplied from the... Agent: Tdk Corporation

20130051148 - Read compensation for partially programmed blocks of non-volatile storage: Read compensation for partially programmed blocks of non-volatile storage is provided. In partially programmed blocks, the threshold voltage distributions may be shifted down relative to their final positions. Upon receiving a request to read a page that is stored in a block, a determination may be made whether the block... Agent:

20130051152 - Semiconductor memory device and method of operating the same: A method of operating a semiconductor memory device includes, applying a read voltage to a selected word line to which a selected memory cell is coupled and applying a pass voltage to non-selected word lines to which non-selected memory cells are coupled, reading data stored in the selected memory cell... Agent: Sk Hynix Inc.

20130051150 - Three-dimensional nand memory with stacked mono-crystalline channels: A three-dimensional (3D) non-volatile memory (NVM) array including spaced-apart horizontally-disposed bitline structures arranged in vertical stacks, each bitline structures including a mono-crystalline silicon beam and a charge storage layer entirely surrounding the beam. Vertically-oriented wordline structures are disposed next to the stacks such that each wordline structure contacts corresponding portions... Agent: Tower Semiconductor Ltd.

20130051154 - Method for and flash memory device having improved read performance: A Flash memory device operable under a single-bit or multiple-bit serial protocol is provided with a capability to determine the address boundary condition of an application from the address field of an address boundary configurable (“ABC”) read command. Based on the identified address boundary condition, the Flash memory device may... Agent:

20130051155 - Semiconductor memory device capable of shortening erase time: In a memory cell array, a plurality of memory cells connected to a plurality of word lines and a plurality of bit lines are arranged in a matrix. A control circuit controls the potentials of said plurality of word lines and said plurality of bit lines. In an erase operation,... Agent:

20130051156 - Systems and methods for erasing charge-trap flash memory: Disclosed herein are methods for erasing charge-trap FLASH memory devices containing at least one memory stack. The stack of transistors includes a first (or source) selector transistor, a second (or drain) selector transistor, and a plurality memory cell transistors connected in series therebetween. During an erase operation, each of the... Agent:

20130051162 - Coded differential intersymbol interference reduction: Encoder and decoder circuits that encode and decode a series of data words to/from a series of code words. The data words include L symbols. The code words include M symbols, where M is larger than L. A set of tightly coupled M links to convey respective symbols in each... Agent: Rambus Inc.

20130051157 - Semiconductor memory device and refresh method thereof: A semiconductor memory device includes a memory core configured to sequentially activate first and second banks in response to first and second bank active signals which are sequentially enabled in response to first and second enable signals when a self-refresh operation is to be performed, select a word line by... Agent: Hynix Semiconductor Inc.

20130051159 - High voltage generation circuit and semiconductor device including the same: A high voltage generation circuit includes a plurality of pumps configured to generate a final pump voltage, a plurality of switches configured to couple the pumps to various nodes, a voltage division circuit configured to divide the final pump voltage from the pumps interconnected by the switches, and outputting a... Agent: Sk Hynix Inc.

20130051158 - Integrated circuit, testing apparatus for integrated circuit, and method of testing integrated circuit: Provided are a redundant memory; a generator that generates a test pattern, and an expected value of data expected to be output from the redundant memory, in response to the test pattern being supplied to the redundant memory; a comparator that compares the expected value generated by the generator, against... Agent: Fujitsu Limited

20130051160 - Semiconductor device having redundant word lines and redundant bit lines: Disclosed herein is a device that includes a memory cell array having short and long sides, a row decoder, a row fuse circuit, a column decoder and a column fuse circuit. The row decoder, the row fuse circuit and the column fuse circuit are arranged along the long side of... Agent: Elpida Memory, Inc.

20130051161 - Apparatuses and methods including memory write operation: Some embodiments include apparatuses and methods having memory cells and access lines coupled to the memory cells. In one such apparatus, the access lines include a first access line and a second access line. The first access line can be adjacent to the second access line. The memory cells include... Agent:

20130051163 - Data transmission circuit and semiconductor memory device including the same: The data transmission circuit includes: a plurality of local bit line pairs through which data is read simultaneously; a plurality of voltage change detection circuits provided for the plurality of local bit line pairs; a global bit line pair; a plurality of column selection circuits configured to select one of... Agent: Panasonic Corporation

20130051164 - Nonvolatile memory devices and methods of driving the same: A method of driving a nonvolatile memory device including applying a reset voltage to a unit memory cell, reading a reset current of the unit memory cell, confirming whether the reset current is within a first current range, if the reset current is not within the first current range, changing... Agent: Samsung Electronics Co., Ltd.

20130051165 - Semiconductor apparatus and data transmission method thereof: A semiconductor apparatus includes a normal data line, an auxiliary data line and a data line selection unit. The normal data line is connected with a data selection unit. The auxiliary data line is connected with the data selection unit. The data line selection unit outputs data to one of... Agent: Hynix Semiconductor Inc.

20130051166 - Apparatuses and methods for compensating for power supply sensitivities of a circuit in a clock path: Apparatuses and methods for compensating for differing power supply sensitivities of a circuit in a clock path. One such method includes altering signal timing of at least one of reference and feedback clock signals differently according to variations in power supply voltage to compensate for differences in delay power supply... Agent: Micron Technology, Inc.

20130051167 - Semiconductor memory device and defective cell relieving method: A memory cell array of a first semiconductor chip includes a normal cell array and a spare cell array. A first defect address data output circuit outputs first defect address data indicating an address of a defective memory cell in the memory cell array. A first comparison circuit compares address... Agent: Kabushiki Kaisha Toshiba

20130051168 - Method and apparatus for sending test mode signals: A test mode signal system includes: a test mode block for generating a plurality, N, of test mode signals; a test mode send block, for generating and outputting a pulsed signal according to a command signal, and for multiplexing the N test mode signals in sets according to the pulsed... Agent:

20130051169 - Method of screening static random access memories for pass transistor defects: A method of screening static random access memory (SRAM) arrays to identify memory cells with bit line side pass transistor defects. After writing a known data state to the memory cells under test, a forward back-bias is applied to the load transistors of those cells. A write of the opposite... Agent: Texas Instruments Incorporated

20130051170 - Semiconductor memory device: In a static random access memory (SRAM) device having a hierarchical bit line architecture, a local sense amplifier (SA) circuit includes P-channel transistors which precharge local bit lines connected to memory cells, P-channel transistors each having a gate connected to a corresponding one of the local bit lines and a... Agent: Panasonic Corporation

20130051171 - Memory refresh methods, memory section control circuits, and apparatuses: Apparatuses, memory section control circuits, and methods of refreshing memory are disclosed. An example apparatus includes a plurality of memory sections and a plurality of memory section control circuits. Each memory section control circuit is coupled to a respective one of the plurality of memory sections and includes a plurality... Agent: Micron Technology, Inc.

20130051172 - Semiconductor memory device: A semiconductor memory device includes a power supply circuit configured to supply an intermediate voltage between a power supply voltage and a ground voltage to each of a plurality of memory cells. The power supply circuit firsts generates a first intermediate voltage between the power supply voltage and the ground... Agent: Renesas Electronics Corporation

20130044530 - Layout of memory cells and input/output circuitry in a semiconductor memory device: A semiconductor memory device includes a memory cell array divided into a plurality of subarrays arranged in matrix form, the plurality of subarrays making up a plurality of subarray columns, an address pad column formed outside the memory cell array, the address pad column comprising a plurality of address pads... Agent: Nec Electronics Corporation

20130044531 - Semiconductor memory devices: A semiconductor memory device includes a stacked structure including a plurality of wordline structures sequentially stacked that each include: a plurality of wordlines with sidewalls and extending in a first direction on the substrate, and a connecting pad extending in a second direction on the substrate and being connected in... Agent: Samsung Electronics Co., Ltd.

20130044534 - Forming method of performing forming on variable resistance nonvolatile memory element, and variable resistance nonvolatile memory device: A forming method of a variable resistance nonvolatile memory element capable of lowering a forming voltage and preventing variations of the forming voltage depending on variable resistance elements. The forming method is for initializing a variable resistance element, including a step (S24) of determining whether or not a current flowing... Agent:

20130044532 - Low temperature beol compatible diode having high voltage margins for use in large arrays of electronic components: A crystalline semiconductor Schottky barrier-like diode sandwiched between two conducting electrodes is in series with a memory element, a word line and a bit line, wherein the setup provides voltage margins greater than 1V and current densities greater than 5×106 A/cm2. This Schottky barrier-like diode can be fabricated under conditions... Agent: International Business Machines Corporation

20130044533 - Memory array with co-planar waveguide based memory element selection: A memory array with co-planar waveguide based memory selection includes a first set of parallel conductive lines placed perpendicular to a second set of parallel conductive lines, memory elements disposed at intersections between the first set of conductive lines and the second set of conductive lines, and selection circuitry to... Agent:

20130044535 - Reference cell circuit and variable resistance nonvolatile memory device including the same: Included are reference cells each including a variable resistance element which reversibly changes between a predetermined low resistance state LR and a predetermined high resistance state HR according to an application of an electric signal, a comparator which compares resistance values of the reference cells, a pulse generation circuit which... Agent:

20130044536 - Array-based integrated circuit with reduced proximity effects: An integrated circuit and method of generating a layout for an integrated circuit in which circuitry peripheral to an array of repetitive features, such as memory or logic cells, is realized according to devices constructed similarly as the cells themselves, in one or more structural levels. The distance over which... Agent: Texas Instruments Incorporated

20130044537 - Magnetic memory, method of manufacturing the same, and method of driving the same: There is provided a magnetic memory with using a magnetoresistive effect element of a spin-injection magnetization reversal type, in which a multi-value operation is possible and whose manufacturing and operation are simple. A preferred aim of this is solved by providing two or more magnetoresistive effect elements which are electrically... Agent:

20130044538 - Stacked mram device and memory system having the same: Provided is a stacked magnetic random access memory (MRAM) in which memory cell arrays having various characteristics or functions are included in memory cell layers. The stacked MRAM device includes a semiconductor substrate and at least one memory cell layers. The semiconductor substrate includes a first memory cell array. Each... Agent:

20130044539 - Apparatuses, devices and methods for sensing a snapback event in a circuit: Example subject matter disclosed herein relates to apparatuses and/or devices, and/or various methods for use therein, in which an application of an electric potential to a circuit may be initiated and subsequently changed in response to a determination that a snapback event has occurred in a circuit. For example, a... Agent: Micron Technology, Inc.

20130044540 - Programming at least one multi-level phase change memory cell: An apparatus for programming at least one multi-level Phase Change Memory (PCM) cell having a first terminal and a second terminal A programmable control device controls the PCM cell to have a respective cell state by applying at least one current pulse to the PCM cell, the control device controlling... Agent: International Business Machines Corporation

20130044541 - Magnetic random access memory: A magnetic random access memory is configured as a read/write memory and at least a first section of the magnetic random access memory is configured to be converted to a read only memory.... Agent: Intel Mobile Communications Gmbh

20130044542 - Method of sorting a multi-bit per cell non-volatile memory and a multi-mode configuration method: A method of sorting a multi-bit per cell non-volatile memory includes programming and reading to test an n-bit-per-cell (n-bpc) non-volatile memory, which has a plurality of m-bpc pages, where m is a positive integer from 1 through n. If the m-bpc page fails the test, counting a block associated with... Agent: Skymedi Corporation

20130044543 - Non-volatile memory bank and page buffer therefor: A memory system having a serial data interface and a serial data path core for receiving data from and for providing data to at least one memory bank as a serial bitstream. Each half of the memory bank is divided into upper and lower sectors. Each sector provides data in... Agent: Mosaid Technologies Incorporated

20130044545 - Non-volatile memory device having vertical structure and method of operating the same: A non-volatile memory device having a vertical structure includes a NAND string having a vertical structure. The NAND string includes a plurality of memory cells, and at least one pair of first selection transistors arranged to be adjacent to a first end of the plurality of memory cells. A plurality... Agent:

20130044544 - Nonvolatile memory device: n

20130044546 - Determining system lifetime characteristics: The present disclosure includes methods and systems for determining system lifetime characteristics. A number of embodiments include a number of memory devices and a controller coupled to the number of memory devices. The controller can be configured to perform a number of operations on the number of memory devices using... Agent: Micron Technology, Inc.

20130044547 - Device, method and computer readable program for accessing memory cells using shortened read attempts: A device, a computer readable medium and a method that may include performing a shortened read attempt of multiple data memory cells that store data to provide an estimate of the data; wherein the shortened read attempt has a duration that is shorter than a duration of a full read... Agent: Technion Research And Development Foundation Ltd.

20130044548 - Flash memory and memory cell programming method thereof: A flash memory and a memory cell programming method thereof are provided. The programming method includes the following steps. A preset programming voltage is applied to a memory cell to program the memory cell. A first verify voltage is applied to the memory cell to detect a programming result of... Agent: Ememory Technology Inc.

20130044549 - Apparatus and methods including source gates: Apparatus and methods are disclosed, such as an apparatus that includes a string of charge storage devices associated with a pillar (e.g., of semiconductor material), a source gate device, and a source select device coupled between the source gate device and the string. Additional apparatus and methods are described.... Agent:

20130044550 - Memory array having word lines with folded architecture: According to an exemplary embodiment, a memory array arrangement includes a plurality of word lines, where at least two of the plurality of word lines are concurrently active word lines. Each of the plurality of word lines drive at least one group of columns. The memory array arrangement also includes... Agent: Broadcom Corporation

20130044551 - Semiconductor memory device: A semiconductor memory device includes a memory cell connected to a read bit line and a pair of write bit lines, and a data amplifier connected to the read bit line. A precharge potential resetting circuit uses a function of generating precharge potentials to the pair of write bit lines... Agent: Panasonic Corporation

20130044552 - Strobe-offset control circuit: A method of operation in a memory controller is disclosed. The method includes receiving a strobe signal having a first phase relationship with respect to first data propagating on a first data line, and a second phase relationship with respect to second data propagating on a second data line. A... Agent: Rambus Inc.

20130044553 - Integrated circuit, system including the same, and operation method of the system: A system includes a first chip configured to supply a training command and a second chip configured to transfer to the first chip a measured time for performing an operation in response to the training command.... Agent:

20130044554 - Dram repair architecture for wide i/o dram based 2.5d/3d system chips: A 2.5D or 3D repair architecture includes a logic die, and a memory die. In the 2.5D architecture, the logic die and memory die are mounted on an interposer. In the 3D architecture, the memory die is mounted on the logic die. The logic has a control logic wrapped with... Agent: Taiwan Semiconductor Manufacturing Co., Ltd.

20130044555 - Processor with memory delayed bit line precharging: A processor includes an array of memory cells, a control module, a precharge circuit, and an amplifier module. The control module generates a clock signal at a first rate, reduces the first rate to a second rate for a predetermined period, and adjusts the second rate back to the first... Agent: Marvell World Trade Ltd.

20130044556 - Sense amplifier scheme for low voltage sram and register files: In at least one embodiment, a sense amplifier circuit includes a pair of bit lines, a sense amplifier output, a keeper circuit, and a noise threshold control circuit. The keeper circuit is coupled to the pair of bit lines and includes an NMOS transistor coupled between a power node and... Agent: Taiwan Semiconductor Manufacturing Company, Ltd.

20130044557 - Memory control method of memory device and memory control system thereof: One exemplary memory control method of a memory device includes: assigning an indicator to each physical row partition in the memory device for indicating if the corresponding physical row partition is to be refreshed; and controlling a partial refresh operation of the memory device according to the indicator of each... Agent: Mediatek Inc.

20130044558 - Memory device and method: A memory module decodes an address to determine a one or more wordline select pattern, or other spatial select pattern. An encoder determines an encoded value based upon the wordline select pattern that is compared to an expected encode value. The encode value has fewer than twice the number of... Agent: Freescale Semiconductor, Inc.

20130039109 - Selectable multi-way comparator: A method for comparing content addressable memory (CAM) elements is disclosed. Binary values are stored in a pair of CAM elements. A comparison value is provided to a group of comparators, the comparison value based on the binary value stored in the pair of CAM elements. A match value is... Agent: Advanced Micro Devices, Inc.

20130039110 - 3d architecture for bipolar memory using bipolar access device: Memory device and method for fabricating a memory device on two layers of a semiconductor wafer. An example device includes bit lines and word lines fabricated at one layer of a semiconductor wafer and re-writable nonvolatile memory cells that include a two-terminal access device with a bidirectional voltage-current characteristics for... Agent: International Business Machines Corporation

20130039111 - Connection and addressing of multi-plane crosspoint devices: A multi-plane circuit structure has at least a first circuit plane and a second circuit plane, and each circuit plane has a plurality of row wire segments, a plurality of column wire segments, and a plurality of crosspoint devices formed at intersections of the row wire segments and the column... Agent:

20130039112 - Semiconductor device: In a semiconductor device of a stacked structure type having a control chip and a plurality of controlled chips, wherein the control chip allocates different I/O sets to the respective controlled chips and processes the I/O sets within the same access cycle, the controlled chip close to the control chip... Agent: Elpida Memory, Inc.

20130039113 - Integrated dram memory device: A DRAM memory device includes at least one memory cell including a transistor having a first electrode, a second electrode and a control electrode. A capacitor is coupled to the first electrode. At least one electrically conductive line is coupled to the second electrode and at least one second electrically... Agent: Stmicroelectronics (crolles 2) Sas

20130039115 - Field programmable read-only memory device: The field programmable read-only memory device comprises a memory cell having a switching element for storing bit information. The switching element provides a switchable electrical connection between word line and a bit line and comprises a static body and a moveable connecting element. The switchable electrical connection is non-volatile.... Agent:

20130039116 - Programmable read-only memory device and method of writing the same: A bit cell of the PROM-device comprises a carbon nanotube having a tilted portion comprising a free end and a fixed portion which is to the reference node. The carbon nanotube comprises a structural defect between the fixed and the tilted portion which causes the carbon nanotube to tilt such... Agent:

20130039114 - Writing circuit, semiconductor integrated circuit and writing method: A writing circuit includes storage to store writing data to be written to an OTP macro; a controller to apply a first signal that causes the OTP macro to execute writing of the writing data, and apply a second signal that causes the OTP macro to execute reading of data... Agent: Fujitsu Limited

20130039117 - Electrical fuse bit cell: An electrical fuse (eFuse) bit cell includes a program transistor, a read transistor, and an eFuse. The program transistor has a first program terminal, a second program terminal, and a third program terminal. The read transistor has a first read terminal, a second read terminal, and a third read terminal.... Agent: Taiwan Semiconductor Manufacturing Company, Ltd.

20130039119 - Memory cell that includes multiple non-volatile memories: A system and method to read and write data at a memory cell that includes multiple non-volatile memories is disclosed. In a particular embodiment, a memory device includes a plurality of memory cells. At least one of the memory cells includes a first non-volatile memory including a first resistive memory... Agent: Qualcomm Incorporated

20130039118 - Semiconductor memory device having diode cell structure: A semiconductor memory device comprises a memory cell, first and second voltage generating circuits generating first and second voltages, and a control circuit. A memory element and a diode included in the memory cell are connected in series between first and second lines. The first voltage has no temperature dependence,... Agent: Elpida Memory Inc.

20130039120 - Static ram: A static RAM includes: a plurality of word lines; a plurality of pairs of local bit lines; a plurality of memory cells arranged in correspondence with intersections of the plurality of pairs of local bit lines and the plurality of word lines; a capacitance shared circuit arranged for each of... Agent: Fujitsu Semiconductor Limited

20130039121 - Magnetic tunnel junction and spin transfer torque random access memory having the same: A magneto-resistance memory device includes a first pinned layer having a first magnetic polarity regardless of current applied to the first pinned layer, a first tunnel insulating layer arranged on the first pinned layer, a first free layer arranged on the first tunnel insulating layer and having a magnetic polarity... Agent:

20130039122 - Magnetoresistive random access memory: A magnetoresistive random access memory includes a memory cell line in which memory cells are formed and write bit lines. The memory cell line 1 includes a magnetic recording layer, magnetization fixed layers, reference layers, spacer layers, and nMOS transistors. The spacer layer and the reference layer are located between... Agent: Renesas Electronics Corporation

20130039123 - Nonvolatile memory cell, nonvolatile memory device and method for driving the same: A nonvolatile memory cell is able to reduce the size per the unit area by employing a dual gate structure where the chalcogenide compound is used for a channel. The nonvolatile memory cell includes a phase-change layer, a first and a second gate that are in contact with sides of... Agent:

20130039124 - Phase change random access memory device and related methods of operation: A method of operating a phase change random access memory (PRAM) device includes performing a program operation to store data in selected PRAM cells of the device, wherein the program operation comprises a plurality of sequential program loops. The method further comprises suspending the program operation in the middle of... Agent:

20130039125 - Flash memory program inhibit scheme: A method for minimizing program disturb in Flash memories. To reduce program disturb in a NAND Flash memory cell string where no programming from the erased state is desired, a local boosted channel inhibit scheme is used. In the local boosted channel inhibit scheme, the selected memory cell in a... Agent: Mosaid Technologies Incorporated

20130039126 - Semiconductor memory device for storing multivalued data: Data storage circuits are connected to the bit lines in a one-to-one correspondence. A write circuit writes the data on a first page into a plurality of 5 first memory cells selected simultaneously by a word line. Thereafter, the write circuit writes the data on a second page into the... Agent:

20130039128 - Non-volatile dynamic random access memory system with non-delay-lock-loop mechanism and method of operation thereof: A method of operation of a non-volatile dynamic random access memory system including: accessing a dynamic random access memory; managing a delay-locked-loop control in the dynamic random access memory; sourcing timing inputs to the dynamic random access memory by a control logic unit with the delay-locked-loop control disabled including: selecting... Agent: Smart Modular Technologies, Inc.

20130039127 - Non-volatile static random access memory devices and methods of operations: Non-Volatile Static Random Access Memory (NVSRAM) cell devices applying only one single non-volatile element embedded in a conventional Static Random Access Memory (SRAM) cell are disclosed. The NVSRAM cell devices can be integrated into a compact cell array. The NVSRAM devices of the invention have a read/write speed of a... Agent: Flash Silicon Incorporation

20130039129 - Memory devices and configuration methods for a memory device: Memory devices and methods of operating memory devices are disclosed. In one such method, different blocks of memory cells have different configurations of user data space and overhead data space. In at least one method, overhead data is distributed within more than one block of memory cells. In another method,... Agent: Micron Technology, Inc.

20130039130 - Program method of nonvolatile memory device: Disclosed is a program method of a nonvolatile memory device including applying a first program voltage to a word line of a memory cell; verifying a variation of a threshold voltage of the memory cell; and applying a second program voltage to a memory cell having a threshold voltage higher... Agent:

20130039131 - Systems and methods involving multi-bank, dual- or multi-pipe srams: Systems and methods are disclosed for increasing the performance of static random access memory (SRAM). Various systems herein, for example, may include or involve dual- or multi-pipe, multi-bank SRAMs, such as Quad-B2 SRAMs. In one illustrative implementation, there is provided an SRAM memory device including a memory array comprising a... Agent:

20130039133 - Data storage for voltage domain crossings: According to an embodiment, an apparatus includes a data storage device. Data to be stored in the data storage device is level shifted from a first voltage domain to a second voltage domain prior to being stored within the data storage device. The data storage device is powered by the... Agent: Qualcomm Incorporated

20130039132 - Line driver circuits, methods, and apparatuses: Described embodiments are directed to line drivers, such as those for providing reduced gate induced drain leakage in a memory array. Corresponding methods of operation of line drivers are also disclosed.... Agent:

20130039134 - Semiconductor device including memory capable of reducing power consumption: A semiconductor device includes a plurality of memory arrays and a plurality of memory array control circuits. Each of the plurality of memory array control circuits includes a read/write control circuit for controlling a read/write operation for the memory array, and a selection circuit for selecting and activating the memory... Agent:

20130039135 - Memory device for managing timing parameters: A method of performing write operations in a memory device including a plurality of banks is performed. Each bank includes two or more sub-banks including at least a first sub-bank and a second sub-bank. The method comprises: performing a first row cycle for writing to a first word line of... Agent:

20130039136 - Semiconductor device and semiconductor memory device: A semiconductor device includes a memory cell, a first bit line coupled to the memory cell, a second bit line, a first sense amplifier circuit including first and second transistors, the first transistor including a gate coupled to the first bit line, and the first and second transistors are coupled... Agent: Elpida Memory, Inc.

20130039137 - Semiconductor memory device: A Static Random Access Memory (SRAM) includes word lines WL, bit lines BL, address decoders that select one of the word lines WL in response to an address signal AD, a sense amplifier that is activated in response to a sense amplifier enable signal SAE, and a sense amplifier control... Agent: International Business Machines Corporation

20130039138 - Methods for providing redundancy and apparatuses: Methods for providing redundancy and apparatuses are disclosed. One such method for providing redundancy performs a mapping of data between an address of a memory determined to indicate a defective memory cell and an address of a redundant area of the memory, only after the data has been loaded into... Agent: Micron Technology, Inc.

20130039140 - Macro and command execution from memory array: Methods and apparatus for executing internal operations of memory devices utilizing instructions stored in the memory array of the memory device are disclosed. Decode blocks adapted to interpret instructions and data stored in the memory device are also disclosed. Methods can be used to perform internal self-test operations of the... Agent: Micron Technology, Inc.

20130039139 - Method of stressing static random access memories for pass transistor defects: A method of stressing and screening static random access memory (SRAM) arrays to identify memory cells with bit line side pass transistor defects. After writing initial data states into the memory array under nominal bias conditions, an elevated bias voltage is applied to the memory array, for example to its... Agent: Texas Instruments Incorporated

20130039141 - Apparatus, system, and method for power reduction management in a storage device: An apparatus, system, and method are disclosed for power reduction management. The method includes determining that a power source has failed to supply electric power above a predefined threshold. The method includes terminating one or more non-essential in-process operations on a nonvolatile memory device during a power hold-up time. The... Agent: Fusion-io

20130039142 - Input buffer circuit, semiconductor memory device and memory system: An input buffer circuit includes a logic unit, a clock enable buffer, and a clock buffer. The logic unit is configured to receive a clock signal and a clock enable signal, and to output a decision signal indicative of whether the clock signal is normally input, where the decision signal... Agent:

20130039143 - Semiconductor memory device, semiconductor system including the semiconductor memory device, and method for operating the semiconductor memory device: A semiconductor memory device includes a first data input/output unit configured to receive a normal training data, whose data window is scanned based on an edge of a source clock, in response to a training input command, and output a data in a state where an edge of the data... Agent: Sk Hynix Inc.

20130039144 - Multiple device apparatus, systems, and methods: Apparatus, systems, and methods are disclosed that operate to generate a clock signal in a die in a stack and to receive the clock signal in another die in the stack. Additional apparatus, systems, and methods are disclosed.... Agent: Micron Technology, Inc.

20130033915 - Content addressable memories with wireline compensation: What is disclosed is a novel memory array and process for creating a memory array to reduce wireline variability. The method includes accessing a routing design of a memory array with a plurality of memory cells. Each memory cell in the array includes one or more access devices, and a... Agent: International Business Machines Corporation

20130033916 - Semiconductor device having plural circuit blocks that operate the same timing: Disclosed herein is a device that includes first and second ports arranged in a first direction and first and second circuits arranged between the first and second ports. The first and second ports are coupled to the first and second circuits, respectively. The first and second circuits include first and... Agent: Elpida Memory, Inc.

20130033917 - Reader for magnetic shift register: A reader for magnetic shift register is provided. The reader includes a magnetic reference layer, a tunneling layer, a magnetic canceling layer and an isolated layer. The magnetic reference layer and the magnetic canceling layer are respectively configured at different sides of a magnetic track for providing anti-parallel magnetic fields.... Agent: Industrial Technology Research Institute

20130033918 - Method and structure for ultra-high density, high data rate ferroelectric storage disk technology using stabilization by a surface conducting layer: A electrometric access head includes a supporting substrate and a plurality of read elements mounted on the supporting substrate. Each read element includes an electrometric sensor for detection of a sign of polarization of domains within a ferroelectric data layer of a ferroelectric storage medium. The ferroelectric data layer serves... Agent: International Business Machines Corporation

20130033923 - Circuit for concurrent read operation and method therefor: A non-volatile memory device includes an array of memory units, each having resistive memory cells and a local word line. Each memory cell has a first and a second end, the second ends are coupled to the local word line of the corresponding memory unit. Bit lines are provided, each... Agent: Crossbar, Inc.

20130033920 - Ionic devices containing a membrane between layers: A device contains a first layer (420), a second layer (440); and a membrane (430) between the first and second layers (420, 440). Mobile ions (425) are in at least one of the first and second layers (420, 440), and the membrane (430) is permeable to the ions. Interfaces of... Agent:

20130033919 - Nonvolatile memory system and program method thereof: A nonvolatile memory system and a program method thereof are provided. The nonvolatile memory system includes a nonvolatile memory cell array, an input/output (I/O) control circuit configured to control a program or read operation for the nonvolatile memory cell array; and a controller configured to store an equation representing a... Agent:

20130033922 - Resistive-switching device capable of implementing multiary addition operation and method for multiary addition operation: The present disclosure provides a resistive-switching device capable of implementing multiary addition operation and a method for implementing multiary addition operation using the resistive-switching device. The resistive-switching device has a plurality of resistance values each corresponding to a respective data value stored by the resistive-switching device and ranging from a... Agent: Peking University

20130033921 - Semiconductor device: A semiconductor device using resistive random access memory (ReRAM) elements and having improved tamper resistance is provided. The semiconductor device is provided with a unit cell which stores one bit of cell data and a control circuit. The unit cell includes n ReRAM elements (n being an integer of 2... Agent: Renesas Electronics Corporation

20130033924 - Code coverage circuitry: A circuit includes a memory (130) coupled to an analog line coverage circuit (104). The analog line coverage circuit includes a plurality of buffers (151-154) in which each buffer is coupled to one memory location of the memory, a plurality of bin cells (161-164) in which each bin cell is... Agent: Freescale Semiconductor, Inc.

20130033925 - Semiconductor device: An object is to provide a semiconductor device having a novel structure. A first wiring; a second wiring; a third wiring, a fourth wiring; a first transistor including a first gate electrode, a first source electrode, and a first drain electrode; a second transistor including a second gate electrode, a... Agent: Semiconductor Energy Laboratory Co., Ltd.

20130033926 - Semiconductor memory device having balancing capacitors: A semiconductor memory device includes a plurality of memory cell blocks including a first memory cell block having bit lines, an edge sense amplifier block including edge sense amplifiers coupled to a portion of the bit lines of the first memory cell block, and a balancing capacitor unit coupled to... Agent: Samsung Electronics Co., Ltd.

20130033927 - Magentic resistance memory apparatus having multi levels and method of driving the same: A magnetic resistance memory apparatus capable of implementing various levels and a method of driving the same are provided. The magnetic resistance memory apparatus includes a first magnetic device that includes a fixed layer having a fixed magnetization direction, a tunnel layer disposed on the fixed layer, and a first... Agent:

20130033928 - Semiconductor storage device and data processing method: Since a nonvolatile RAM allows random reading and writing operations, an erasing mode is unnecessary. From the system side, however, it is desirable to have the erasing mode because of its nonvolatile characteristic. Moreover, the erasing operation is desirably carried out at high speed with low power consumption. Therefore, memory... Agent:

20130033930 - Supply voltage generating circuit and semiconductor device having the same: A supply voltage generating circuit includes a first charge pump circuit that generates a first internal supply voltage, and second charge pump circuit that generates a second internal supply voltage. The absolute value of the second internal supply voltage is greater than that of the first internal supply voltage. The... Agent: Elpida Memory, Inc.

20130033929 - Write scheme in a phase change memory: In a phase change memory, an input data corresponding to a plurality of memory cells is received and a previous data is read from the plurality of memory cells. The input data is compared with the previous data. In the case where the input data is different from the previous... Agent: Mosaid Technologies Incorporated

20130033931 - Storage element and storage device: Provided is a storage element including a storage layer that holds information according to a magnetization state of a magnetic body, a magnetization fixing layer that has magnetization serving as a reference of the information stored in the storage layer, and an insulation layer that is formed of a non-magnetic... Agent: Sony Corporation

20130033932 - Nonvolatile semiconductor memory device and method for driving same: According to one embodiment, a nonvolatile semiconductor memory device includes a memory unit and a control unit. The memory unit includes a charge storage film and a memory cell transistor. The transistor is provided for each of storage regions configured to store charge in the film. The control unit sets... Agent:

20130033933 - Adjusting operational parameters for memory cells: Techniques and devices relating to adjusting one or more operational parameters for memory cells are provided. One such device may include a detection unit configured to perform one or more reading operations on a set of memory cells to determine an upper bound of the threshold voltages of the set... Agent:

20130033934 - Memory cell arrangement, method for controlling a memory cell, memory array and electronic device: In an embodiment of the invention, a memory cell arrangement includes a substrate and at least one memory cell including a charge storing memory cell structure and a select structure. The memory cell arrangement further includes a first doping well, a second doping well and a third doping well arranged... Agent: Infineon Technologies Ag

20130033935 - Memory die self-disable if programmable element is not trusted: Techniques are disclosed herein for automatically self-disabling a memory die in the event that a programmable element on the memory die for indicating whether the memory die is defective cannot be trusted. Memory die are provided with chip enable circuitry to allow particular memory die to be disabled. If the... Agent:

20130033936 - Methods to operate a memory cell: Memory devices and methods for operating a memory cell are disclosed, such as a method that uses two program verify levels (e.g., low program verify level and program verify level) to determine how a data line voltage should be increased. A threshold voltage of a memory cell that has been... Agent: Politecnico Di Milano

20130033937 - Methods for program verifying a memory cell and memory devices configured to perform the same: A method for program verify is disclosed, such as one in which a threshold voltage of a memory cell that has been biased with a programming voltage can be determined and its relationship with multiple program verify voltage ranges can be determined. The program verify voltage range in which the... Agent: Politecnico Di Milano

20130033938 - Nonvolatle memory device and related programming method: A nonvolatile memory device is programmed by performing a plurality of program loops each comprising applying a program voltage to a selected wordline to change a threshold voltage of a selected memory cell, and applying a verification voltage to the selected wordline to verify a program state of the selected... Agent: Samsung Electronics Co., Ltd.

20130033939 - Functional data programming and reading in a memory: Methods for functional programming memory cells and apparatuses are disclosed. One such method for functional programming includes encoding a group of data with a function to generate representative data and programming the representative data to the memory. In one embodiment, the representative data is a pattern of threshold voltages to... Agent: Micron Technology, Inc.

20130033940 - Apparatus and methods of bit line setup: Methods and apparatus are disclosed, including an apparatus that has a memory cell array with a memory cell selectively coupled to a bit line. A control circuit is configured to provide a control signal. A voltage generator is configured to provide a sense signal and a precharge signal in response... Agent:

20130033941 - Non-volatile semiconductor memory having multiple external power supplies: A memory device includes core memory such as flash memory for storing data. The memory device includes a first power input to receive a first voltage used to power the flash memory. Additionally, the memory device includes a second power input to receive a second voltage. The memory device includes... Agent: Mosaid Technologies Incorporated

20130033943 - Data input/output circuit and semiconductor memory device: A data input/output circuit includes: an amplification unit configured to generate a data signal by amplifying data of a first input/output line coupled to a bank during a read operation, and generate a driving signal by amplifying data of a second input/output line coupled to a data input/output pad during... Agent: Hynix Semiconductor Inc.

20130033942 - System-in package including semiconductor memory device and method for determining input/output pins of system-in package: A semiconductor memory device includes an internal clock generation unit configured to generate an internal clock including periodic pulses during a period of a test mode; a DQ information signal generation block configured to generate DQ information signals which are sequentially enabled, in response to the internal clock; and a... Agent: Hynix Semiconductor Inc.

20130033944 - Internal voltage generation circuit: An internal voltage generation circuit includes: a selection unit configured to select one of first and second reference voltages as a selection reference voltage in response to a self refresh signal and a power-down mode signal and output the selection reference voltage; a driving signal generation unit configured to compare... Agent: Hynix Semiconductor Inc.

20130033945 - System and method for interfacing burst mode devices and page mode devices: A burst read control circuit acts as an interface to allow a burst-read capable device to execute burst reads from a page-mode capable memory device. The burst read control circuit coordinates burst read requests from the burst-read capable device and subsequent responses from the page-mode capable memory device by accessing... Agent: Hamilton Sundstrand Corporation

20130033946 - Frequency-agile strobe window generation: The disclosed embodiments relate to components of a memory system that support frequency-agile strobe enable window generation during read accesses. In specific embodiments, this memory system contains a memory controller which includes a timing circuit to synchronize a timing-enable signal with a timing signal returned from a read path, wherein... Agent: Rambus Inc.

20130033947 - Clock generator: Disclosed herein is a clock generator that comprises a master or first oscillator having an output terminal which provides a master clock signal and at least one slave or second oscillator having an output terminal which provides a slave clock signal, the master and slave oscillators comprising respective time delay... Agent: Elpida Memory, Inc.

20130033948 - Device and method for detecting resistive defect: The invention provides a device and method for detecting a resistive defect in a static random access memory (SRAM) device. A first aspect of the invention provides a static random access memory (SRAM) device comprising: a bitline; a wordline; a bitline precharge circuit electrically connected to the bitline and adapted... Agent: International Business Machines Corporation

20130033949 - Data control circuit: The data control circuit includes an input/output line and a driver. The input/output line precharging circuit precharges a global input/output line to a predetermined voltage when either a reading operation or a writing operation is inoperative. The driver includes a number of MOS transistors and drives the global input/output line... Agent: Hynix Semiconductor Inc.

20130033950 - Apparatus and method for refreshing dram: A refresh method for DRAM is provided, in which a memory cell array is arranged to have multiple storing pages. Each storing page has a counter value. The method includes detecting out a portion of the storing pages being no longer used, indicated as a “no-use portion”, and another portion... Agent: Novatek Microelectronics Corp.

20130033951 - Structure and method for storing multiple repair pass data into a fusebay: Fuse macros of identical number of pages are serially arranged to form the same number of fusebay pages each having a length equal to the sum of the respective fuse macro page lengths. Each fuse macro has an enable latch configured to allow activation of one fuse macro at a... Agent: International Business Machines Corporation

20130033953 - Computer motherboard and voltage adjustment circuit thereof: A voltage adjustment circuit includes a south bridge, a complex programmable logic device (CPLD), a power supply unit, a voltage conversion unit, and a resistance unit. The south bridge detects a type of a number of dynamic random access memories (DRAMs), and outputs a corresponding signal according to a detected... Agent: Hong Fu Jin Precision Industry (shenzhen) Co., Ltd.

20130033952 - Semiconductor memory device: A semiconductor memory device includes: a reference voltage generation unit configured to generate first and second reference voltages, wherein a level of the first reference voltage increases with decreasing internal temperature, and a level of the second reference voltage decreases with decreasing internal temperature; and a level control unit configured... Agent: Hynix Semiconductor Inc.

20130033954 - Memory buffers and modules supporting dynamic point-to-point connections: A memory module comprises a module interface having module data-group ports to communicate data as respective data groups, a command port to receive memory-access commands, a first memory device including a first device data-group port, a second memory device including a second device data-group port, and a signal buffer coupled... Agent: Rambus Inc.