|Static information storage and retrieval patents - Monitor Patents|
USPTO Class 365 | Browse by Industry: Previous - Next | All
12/2012 | Recent | 15: May | Apr | Mar | Feb | Jan | 14: Dec | Nov | Oct | Sep | Aug | Jul | Jun | May | Apr | Mar | Feb | Jan | 13: Dec | Nov | Oct | Sep | Aug | Jul | Jun | May | Apr | Mar | Feb | Jan | 12: Dec | Nov | Oct | Sep | Aug | July | June | May | April | Mar | Feb | Jan | 11: Dec | Nov | Oct | Sep | Aug | Jul | Jun | May | Apr | Mar | Feb | Jan | 10: Dec | Nov | Oct | Sep | Aug | Jul | Jun | May | Apr | Mar | Feb | Jan | | 09: Dec | Nov | Oct | Sep | Aug | Jl | Jn | May | Apr | Mar | Fb | Jn | | 2008 | 2007 |
Static information storage and retrieval December patent applications/inventions, industry category 12/12Below are recently published patent applications awaiting approval from the USPTO. Recent week's RSS XML file available below.
Listing for abstract view: USPTO application #, Title, Abstract excerpt,Patent Agent. Listing format for list view: USPTO National Class full category number, title of the patent application. 12/27/2012 > 41 patent applications in 33 patent subcategories.
20120327696 - Content addressable memory array having virtual ground nodes: Power consumption of CAM devices is reduced during compare operations between a search key and data stored in the device's array by reducing the amount of electric charge by which the match line is discharged during mismatch conditions. More specifically, for some embodiments, each row of the CAM array includes... Agent:
20120327697 - Distributed flash memory storage manager systems: A flash memory storage system may include several modules of flash memory storage manager circuitry, each having some associated flash memory. The modules may be interconnected via the flash memory storage manager circuitry of the modules. The system may be able to write data to and/or read data from the... Agent:
20120327698 - Interconnection architecture for memory structures: An interconnect architecture for connecting read/write circuitry to a memory structure, the interconnect architecture includes a switching layer having a number of access switches arranged in at least one set of two offset switch blocks, the access switches being connected to a first set of parallel wire tracks and a... Agent:
20120327699 - Word line fault detection: In a memory having a word line driver and a ROM having N bit positions and a plurality of rows in which each row is coupled to a corresponding word line of the word line driver and stores a unique N bit value, a method includes activating, by the word... Agent:
20120327700 - Low voltage metal gate antifuse with depletion mode mosfet: An antifuse according to an embodiment of the invention herein can include a depletion mode metal oxide semiconductor field effect transistor (“MOSFET”) having a conduction channel and a metal gate overlying the conduction channel. A cathode and an anode of the antifuse can be electrically coupled to the gate and... Agent: International Business Machines Corporation
20120327701 - Memory array architecture with two-terminal memory cells: A non-volatile memory device includes a word line extending along a first direction; a bit line extending along a second direction; a memory unit having a read transistor coupled to the bit line, at least one two-terminal memory cell, and a select transistor, the two-terminal memory cell having a first... Agent: Crossbar, Inc.
20120327702 - Nonvolatile memory element and nonvolatile memory device: A nonvolatile memory element includes: a first electrode layer; a second electrode layer; and a variable resistance layer which is placed between the electrode layers, and whose resistance state reversibly changes between a high resistance state and a low resistance state based on a polarity of a voltage applied between... Agent:
20120327703 - Random access memory controller having common column multiplexer and sense amplifier hardware: Systems and methods are provided for a random access memory controller. A random access memory controller includes a column multiplexer and sense amplifier pair, where the column multiplexer and sense amplifier pair includes a column multiplexer and a sense amplifier that are configured to utilize common circuitry. The common circuitry... Agent:
20120327705 - Data-aware sram systems and methods forming same: Exemplary embodiments for SRAM cells, new control units for SRAM systems, and embodiments of SRAM systems are described herein. An SRAM cell is configured to receive a first input voltage signal and a second input voltage signal with a different value from the first input voltage signal, and to maintain... Agent: Taiwan Semiconductor Manufacturing Company, Ltd.
20120327704 - Semiconductor memories: A semiconductor memory includes a bit cell having first and inverters forming a latch. First and second transistors are respectively coupled to first and second storage nodes of the latch and to first and second write bit lines. Each of the first and second transistors has a respective gate coupled... Agent: Taiwan Semiconductor Manufacturing Co., Ltd.
20120327707 - Magnetic random access memory device and method of writing data therein: In a method of writing data in an MRAM device, a first operation unit is selected in a plurality of memory cells of the MRAM device. First to n-th switching pulses are sequentially applied to the first operation unit to write data in first to n-th groups of memory cells... Agent:
20120327706 - Spin-torque transfer memory cell structures with symmetric switching and single direction programming: Techniques are provided for programming a spin torque transfer magnetic random access memory (STT-MRAM) cell using a unidirectional and/or symmetrical programming current. A unidirectional programming current flows through the free region of the STT-MRAM cell in one direction to switch the magnetization of the free region in at least two... Agent: Micron Technology, Inc.
20120327708 - High-endurance phase change memory devices and methods for operating the same: Phase change based memory devices and methods for operating such devices described herein overcome the set or reset failure mode and result in improved endurance, reliability and data storage performance. A high current repair operation is carried out in response to a set or reset failure of a phase change... Agent: Macronix International Co., Ltd.
20120327709 - Programming of phase-change memory cells: A method and apparatus for programming a phase-change memory cell. A bias voltage signal (VBL) is applied to the cell. A measurement portion (m) of this bias voltage signal has a profile which varies with time. A measurement (TM), which is dependent on a predetermined condition being satisfied, is then... Agent: International Business Machines Corporation
20120327711 - Nonvolatile memory device, memory system comprising same, and method of operating same: A method of operating a nonvolatile memory device comprises receiving a read command from a memory controller, determining a read mode of the nonvolatile memory device, selecting a read voltage based on the read mode, and performing a read operation on memory cells of a selected page of the nonvolatile... Agent: Samsung Electronics Co., Ltd.
20120327712 - Method for memory cell erasure with a programming monitor of reference cells: Embodiments of the present disclosure provide methods, devices, modules, and systems for operating memory cells. One method includes: performing an erase operation on a selected group of memory cells, the selected group including a number of reference cells and a number of data cells; performing a programming monitor operation on... Agent: Micron Technology, Inc.
20120327713 - In-field block retiring: Memory devices and methods are disclosed, including a method involving erasing a block of memory cells. After erasing the block, and before subsequent programming of the block, a number of bad strings in the block are determined based on charge accumulation on select gate transistors. The block is retired from... Agent: Micron Technology, Inc.
20120327714 - Memory architecture of 3d array with diode in memory string: Various embodiments are directed to 3D memory arrays that lack a select line and devices controlled by the select line between one of the source line and the bit line, and the memory cells. Diodes between the other of source line and the bit line, and the memory cells provide... Agent: Macronix International Co., Ltd.
20120327715 - Nonvolatile memory devices having vertically integrated nonvolatile memory cell sub-strings therein: Methods of forming nonvolatile memory devices according to embodiments of the invention include techniques to form highly integrated vertical stacks of nonvolatile memory cells. These vertical stacks of memory cells can utilize dummy memory cells to compensate for process artifacts that would otherwise yield relatively poor functioning memory cell strings... Agent:
20120327716 - Compensation of non-volatile memory chip non-idealities by program pulse adjustment: To program a set of non-volatile storage elements, a set of programming pulses are applied to the control gates (or other terminals) of the non-volatile storage elements. The programming pulses have pulse widths that vary as a function of simulated pulse magnitude data. The programming pulses can also have pulse... Agent:
20120327710 - Adaptive write procedures for non-volatile memory: A method includes performing a write operation on memory cells of a memory array to a first logic state using a voltage of a charge pump. A portion of the write operation is performed on the memory cells of the memory array using the voltage of the charge pump. A... Agent:
20120327717 - High read speed memory with gate isolation: Providing for a serial array memory transistor architecture that achieves high read speeds compared with conventional serial array memory is described herein. By way of example, the serial array memory can be connected to and can drive a gate voltage of a small capacitance pass transistor, to facilitate sensing memory... Agent: Spansion LLC
20120327718 - Semiconductor memory device and operating method thereof: An operating method of a semiconductor memory device includes performing a first LSB program loop for storing first LSB data in first memory cells of a word line, performing a second LSB program loop for storing second LSB data in second memory cells of the selected word line and for... Agent:
20120327719 - Thermally assisted flash memory with segmented word lines: A memory includes an array of memory cells including rows and columns including segmented word lines along the rows. The segments of the segmented word lines include local word lines. First and second switches are coupled to corresponding first and second ends of local word lines. The memory includes circuitry... Agent: Macronix International Co., Ltd.
20120327720 - Adaptive write procedures for non-volatile memory using verify read: A method includes performing a write operation on memory cells of a memory array to a first logic state using a voltage of a charge pump. A portion of the write operation is performed on the memory cells of the memory array using the voltage of the charge pump. A... Agent:
20120327721 - Method for erasing memory array: A method for erasing a memory array is provided. The memory array comprises a plurality of memory cell strings, and each of the memory cell strings comprises a plurality of memory cells connected to a plurality of word lines. The method for erasing the memory array includes the following steps.... Agent: Macronix International Co., Ltd.
20120327725 - Circuit devices and methods having adjustable transistor body bias: Circuits, integrated circuits devices, and methods are disclosed that may include biasable transistors with screening regions positioned below a gate and separated from the gate by a semiconductor layer. Bias voltages can be applied to such screening regions to optimize multiple performance features, such as speed and current leakage. Particular... Agent: Suvolta, Inc.
20120327722 - Method and system for a serial peripheral interface: An integrated circuit includes a serial peripheral interface memory device. In an embodiment, the memory device includes a clock signal, a plurality of pins, and a configuration register. In an embodiment, the configuration register includes a wait cycle count. The method includes transmitting a read address to the memory device... Agent: Macronix International Co., Ltd.
20120327723 - Semiconductor device: A data input buffer is changed from an inactive to an active state after the reception of instruction for a write operation effected on a memory unit. The input buffer is a differential input buffer having interface specs based on SSTL, for example, which is brought to an active state... Agent: Renesas Electronics Corporation
20120327724 - Semiconductor memory with redundant word lines, system, and method of manufacturing semiconductor memory: A semiconductor memory has a memory cell array having a plurality of real word lines, a plurality of redundant word lines, a plurality of bit lines crossing with the real and redundant word lines, a plurality of memory cells provided at crossing section of the real and redundant word lines... Agent: Fujitsu Semiconductor Limited
20120327726 - Methods and circuits for dynamically scaling dram power and performance: A memory system supports high-performance and low-power modes. The memory system includes a memory core and a core interface. The memory core employs core supply voltages that remain the same in both modes. Supply voltages and signaling rates for the core interface may be scaled down to save power. Level... Agent: Rambus Inc
20120327727 - Memory device and related control method: A memory device includes: a first memory cell at least controlled by a first word line; a first auxiliary circuit coupled to an auxiliary bit line and controlled by the first word line, the first auxiliary circuit capable of storing a predetermined data value; and a control circuit capable of... Agent:
20120327728 - Method and apparatus for memory command input and control: Memories containing command decoder, chip enable, and signal truncation circuits are disclosed. One such command decoder circuit may include command decoder logic configured to receive command signals and output a decoded command to an interconnect bus responsive to a chip select signal having an active state. Decoder circuits may also... Agent: Micron Technology, Inc.
20120327729 - Memory testing device having cross interconnections of multiple drivers and its implementing method: Disclosed is a memory testing device having cross interconnections of multiple drivers, comprising a first wiring bus and a second wiring bus connected to a first device area and a third wiring bus and a fourth wiring bus connected to a second device area. A first I/O driver module bus... Agent: Powertech Technology Inc.
20120327732 - Semiconductor integrated device: Provided is a semiconductor integrated device including a semiconductor memory circuit and a peripheral circuit of the semiconductor memory circuit. The peripheral circuit includes a first transistor having a first voltage as a breakdown voltage of a gate oxide film. The semiconductor memory circuit includes a pair of bit lines,... Agent: Renesas Electronics Corporation
20120327731 - Semiconductor memory apparatus and bit line equalizing circuit: A semiconductor memory apparatus comprise s bit line sense amplifier unit, and a pair of precharge elements coupled in series between a first bit line and a second bit line and having an asymmetrical contact resistance ratio.... Agent: Hynix Semiconductor Inc.
20120327730 - Sram differential voltage sensing apparatus: An SRAM differential voltage sensing apparatus is coupled to a memory circuit. The memory circuit comprises a memory bank, a plurality of bit lines, a plurality of data lines coupled to the plurality of bit lines via a plurality of transmission gates and a sense amplifier. When the sense amplifier... Agent: Taiwan Semiconductor Manufacturing Company, Ltd.
20120327733 - Semiconductor memory device: A semiconductor memory device has: memory blocks; and a local bus connected to the memory blocks. Each memory block has: switches respectively provided between bit line pairs and the local bus and each of which is turned ON in response to a selection signal; a dummy local bus; first and... Agent: Renesas Electronics Corporation
20120327734 - Semiconductor memory, system, and method of operating semiconductor memory: A memory has memory cells in a matrix; a first selection unit selecting any of first signal lines in the memory cells, in response to an access request; a second selection unit selecting any of second signal lines in the memory cells, after the first selection unit starts operating; a... Agent: Fujitsu Semiconductor Limited
20120327735 - Block-row decoders, memory block-row decoders, memories, methods for deselecting a decoder of a memory and methods of selecting a block of memory: Block-row decoders, memory block-row decoders, memories, methods for deselecting a decoder of a memory and methods of selecting a block of memory are disclosed. An example memory block-row decoder includes a plurality of block-row decoders, each of the block-row decoders having a decoder switch tree. Each block-row decoder is configured... Agent: Micron Technology, Inc
20120327736 - Data sampling devices: Designs of a sampling controller working with memory chips are described. The designs enable a memory chip to work in high frequency clocks, resulting in high data throughput rate. A data sampling device includes a memory chip and a sampling controller. The sampling controller includes an asynchronous data memory. A... Agent: Vimicro Corporation12/20/2012 > 51 patent applications in 31 patent subcategories.
20120320651 - Semiconductor memory device: A semiconductor memory device comprises: a semiconductor substrate; a memory cell array provided above the semiconductor substrate and including a plurality of memory cells that are stacked; a plurality of bit lines connected electrically to the plurality of memory cells; and a plurality of sense amplifiers connected to the bit... Agent: Kabushiki Kaisha Toshiba
20120320652 - Semiconductor memory device: According to an embodiment, a semiconductor memory device comprises: a semiconductor substrate; a memory cell array configured having a plurality of memory units, each of the memory units including a plurality of memory cells connected in series, the plurality of memory cells being stacked, the plurality of memory units involving... Agent: Kabushiki Kaisha Toshiba
20120320653 - Semiconductor system: A device that includes a first semiconductor chip and a second semiconductor chip. The first semiconductor chip includes a first terminal, a second terminal, a first circuit electrically coupled to the second terminal, a second circuit electrically coupled to the first terminal and the first circuit, and a third circuit... Agent: Elpida Memory, Inc.
20120320654 - Semiconductor system: A system that includes a first semiconductor chip, a second semiconductor chip, and a controller chip. The first semiconductor chip includes a first terminal, a second terminal, a first circuit electrically coupled to the second terminal, a second circuit electrically coupled to the first terminal and the first circuit, and... Agent: Elpida Memory, Inc.
20120320655 - Semiconductor devices: A semiconductor device includes a cell region including memory cells that have a selection element and a data storage element, and a driving circuit region including a driving transistor configured to operate the selection element. The driving transistor includes active portions defined by a device isolation pattern in a substrate... Agent:
20120320656 - Programmable resistive memory unit with data and reference cells: A method and system of a programmable resistive memory having a plurality of programmable resistive memory units is disclosed. At least one of the programmable resistive memory units has at least one data cell and at least one reference cell. The data cell can have one programmable resistive element coupled... Agent:
20120320657 - Programmable resistive memory unit with multiple cells to improve yield and reliability: A method and system for a programmable resistive memory to improve yield and reliability has a plurality of programmable resistive units. Each programmable resistive unit can have at least one programmable resistive cell. Each programmable resistive cell can have a programmable resistive element with a first end coupled to a... Agent:
20120320661 - Method of programming variable resistance element and nonvolatile storage device: A method includes applying a first polarity writing voltage pulse to a metal oxide layer to change its resistance state from high to low into a write state, applying a second polarity erasing voltage pulse different from the first polarity to the metal oxide layer to change its resistance state... Agent:
20120320662 - Nonvolatile semiconductor memory device: A nonvolatile semiconductor memory device in accordance with an embodiment comprises a plurality of first, second lines, a plurality of memory cells, and a control circuit. The plurality of second lines extend so as to intersect the first lines. The plurality of memory cells are disposed at intersections of the... Agent: Kabushiki Kaisha Toshiba
20120320658 - Nonvolatile static random access memory cell and memory circuit: A non-volatile static random access memory (NVSRAM) cell including a static random access circuit, first storage device, a second storage device, and a switch unit is provided. The static random access circuit has a first terminal and a second terminal respectively having a first voltage and a second voltage. Stored... Agent: Industrial Technology Research Institute
20120320659 - Resistance-change memory device and method of operating the same: Disclosed herein is a resistance-change memory device including a bit line; a voltage supplying layer; a memory element connected between the bit line and the voltage supplying layer, a resistance value of the memory element being changed in accordance with an applied voltage; and a drive controlling circuit causing a... Agent: Sony Corporation
20120320660 - Write and erase scheme for resistive memory device: A method for programming a two terminal resistive memory device, the method includes applying a bias voltage to a first electrode of a resistive memory cell of the device; measuring a current flowing through the cell; and stopping the applying of the bias voltage if the measured current is equal... Agent: Crossbar, Inc.
20120320663 - Memory device and semiconductor device: A memory device with low power consumption is provided. A memory device includes a first logic element generating an output potential by inverting a polarity of a potential of a signal including data in accordance with a first clock signal; second and third logic elements holding the output potential generated... Agent: Semiconductor Energy Laboratory Co., Ltd.
20120320664 - Semiconductor device: There is provided a technique for ensuring both an SNM and a write margin simultaneously in a semiconductor device having static memory cells. A semiconductor device has a plurality of static memory cells. The semiconductor device includes a memory cell array having the static memory cells arranged in a matrix,... Agent: Renesas Electronics Corporation
20120320667 - Magnetic random access memory: A magnetic random access memory according to the present invention is provided with: a magnetic recording layer including a magnetization free region having a reversible magnetization, wherein a write current is flown through the magnetic recording layer in an in-plane direction; a magnetization fixed layer having a fixed magnetization; a... Agent: Nec Corporation
20120320666 - Magnetoresistive element and magnetic memory: There is provided a magnetoresistive element whose magnetization direction is stable in a direction perpendicular to the film surface and whose magnetoresistance ratio is controlled, as well as magnetic memory using such a magnetoresistive element. By having the material of a ferromagnetic layer forming the magnetoresistive element comprise a ferromagnetic... Agent: Hitachi, Ltd.
20120320665 - Semiconductor memory: A semiconductor memory includes a first memory cell including: a first resistance change element and a first select transistor. The semiconductor memory includes a second memory cell including: a second select transistor and a second resistance change element. The semiconductor memory includes a third memory cell including: a third select... Agent: Kabushiki Kaisha Toshiba
20120320668 - Phase qubit cell having enhanced coherence: Methods and apparatuses are provided for storing a quantum bit. One apparatus includes a first phase qubit, a second phase qubit, and a common bias circuit configured to provide a first bias to the first phase qubit and a second bias to the second phase qubit, such that noise within... Agent:
20120320670 - Fast verify for phase change memory with switch: A phase change memory with switch (PCMS) compensates for threshold voltage drift by utilizing a lower demarcation voltage for a verify operation after programming than for a read operation occurring at least a predetermined period of time after the programming operation.... Agent:
20120320669 - Memory device and method of operating the same: A memory device is provided. The memory device includes a memory array; a first circuit electrically connected to the memory array, and causing the memory array to be operated in a first mode; and a second circuit electrically connected to the memory array, and causing the memory array to be... Agent: Macromix International Co., Ltd.
20120320673 - Data storage system having multi-level memory device and operating method thereof: A method for a data storage system is disclosed. The method includes providing a memory cell array, and providing N blocks in a first region of the memory cell array, N being an integer greater than 1. Each cell of each block of the N blocks is configured to store... Agent:
20120320672 - Memory device readout using multiple sense times: A method for data storage includes storing data in a group of analog memory cells by writing respective storage values into the memory cells in the group. One or more of the memory cells in the group are read using a first readout operation that senses the memory cells with... Agent: Anobit Technologies Ltd.
20120320671 - Memory device with reduced sense time readout: A method for data storage includes providing at least first and second readout configurations for reading storage values from analog memory cells, such that the first readout configuration reads the storage values with a first sense time and the second readout configuration reads the storage values with a second sense... Agent: Anobit Technologies
20120320674 - Multi-level cell access buffer with dual function: An access buffer, such as page buffer, for writing to non-volatile memory, such as Flash, using a two-stage MLC (multi-level cell) operation is provided. The access buffer has a first latch for temporarily storing the data to be written. A second latch is provided for reading data from the memory... Agent: Mosaid Technologies Incorporated
20120320675 - Semiconductor memory device and related method of programming: A method of programming a nonvolatile memory device comprises applying a program voltage to a selected wordline to program selected memory cells, and performing a verify operation by applying a verify voltage to the selected wordline to determine the programming status of the selected memory cells. The verify operation applies... Agent: Samsung Electronics Co., Ltd.
20120320676 - Semiconductor system, nonvolatile memory apparatus, and an associated read method: A semiconductor system includes a host configured to output a command, a control signal, an address signal, and data; and a nonvolatile memory apparatus configured to receive at least one of the command, the control signal, the address signal, and the data from the host, to provide a process result... Agent: Hynix Semiconductor Inc.
20120320678 - Non-volatile semiconductor memory device: In performing a read operation of a memory transistor, a control circuit supplies a first voltage to a selected word line connected to a selected memory transistor. A second voltage is supplied to a non-selected word line connected to a non-selected memory transistor other than the selected memory transistor, the... Agent: Kabushiki Kaisha Toshiba
20120320677 - Nonvolatile semiconductor memory device: In a writing operation, a control circuit raises the voltage of a writing-prohibited bit line among a plurality of bit lines to a first voltage, and thereafter brings the writing-prohibited bit line into a floating state. Then, the control circuit raises the voltage of a writing bit line other than... Agent: Kabushiki Kaisha Toshiba
20120320679 - System and method for minimizing write amplification while maintaining sequential performance using logical group stripping in a multi-bank system: A system and method for reducing write amplification while maintaining a desired level of sequential read and write performance is disclosed. A controller in a multi-bank flash storage device may receive host data for writing to the plurality of flash memory banks. The controller may organize the received data in... Agent:
20120320680 - Method, apparatus, and manufacture for staggered start for memory module: A method, apparatus, and manufacture for memory device startup is provided. Flash memory devices are configured such that, upon the power supply voltage reaching a pre-determined level, each flash memory is arranged to load the random access memory with instructions for the flash memory, and then execute a first portion... Agent: Spansion LLC
20120320681 - Reducing the programming current for memory matrices: A sector of an electrically programmable non-volatile memory includes memory cells connected to word lines and to bit lines, each cell including at least one transistor having a gate connected to a word line, a drain connected to a bit line and a source connected to a source line. The... Agent: Stmicroelectronics (rousset) Sas
20120320683 - Compensating for coupling during programming: Shifts in the apparent charge stored on a floating gate (or other charge storing element) of a non-volatile memory cell can occur because of the coupling of an electric field based on the charge stored in adjacent floating gates (or other adjacent charge storing elements). To compensate for this coupling,... Agent:
20120320682 - Semiconductor memory system including a plurality of semiconductor memory devices: A communication line is connected to first and second chips, and held at a first signal level. A monitor circuit changes a signal level of the communication line from the first signal to a second signal level while one of the first and second chips uses a current larger than... Agent:
20120320684 - Method for discharging a voltage from a capacitance in a memory device: In discharging a voltage from a circuit capacitance, a supply voltage to a memory device is monitored. The capacitance is discharged through a discharge circuit from a relatively high voltage to a relatively low voltage when the supply voltage decreases below a trip voltage. The trip voltage is set by... Agent: Micron Technology, Inc.
20120320685 - Erase operation control sequencing apparatus, systems, and methods: Apparatus, systems, and methods may operate to receive an external erase command at a control circuit coupled to an erasable memory array located on a substrate. A global select gate voltage may thereafter be enabled for application to wordline transistors coupled to the erasable memory array after a voltage applied... Agent:
20120320686 - Semiconductor memory device, information processing system including the same, and controller: A system including a controller and a memory chip. The controller includes first and second selection signal terminals supplying first and second selection signals, respectively, multiple first data terminals and multiple second data terminals. The memory chip includes a semiconductor substrate, third and fourth selection signal terminals provided on the... Agent: Elpida Memory, Inc.
20120320687 - Low voltage sensing scheme having reduced active power down standby current: A low voltage sensing scheme reduces active power down standby leakage current in a memory device. A clamping device or diode is used between a Psense amplifier control line (e.g. ACT) and Vcc and/or between an Nsense amplifier control line (e.g. RNL*) and Vss (ground potential). The clamping diode is... Agent:
20120320688 - Switched interface stacked-die memory architecture: Systems and methods disclosed herein include those that may receive a memory request including a requested memory address and may send the memory request directly to an address decoder associated with a stacked-die memory vault without knowing whether a repair address is required. If a subsequent analysis of the memory... Agent:
20120320689 - Performing logic functions on more than one memory cell within an array of memory cells: A circuit structure is provided for performing a logic function within a memory. A plurality of read word line transistors are provided that receive a read word line signal and, upon receiving the read word line signal, the plurality of read word line transistors provide a path from a plurality... Agent: International Business Machines Corporation
20120320690 - Semiconductor memory device, information processing system including the same, and controller: A semiconductor device that includes a semiconductor substrate. First and second mode registers are provided on the semiconductor substrate and store information, respectively. First and second circuits are provided on the semiconductor substrate. The first and second circuits have substantially the same configuration. The first and second circuits perform an... Agent: Elpida Memory, Lnc.
20120320691 - Clamped bit line read circuit: One embodiment of the present invention sets forth a clamping circuit that is used to maintain a bit line of a storage cell in a memory array at a nearly constant clamp voltage. During read operations the bit line is pulled high or low from the clamp voltage by the... Agent:
20120320692 - Random access memory for use in an emulation environment: In another aspect, the two memory cells can be considered a dual bit cell that contains a copying mechanism. There are two interleaved memory planes, assembled from bit cells that contain two bits of information. One bit is the primary bit that corresponds to the normal RAM bit. The second... Agent: Mentor Graphics Corporation
20120320693 - Dual function compatible non-volatile memory device: A dual function memory device architecture compatible with asynchronous operation and synchronous serial operation. The dual function memory device architecture includes one set of physical ports having two different functional assignments. Coupled between the physical ports and core circuits of the memory device are asynchronous and synchronous input and output... Agent: Mosaid Technologies Incorporated
20120320694 - Write assist in a dual write line semiconductor memory: A semiconductor memory storage device is disclosed, the memory having a plurality of storage cells. Each storage cell comprises two access control devices, each of the access control devices providing the storage cell with access to or isolation from a respective one of two data lines in response to an... Agent:
20120320695 - Pre-charge voltage generation and power saving modes: A system includes a voltage generator to produce a pre-charge voltage signal for pre-charging one or more signals in a memory circuit. The one or more signals can be data bus lines used to access memory. The voltage generator can include an input indicating whether the memory circuit is set... Agent: Mosaid Technologies Incorporated
20120320696 - Semiconductor memory with sense amplifier: In an exemplary aspect, the present invention provides a semiconductor memory device including sense amplifiers that drive bit lines to which memory cells are connected, and driver transistors that supply a power supply to the sense amplifiers, wherein the sense amplifiers are arranged in rows and constitutes a first sense-amplifier... Agent: Renesas Electronics Corporation
20120320697 - Non-volatile semiconductor memory device: A non-volatile semiconductor memory device includes a plurality of memory strings, a plurality of memory blocks, a plurality of source-lines, and a control circuit. Each of the memory strings includes a plurality of stacked memory transistors. Each of the memory blocks includes the memory strings. Each of the source-lines are... Agent: Kabushiki Kaisha Toshiba
20120320698 - Nonvolatile semiconductor memory device and method for erasing data thereof: A control circuit is configured to set a drain-side select transistor and a source-side select transistor connected to a selected memory string to non-conductive states. The control circuit is configured to apply a first voltage to a non-selected word line connected to a gate of a non-selected memory cell in... Agent: Kabushiki Kaisha Toshiba
20120320700 - Current leakage reduction: This description relates to a circuit including a bit line. The circuit further includes at least one memory bank. The at least one memory bank includes at least one memory cell, a first device configured to provide a current path between the bit line and the at least one memory... Agent: Taiwan Semiconductor Manufacturing Company, Ltd.
20120320701 - Multi-channel memory and power supply-driven channel selection: Subject matter disclosed herein relates to a memory device, and more particularly to a multi-channel memory device and methods of selecting one or more channels of same.... Agent: Micron Technology, Inc.
20120320699 - Semiconductor device: A word driver drives a word line with a first power supply voltage and with a second power supply voltage which has a potential lower than the first power potential, respectively in a first time period and in a second time period following the first time period for activating the... Agent: Elpida Memory, Inc.12/13/2012 > 58 patent applications in 34 patent subcategories.
20120314468 - Memory array with local bitlines and local-to-global bitline pass gates and gain stages: A memory array includes wordlines, local bitlines, two-terminal memory elements, global bitlines, and local-to-global bitline pass gates and gain stages. The memory elements are formed between the wordlines and local bitlines. Each local bitline is selectively coupled to an associated global bitline, by way of an associated local-to-global bitline pass... Agent: Unity Semiconductor Corporation
20120314470 - Memory device: A memory cell includes a first transistor controlling writing of the first date by being in an on state, and holding of the first data by being in an off state, a second transistor in which a potential of one of a source and a drain is a potential of... Agent: Semiconductor Energy Laboratory Co., Ltd.
20120314471 - Semiconductor device: A semiconductor device comprises a first region and a second region. The first region includes a plurality of memory cells each of which holds respective data and a plurality of sense amplifiers that respectively amplify the data in the plurality of memory cells, based on a first voltage. The second... Agent: Elpida Memory, Inc.
20120314469 - Semiconductor storage device: A semiconductor storage device includes a semiconductor substrate and an active area on the semiconductor substrate. A plurality of cell transistors are formed on the active area. A first bit line and a second bit line are paired with each other. A plurality of word lines intersect the first and... Agent: Kabushiki Kaisha Toshiba
20120314472 - Multiple-bit programmable resistive memory using diode as program selector: A method and system for multiple-bit programmable resistive cells having a multiple-bit programmable resistive element and using diode as program selector are disclosed. The first and second terminals of the diode having a first and second types of dopants can be fabricated from source/drain of MOS in a well for... Agent:
20120314473 - Multiple-state one-time programmable (otp) memory to function as multi-time programmable (mtp) memory: A circuit, method, and system for using multiple-state One-Time Programmable (OTP) memory to function as a multiple-bit programmable (MTP) memory are disclosed. The OTP memory can have N(N>2) distinct resistance states, that can be differentiated by at least N−1 reference resistances, can be functionally equivalent programmed N−1 times. The multiple-state... Agent:
20120314474 - Non-volatile memory cell structure and method for programming and reading the same: The present invention provides a non-volatile memory cell structure. A first isolation structure is disposed on a substrate and a semiconductor layer is disposed on the first isolation structure to form a silicon on insulator device. A first doping region is made of a portion of the semiconductor layer. A... Agent:
20120314475 - Low voltage programmable mosfet antifuse with body contact for diffusion heating: An antifuse can include an insulated gate field effect transistor (“IGFET”) having an active semiconductor region including a body and first regions, i.e., at least one source region and at least one drain region separated from one another by the body. A gate may overlie the body and a body... Agent: International Business Machines Corporation
20120314476 - Organic ferroelectric material based random access memory: Illustrative embodiments provide a FETRAM that is significantly improved over the operation of conventional FeRAM technology. In accordance with at least one disclosed embodiment, a CMOS-processing compatible memory cell (see definition above) provides an architecture enabling a non-destructive read out operation using organic ferroelectric PVDF-TrFE as the memory storage unit... Agent: Purdue Research Foundation
20120314477 - Array voltage regulating technique to enable data operations on large cross-point memory arrays with resistive memory elements: Embodiments of the invention relate generally to semiconductors and memory technology, and more particularly, to systems, integrated circuits, and methods to preserve states of memory elements in association with data operations using variable access signal magnitudes for other memory elements, such as implemented in third dimensional memory technology. In some... Agent: Unity Semiconductor Corporation
20120314481 - Cell-state measurement in resistive memory: Apparatus and method for measuring the state of a resistive memory cell. A bias voltage controller applies a bias voltage to the cell and controls the level of the bias voltage. A feedback signal generator senses cell current due to the bias voltage and generates a feedback signal (SFB) dependent... Agent: International Business Machines Corporation
20120314479 - Memory element and memory device: A memory element includes: a memory layer disposed between a first electrode and a second electrode. The memory layer includes: an ion source layer containing one or more metallic elements, and one or more chalcogen elements of tellurium (Te), sulfur (S), and selenium (Se); and a resistance change layer disposed... Agent: Sony Corporation
20120314478 - Resistive memory device and sensing margin trimming method thereof: A resistive memory device and a sensing margin trimming method are provided. The resistive memory device includes a memory cell array and a trimming circuit. The memory cell array has a plurality of resistive memory cells. The trimming circuit generates a trimming signal according to a characteristic distribution shift value... Agent:
20120314480 - Semiconductor memory device: In a semiconductor memory device using a variable resistive element made of a metal oxide for storing information, a voltage amplitude of a writing voltage pulse for changing the variable resistive element to a high resistance state is set within a voltage range in which the resistance value of the... Agent:
20120314484 - Multilevel dram: A multi-level dynamic random-access memory (MLDRAM) represents an original bit combination of more than one bit using a cell voltage stored in a single memory cell. The cell voltage is in one of a number of discrete analog voltage ranges each corresponding to a respective one of the possible values... Agent: Rambus Inc
20120314483 - Semiconductor device: A semiconductor device includes a bit line, a memory cell, and a control circuit. The memory cell includes a switch circuit coupled to the bit line and a memory element configured to store either one of first and second data. The control circuit controls a voltage of the bit line... Agent: Elpida Memory, Inc.
20120314482 - Semiconductor memory device: An object is to increase the retention characteristics of a memory device formed using a semiconductor with a wide bandgap, such as an oxide semiconductor. A transistor including a back gate (a back gate transistor) is inserted in series at one end of a bit line so that the back... Agent: Semiconductor Energy Laboratory Co., Ltd.
20120314485 - Complementary soi lateral bipolar for sram in a low-voltage cmos platform: An example embodiment is a memory cell including a SOI substrate. A first and second set of lateral bipolar transistors are fabricated on the SOI substrate. The first and second set of lateral bipolar transistors are electrically coupled to form two inverters. The inverters are cross coupled to form a... Agent: International Business Machines Corporation
20120314486 - Semiconductor memory device for reducing charge/discharge power of write bitlines: It is aimed to provide a semiconductor memory device capable of solving a half-select problem in 8Tr SRAMs and, simultaneously, achieving a reduction in charge/discharge power in a half-selected column, which has been a problem with the conventional write-back scheme. An 8Tr SRAM includes 1) a bitline half driver circuit... Agent: Semiconductor Technology Academic Research Center
20120314490 - Magnetic memory system and methods in various modes of operation: A magnetic memory system includes a superconductor circuit and one or more magnetic memory elements to store data. To write data, a driver circuit in the superconductor circuit generates a magnetic signal for transmission over a superconductor link extending between the superconductor circuit and the magnetic memory element. To read... Agent:
20120314487 - Magnetic random access memory devices including multi-bit cells: A magnetic random access memory (“MRAM”) cell includes: (1) a first magnetic layer having a first magnetization direction and a magnetic anisotropy axis; (2) a second magnetic layer having a second magnetization direction; and (3) a spacer layer disposed between the first magnetic layer and the second magnetic layer. The... Agent: Crocus Technology, Inc.
20120314488 - Magnetic random access memory devices including multi-bit cells: A magnetic random access memory (MRAM) cell includes a storage layer, a sense layer, and a spacer layer between the storage layer and the sense layer. A field line is magnetically coupled to the MRAM cell to induce a magnetic field along a magnetic field axis, and at least one... Agent: Crocus Technology, Inc.
20120314489 - Systems and methods for direct communication between magnetic tunnel junctions: Systems and methods that enable direct communications between magnetic tunnel junctions are provided. In one embodiment, a device includes multiple input magnetic tunnel junctions and an output magnetic tunnel junction. The multiple input magnetic tunnel junctions are connected in parallel, and the output magnetic tunnel junction is connected in series... Agent: Regents Of The University Of Minnesota
20120314492 - Non-volatile memory device having phase-change material and method for fabricating the same: A non-volatile memory device includes a plurality of memory blocks. Each of memory blocks includes a main area including a plurality of first memory cells having a phase-change material and a spare area including at least one second memory cell for storing initial information about the plurality of first memory... Agent: Samsung Electronics Co., Ltd.
20120314493 - Phase change memory and method for fabricating phase change memory: A phase change memory includes an insulating layer on a substrate, an electrode layer having one pole and an electrode layer having another pole within the insulating layer, an opening portion whose lower portion on an upper portion of the insulating layer is substantially square or substantially rectangular, a phase... Agent: Tokyo Electron Limited
20120314491 - Set pulse for phase change memory programming: Subject matter disclosed herein relates to a memory device, and more particularly to a single pulse algorithm for programming a phase change memory.... Agent: Micron Technology, Inc.
20120314494 - Semiconductor storage device: In a memory, the MTJ elements respectively have a first end electrically connected to any one of a source and a drain of one of the cell transistors. First bit lines each of which is electrically connected to the other one of the source and the drain of one of... Agent: Kabushiki Kaisha Toshiba
20120314495 - Apparatus for reducing the impact of program disturb: The unintentional programming of an unselected (or inhibited) non-volatile storage element during a program operation that intends to program another non-volatile storage element is referred to as “program disturb.” A system is proposed for programming and/or reading non-volatile storage that reduces the effect of program disturb. In one embodiment, different... Agent:
20120314496 - Nonvolatile memory devices having improved read reliability: Memory systems include at least one nonvolatile memory array having a plurality of rows of nonvolatile multi-bit (e.g., N-bit, where N>2) memory cells therein. A control circuit is also provided, which is electrically coupled to the nonvolatile memory array. The control circuit is configured to program at least two pages... Agent:
20120314497 - Semiconductor memory device capable of realizing a chip with high operation reliability and high yield: A semiconductor memory device capable of preventing a defect caused by lowering the etching precision in an end area of the memory cell array is provided. A first block is constructed by first memory cell units each having of memory cells, a second block is constructed by second memory cell... Agent: Kabushiki Kaisha Toshiba
20120314498 - Method for detecting flash program failures: One or more techniques are provided for programming a flash memory device. In one embodiment, the memory device is programmed such that a data pattern written to a page in the memory device has encoded therein an expected count value corresponding to the number of times a first binary value... Agent: Micron Technology, Inc.
20120314499 - Intelligent shifting of read pass voltages for non-volatile storage: A first read pass voltage is determined and optimized for cycled memory. One or more starting read pass voltages are determined for one or more dies. The system dynamically calculates a current read pass voltage based on the number of program/erase erase cycles, the first read pass voltage and the... Agent:
20120314500 - Nonvolatile memory devices and methods of programming nonvolatile memory devices: A nonvolatile memory device includes a memory cell array, a page buffer unit which output a verify-read result, a reference current generating unit which generates a reference current signal, a page buffer decoding unit which outputs currents according to the verify-read result. The nonvolatile memory device further includes an analog... Agent:
20120314501 - Semiconductor device and method of programming the same: A method of programming a semiconductor device includes performing a Least Significant Bit (LSB) program operation on selected memory cells, performing a soft program operation on the remaining memory cells other than memory cells on which the LSB program operation has been performed, and performing a Most Significant Bit (MSB)... Agent: Sk Hynix Inc.
20120314503 - Coarse and fine programming in a solid state memory: Memory devices adapted to receive and transmit analog data signals representative of bit patterns of two or more bits facilitate increases in data transfer rates relative to devices communicating data signals indicative of individual bits. Programming of such memory devices includes initially programming a cell with a coarse programming pulse... Agent: Micron Technology, Inc.
20120314502 - Programming non-volatile storage with synchonized coupling: A process for programming non-volatile storage is able to achieve faster programming speeds and/or more accurate programming through synchronized coupling of neighboring word lines. The process for programming includes raising voltages for a set of word lines connected a group of connected non-volatile storage elements. The set of word lines... Agent:
20120314504 - Semiconductor memory device: According to one embodiment, a semiconductor memory device includes units each including memory cells, a data bus connected to each of the units and having data lines, holding circuits configured to hold fail information supplied from the unit through the data bus as a verify result after writing data, and... Agent:
20120314505 - Row decoder and non-volatile memory device: A non-volatile memory device and a row decoder, the non-volatile memory device including: a memory cell array comprising a plurality of memory cells and each memory cell includes a first cell transistor and a second cell transistor; and a row decoder comprising a first driver and a second driver for... Agent:
20120314506 - Semiconductor device and method of operating the same: A semiconductor device includes cell strings that each include a plurality of memory cells, a page buffer having latches coupled to bit lines and precharge the bit lines in response to page buffer control signals, a page buffer control circuit configured to generate the page buffer control signals using a... Agent:
20120314508 - Control circuitry for memory cells: Control circuitry for memory cells is described. In an embodiment, a breakdown detection circuit is described which is arranged to detect abnormally high currents indicative of a defective cell during programming of a memory cell through monitoring the impedance level at a terminal in the breakdown detection circuit. The breakdown... Agent: Cambridge Silicon Radio Limited
20120314507 - Reduced voltage nonvolatile flash memory: Subject matter disclosed herein relates to a memory device, and more particularly to flash memory.... Agent: Micron Technology, Inc.
20120314509 - Non-volatile semiconductor device, and method of operating the same: A non-volatile semiconductor device and a method for operating the same are disclosed, where the non-volatile semiconductor device includes a gate dielectric layer, a p-type floating gate, a coupling gate, a first p-type source/drain, a second p-type source/drain, a first contact plug and a second contact plug. The gate dielectric... Agent:
20120314511 - Semiconductor device: A device includes a semiconductor substrate, a first penetrating electrode penetrating through the semiconductor substrate, a first test pad, and a first tri-state buffer coupled between the first penetrating electrode and the first test pad. The first tri-state buffer receives a buffer control signal at a control terminal thereof. The... Agent: Elpida Memory, Inc.
20120314510 - Semiconductor memory device: Provided is a semiconductor memory device including a plurality of memory cells arranged in a matrix, a plurality of word lines arranged corresponding to each row of the memory cells, a plurality of bit line pairs arranged corresponding to each column of the memory cells, a column selector that selects... Agent: Renesas Electronics Corporation
20120314512 - Cache memory and method for driving the same: A cache memory which can operate with less power consumption and has an improved cache hit rate and a method for driving the cache memory are provided. Two data storage portions (a first storage portion and a second storage portion) and one data transfer portion are provided in one memory... Agent: Semiconductor Energy Laboratory Co., Ltd.
20120314513 - Semiconductor memory device and method of driving semiconductor memory device: A semiconductor memory device includes a memory portion that includes i (i is a natural number) sets each including j (j is a natural number of 2 or larger) arrays each including k (k is a natural number of 2 or larger) lines to each of which a first bit... Agent: Semiconductor Energy Laboratory Co., Ltd.
20120314514 - Semiconductor memory device: A semiconductor memory device includes word lines stacked over a substrate having a plurality of memory block regions, select lines arranged over the word lines, vertical channel layers formed to penetrate through the select lines and the word lines and extending to the substrate, and a charge trap layer disposed... Agent:
20120314515 - Semiconductor memory device: In a semiconductor memory device, the output of a regulator is coupled to the inputs of first and second switches, the output of the first switch is coupled to a path for supplying the drain voltage of a memory cell in the first mode, and the output of the second... Agent: Panasonic Corporation
20120314516 - Performing stuck-at testing using multiple isolation circuits: A memory may include a memory array, a plurality of control circuits, and a plurality of isolation circuits. The plurality of control circuits may be configured to generate control signals for the memory array. For example, the plurality of control circuits may include a plurality of word line driver circuits.... Agent:
20120314517 - Asynchronous/synchronous interface: The present disclosure includes methods, and circuits, for operating a memory device. One method embodiment for operating a memory device includes controlling data transfer through a memory interface in an asynchronous mode by writing data to the memory device at least partially in response to a write enable signal on... Agent: Micron Technology, Inc.
20120314518 - Semiconductor memory device and method of operating the same: A semiconductor memory device includes a count clock generation unit for generating a count clock in response to a clock signal and a dummy count clock, a column address generation unit for generating a column address in response to the count clock, and a Y decoder for sending data, stored... Agent: Sk Hynix Inc.
20120314520 - Memory architecture with redundant resources: A hierarchical memory architecture includes an array of memory sub-arrays, each of which includes an array of memory cells. Each sub-array is supported by local wordlines, local column-select lines, and bitlines. The local wordlines are controlled using main wordlines that extend past multiple sub-arrays in a direction parallel to a... Agent: Rambus Inc.
20120314519 - Word line driving signal control circuit, semiconductor memory apparatus having the same, and word line driving method: A word line driving signal control circuit of a semiconductor memory apparatus provided with a sub-redundancy cell array includes a fuse unit configured to generate a redundancy enable signal in response to a bank active signal and an address signal, and a repair determination unit configured to activate one of... Agent: Hynix Semiconductor Inc.
20120314521 - Memory throughput increase via fine granularity of precharge management: Methods and apparatus to improve throughput in memory devices are described. In one embodiment, memory throughput is increased via fine granularity of precharge management. In an embodiment, three separate precharge timings may be used, e.g., optimized per memory bank, per memory bank group, and/or per a memory device. Other embodiments... Agent:
20120314522 - Controlling clock input buffers: An integrated circuit may have a clock input pin coupled to a buffer (24). The buffer may supply a clock signal (28) to an integrated circuit chip such as the memory. To conserve power, the buffer is powered down. When ready for use, the buffer is quickly powered back up.... Agent: Micron Technology, Inc
20120314523 - Multi-port memory devices and methods: Embodiments of a multi-port memory device may include a plurality of ports and a plurality of memory banks some of which are native to each port and some of which are non-native to each port. The memory device may include a configuration register that stores configuration data indicative of the... Agent: Micron Technology, Inc.
20120314524 - Semiconductor device: An object is to increase the retention characteristics of a memory device formed using a wide bandgap semiconductor. A bit line controlling transistor is inserted in a bit line in series. The minimum potential of a gate of the transistor is set to a sufficiently negative value. The gate of... Agent: Semiconductor Energy Laboratory Co., Ltd.
20120314525 - Semiconductor memory device and driving method thereof: A semiconductor memory device includes a plurality of wordlines and a driver configured to, when an wordline of the plurality of wordlines is activated by an active command, drive at least one non-activated wordline neighboring the activated wordline and remaining non-activated wordlines with different wordline driving voltage levels during a... Agent:12/06/2012 > 43 patent applications in 29 patent subcategories.
20120307542 - Local bit lines and methods of selecting the same to access memory elements in cross-point arrays: Embodiments relate generally to semiconductors and memory technology, and more particularly, to systems, integrated circuits, and methods to implement a memory architecture that includes local bit lines for accessing subsets of memory elements, such as memory elements based on third dimensional memory technology. In at least some embodiments, an integrated... Agent: Unity Semiconductor Corporation
20120307543 - Semiconductor device: A semiconductor device including multiple subarrays arrayed in a matrix in the row and column directions, and respectively containing multiple memory cells, bit lines coupled to the memory cells, and precharge circuits (to charge the bit lines; column select signal lines extending in the column direction for selecting subarray columns;... Agent: Renesas Electronics Corporation
20120307544 - Semiconductor memory apparatus: A semiconductor memory apparatus includes a boundary circuit unit positioned between a low voltage page buffer and a high voltage page buffer and having circuits configured to electrically couple the low voltage page buffer and the high voltage page buffer. The boundary circuit unit includes: a first boundary circuit unit... Agent: Sk Hynix Inc.
20120307545 - Interleaved bit line architecture for 2t2c ferroelectric memories: A ferroelectric memory with interleaved pairs of ferroelectric memory cells of the two-transistor, two-capacitor (2T2C) type. Each memory cell in a given pair is constructed as first and second portions, each portion including a transistor and a ferroelectric capacitor. Within each pair, a first portion of a second memory cell... Agent: Texas Instruments Incorporated
20120307546 - Non-volatile memory cell including a resistivity change material: A non-volatile memory cell including a resistivity change material configured to reversibly change state between at least two stable states having different electrical resistances and conformed such that transformation from one state to another is obtained by controlling the temperature increase or decrease of the resistivity change material, wherein the... Agent: Commissariat A L'energie Atomique Et Aux Ene. Alt.
20120307547 - Resistive memory devices and memory systems having the same: A nonvolatile memory device includes an array of resistive memory cells and a write driver, which is configured to drive a selected bit line in the array with a reset current pulse, which is responsive to a first external voltage input through a first terminal/pad of the memory device during... Agent:
20120307548 - Dual-port subthreshold sram cell: An innovative dual-port subthreshold static random access memory (SRAM) cell for sub-threshold voltage operation is disclosed. During write mode, the dual-port subthreshold SRAM cell would cut off the positive feedback loop of the inverters and utilize the reverse short-channel effect to enhance write capability. The single-ended read/write port structure further... Agent: National Chiao Tung University
20120307549 - Nonvolatile latch circuit: A nonvolatile latch circuit that includes a logic circuitry comprising at least an input terminal, a clock terminal, an output terminal, and a nonvolatile memory element. The logic circuitry is electrically coupled to a high voltage source at a first source terminal and to a low voltage source at a... Agent:
20120307550 - Asymmetric static random access memory cell with dual stress liner: A solid-state memory in which each memory cell is constructed of complementary metal-oxide-semiconductor (CMOS) inverters implemented with dual stress liner (DSL) technology. Each memory cell includes a pair of cross-coupled CMOS inverters, and corresponding pass gates for coupling the cross-coupled storage nodes to first and second bit lines. Asymmetry is... Agent: Texas Instruments Incorporated
20120307551 - Semiconductor device: The present invention is directed to provide a semiconductor device having a dual-port memory circuit in which influence of placement of replica cells exerted on enlargement of chip area is reduced. A memory cell array of a dual-port memory circuit has : a first replica cell array used to respond... Agent: Renesas Electronics Corporation
20120307553 - Circuitry for reading phase change memory cells having a clamping circuit: A read circuit for reading at least one memory cell adapted to storing a logic value, the at least one memory cell including: a storage element made of a phase-change material; and an access element for coupling the storage element to the read circuit in response to a selection of... Agent:
20120307554 - Determining cell-state in phase-change memory: A method, an apparatus, and a device for determining the state of a phase-change memory cell. The method includes the steps of: biasing a cell with a time-varying read voltage (Vread); making a measurement (TM) that satisfies a predetermined condition where the predetermined condition depends on a cell current when... Agent: International Business Machines Corporation
20120307555 - Phase change memory structures and methods: Methods, devices, and systems associated with phase change memory structures are described herein. One method of forming a phase change memory structure includes forming an insulator material on a first conductive element and on a dielectric material of a phase change memory cell, forming a heater self-aligned with the first... Agent: Micron Technology, Inc.
20120307552 - Process of producing a resistivity-change memory cell intended to function in a high-temperature environment: A process of producing a resistivity-change memory cell is described. The process includes a deposition at room temperature, in amorphous state, of a layer of a nitrogen (N)-doped alloy of germanium (Ge) and tellurium (Te) to constitute the resistivity-change material of the memory cell. An annealing is then performed such... Agent: Commissariat A L'energie Atomique Et Aux Ene. Alt.
20120307556 - Magnetic device with exchange bias: A magnetic device includes a magnetic layer having a variable direction of magnetisation, and a first antiferromagnetic layer in contact with the magnetic layer, the first antiferromagnetic layer being able to trap the direction of magnetisation of the magnetic layer. The magnetic device also includes a layer made of a... Agent: Commissariat à I' é Nergie Atomique Et é Nergies Alternatives
20120307558 - Apparatus for reducing the impact of program disturb: The unintentional programming of an unselected (or inhibited) non-volatile storage element during a program operation that intends to program another non-volatile storage element is referred to as “program disturb.” A system is proposed for programming and/or reading non-volatile storage that reduces the effect of program disturb. In one embodiment, different... Agent:
20120307557 - Nonvolatile semiconductor memory device and data erase method thereof: A nonvolatile semiconductor memory device according to an aspect includes a semiconductor substrate, a memory cell array, memory strings, drain side selection transistors, source side selection transistors, word lines, bit lines, a source line, a drain side selection gate line, a source side selection gate line, and a control circuit.... Agent: Kabushiki Kaisha Toshiba
20120307559 - Data modulation for groups of memory cells: Methods, devices, and systems for data modulation for groups of memory cells. Data modulation for groups of memory cells can include modulating N units of data to a combination of programmed states. Each memory cell of a group of G number of memory cells can be programmed to one of... Agent: Micron Technology, Inc.
20120307560 - Page-buffer and non-volatile semiconductor memory including page buffer: A non-volatile memory device includes a memory cell array which includes a plurality of non-volatile memory cells, a plurality of word lines, and a plurality of bit lines. The memory device further includes an internal data output line for outputting data read from the bit lines of the memory array,... Agent: Samsung Electronics Co., Ltd.
20120307561 - Non-volatile memory device and method controlling dummy word line voltage according to location of selected word line: A non-volatile memory device includes access circuitry that selects a word line during an operation, applies a selected word line voltage to the selected word line, applies a non-selected word line voltage to non-selected word lines among the word lines, and applies a dummy word line voltage to the dummy... Agent: Samsung Electronics Co., Ltd.
20120307563 - Nonvolatile memory with bitline capacitive coupling compensation: A method of programming memory cells in a nonvolatile memory, includes applying a programming voltage to a first bitline and setting a second bitline in a floating state. The method further includes applying a compensation voltage to a shield conductive line coupled to the bitline set in the floating state,... Agent: Stmicroelectronics (rousset) Sas
20120307562 - Nonvolatile semiconductor memory device: A nonvolatile semiconductor memory device according to an embodiment includes: a semiconductor substrate; a memory cell array including a plurality of memory cells, the memory cells being stacked on the semiconductor substrate; and a power supply circuit provided on the semiconductor substrate. The power supply circuit includes: a pump circuit... Agent: Kabushiki Kaisha Toshiba
20120307564 - Method for kink compensation in a memory: This disclosure concerns memory kink compensation. One method embodiment includes applying a number of sequentially incrementing programming pulses to a memory cell, with the sequential programming pulses incrementing by a first programming pulse step voltage magnitude. A seeding voltage is applied after applying the number of sequentially incrementing programming pulses.... Agent: Micron Technology, Inc.
20120307565 - Method for operating non-volatile memory device: A method for operating a non-volatile memory device includes performing an erase operation onto a memory block including a plurality of memory cells, and performing a first soft program operation onto all the memory cells of a string, after the erase operation, grouping word lines of the string into a... Agent:
20120307566 - Memory cell sensing using a boost voltage: The present disclosure includes devices, methods, and systems including memory cell sensing using a boost voltage. One or more embodiments include pre-charging and/or floating a data line associated with a selected memory cell, boosting the pre-charged and/or floating data line, and determining a state of the selected memory cell based... Agent: Micron Technology, Inc.
20120307567 - Method of operating non-volatile memory device: A method of operating a non-volatile memory device includes erasing a memory cell block, supplying a first drain turn-on voltage higher than a target level to the drain select line of the memory cell block, and performing a soft program operation by supplying a soft program voltage to the word... Agent:
20120307568 - Techniques for providing a semiconductor memory device: Techniques for providing a semiconductor memory device are disclosed. In one particular embodiment, the techniques may be realized as a semiconductor memory device including a plurality of memory cells arranged in an array of rows and columns. Each memory cell may include a first region coupled to a source line,... Agent: Micron Technology, Inc.
20120307569 - Printed non-volatile memory: A nonvolatile memory cell is disclosed, having first and second semiconductor islands at the same horizontal level and spaced a predetermined distance apart, the first semiconductor island providing a control gate and the second semiconductor island providing source and drain terminals; a gate dielectric layer on at least part of... Agent:
20120307570 - Method for relaying data to memory array: A method is provided for relaying data to a memory array operating in synchronization with a clock signal having a first transition edge. A data strobe signal having a second transition edge corresponding to the first transition edge is provided. A first signal is provided. The data is latched into... Agent:
20120307572 - Semiconductor device: The semiconductor device makes a comparison between a word-line timing signal for determining a word-line activation time and a reference signal, applies a back-gate bias for enlarging a read margin when the result of the comparison represents a low condition of the read margin, and applies a back-gate bias for... Agent: Renesas Electronics Corporation
20120307571 - Sense amplifier circuit: A sense amplifier circuit comprises a first inverter configured to provide a first trigger point during a pre-charge stage of a READ operation of a memory cell and provide a second trigger point either lower or higher than the first trigger point during a sense stage of the READ operation... Agent: Taiwan Semiconductor Manufacturing Company, Ltd.
20120307573 - Semiconductor device: A semiconductor device includes first and second bit lines, and a transistor coupled between the first and second bit lines. The semiconductor device further includes a substrate bias control circuit that supplies one of a first substrate bias voltage and a second substrate bias voltage to the transistor. By controlling... Agent: Elpida Memory, Inc.
20120307574 - Sram read and write assist apparatus: A SRAM READ and WRITE assist apparatus comprises a bit line voltage tracking block, a READ assist timer, a READ assist unit, a WRITE assist unit a WRITE control unit. The bit line voltage tracking block detects a voltage on a tracking bit line coupled to a plurality of tracking... Agent: Taiwan Semiconductor Manufacturing Company, Ltd.
20120307576 - Analog sensing of memory cells with a source follower driver in a semiconductor memory device: Memory devices, methods, and sample and hold circuits are disclosed, including a memory device that includes a sample and hold circuit coupled to a bit line. One such sample and hold circuit includes a read circuit, a verify circuit, and a reference circuit. The read circuit stores a read threshold... Agent: Micron Technology, Inc.
20120307575 - Memory controller and control method: A memory controller includes: a first write circuit configured to write a first dummy pattern including a plurality of consecutive first dummy values at a first address of a memory; a second write circuit configured to write a first pattern including a plurality of types of consecutive values at a... Agent: Fujitsu Limited
20120307577 - System and method for gate training in a memory system: A system and method for gate training in a memory system is disclosed. In one embodiment, in a method for calibrating read data strobe gating, a first read command is issued to a memory module. A first DQS gate signal is issued before the beginning of the preamble of a... Agent:
20120307578 - Semiconductor device having redundant select line to replace regular select line: Disclosed herein is a semiconductor device that includes a plurality of normal memory cells, a plurality of first normal lines each coupled to corresponding one or ones of the normal memory cells, a plurality of redundant memory cells, and first and second redundant lines each coupled to corresponding one or... Agent: Elpida Memory, Inc.
20120307579 - Memory reliability verification techniques: Some embodiments of the present disclosure relate to improved reliability verification techniques for semiconductor memories. Rather than merely carrying out a BIST test by verifying whether a memory cell accurately stores a “1” or “0” under normal read/write conditions, aspects of the present invention relate to BIST tests that test... Agent: Infineon Technologies Ag
20120307580 - Pre-charge and equalization devices: A circuit comprises a set of pre-charge and equalization devices, a control signal line, and a word line. The set of pre-charge and equalization devices is configured to pre-charge and equalize a pair of data lines. The control signal line is configured to control the pre-charge and equalization devices. The... Agent: Taiwan Semiconductor Manufacturing Company, Ltd.
20120307583 - Semiconductor device for performing a refresh operation: A semiconductor device according to the present invention has an address scrambling circuit for performing address scrambling operation of an address and a redundancy judging circuit for judging that redundancy judgment is performed about the address scrambled by the address scrambling circuit. This structure makes it possible to completely refresh... Agent: Elpida Memory, Inc.
20120307581 - Semiconductor device on which wafer-level burn-in test is performed and manufacturing method thereof: Disclosed herein is a device that includes a clock generation circuit that generates an internal clock signal during a normal operation and stops generation of the internal clock signal during a wafer-level burn-in test, a clock tree line that transmits the internal clock signal, and a selector that supplies a... Agent: Elpida Memory, Inc.
20120307582 - Semiconductor device performing self refresh operation: When refresh activation signals (REFACT0 to REFACT3) are supplied, the internal memory cells in two or more memory banks (0 to 3) are refreshed. A refresh control circuit performs a first refresh control operation to activate a refresh operation in all of the memory banks when an auto refresh command... Agent: Elpida Memory, Inc.
20120307584 - Memory power supply circuit: A memory power supply circuit is used for providing power to a first memory module received in a first memory slot and a second memory module received in a second memory slot, and comprises a logic circuit and a switching power supply. The logic circuit comprises a first input terminal... Agent: Hong Fu Jin Precision Industry (shenzhen)co., Ltd.Previous industry: Electric power conversion systems
Next industry: Agitating
RSS FEED for 20150611:
Integrate FreshPatents.com into your RSS reader/aggregator or website to track weekly updates.
For more info, read this article.
Thank you for viewing Static information storage and retrieval patents on the FreshPatents.com website. These are patent applications which have been filed in the United States. There are a variety ways to browse Static information storage and retrieval patent applications on our website including browsing by date, agent, inventor, and industry. If you are interested in receiving occasional emails regarding Static information storage and retrieval patents we recommend signing up for free keyword monitoring by email.
Advertise on FreshPatents.com - Rates & Info
FreshPatents.com Support - Terms & Conditions
Results in 0.31468 seconds