|Static information storage and retrieval patents - Monitor Patents|
USPTO Class 365 | Browse by Industry: Previous - Next | All
11/2012 | Recent | 13: May | Apr | Mar | Feb | Jan | 12: Dec | Nov | Oct | Sep | Aug | July | June | May | April | Mar | Feb | Jan | 11: Dec | Nov | Oct | Sep | Aug | Jul | Jun | May | Apr | Mar | Feb | Jan | 10: Dec | Nov | Oct | Sep | Aug | Jul | Jun | May | Apr | Mar | Feb | Jan | | 09: Dec | Nov | Oct | Sep | Aug | Jl | Jn | May | Apr | Mar | Fb | Jn | | 2008 | 2007 |
Static information storage and retrieval November recently filed with US Patent Office 11/12Below are recently published patent applications awaiting approval from the USPTO. Recent week's RSS XML file available below.
Listing for abstract view: USPTO application #, Title, Abstract excerpt,Patent Agent. Listing format for list view: USPTO National Class full category number, title of the patent application. 11/29/2012 > 44 patent applications in 24 patent subcategories. recently filed with US Patent Office
20120300527 - Nonvolatile memory including plural memory cells stacked on substrate: According to example embodiments, a nonvolatile memory device includes a memory cell array including a plurality of memory cells stacked on a substrate, a plurality of word lines connected with the memory cell array, a plurality of pass voltage generators, and a voltage control circuit. The pass voltage generators each... Agent:
20120300528 - Stacked memory module and system: A three dimensional memory module and system are formed with at least one slave chip stacked over a master chip. Through semiconductor vias (TSVs) are formed through at least one of the master and slave chips. The master chip includes a memory core for increased capacity of the memory module/system.... Agent:
20120300529 - Semiconductor device having hierarchically structured bit lines and system including the same: A device includes a first sense amplifier array including a plurality of first sense amplifiers arranged in a first direction, each of the first sense amplifiers including first and second nodes, a plurality of first global bit lines extending in a second direction crossing the first direction, the first global... Agent: Elpida Memory, Inc.
20120300531 - Current writing circuit for a resistive memory cell arrangement: A current writing circuit for a resistive memory cell arrangement is provided. The current writing circuit comprises a first current source; a first reference potential terminal; a first switch configured to switch between the first current source and the first reference potential terminal during a write operation; a second current... Agent: Agency For Science, Technology And Research
20120300534 - High density memory device: A method of operating a memory device having a dielectric material layer, a transition metal oxide layer and a set of electrodes each formed over a substrate, includes applying a voltage across the set of electrodes producing an electric field across the transition metal oxide layer enabling the transition metal... Agent: International Business Machines Corporation
20120300530 - Memory cell operation: Methods, devices, and systems associated with memory cell operation are described. One or more methods of operating a memory cell include charging a capacitor coupled to the memory cell to a particular voltage level and programming the memory cell from a first state to a second state by controlling discharge... Agent: Micron Technology, Inc.
20120300532 - Method of forming process for variable resistive element and non-volatile semiconductor memory device: A method of a forming process for a variable resistive element, which is performed in short time comparable to the pulse forming and a writing current in a switching action is the same level as that of the DC forming, is provided. In the forming process, a variable resistive element... Agent:
20120300535 - Non-volatile memory device ion barrier: An ion barrier layer made from a dielectric material in contact with an electronically insulating layer is operative to prevent mobile ions transported into the electronically insulating layer from passing through the ion barrier layer and into adjacent layers during data operations on a non-volatile memory cell. A conductive oxide... Agent: Unity Semiconductor Corporation
20120300533 - Nonvolatile memory cell operating by increasing order in polycrystalline semiconductor material: A memory cell is provided that includes a first conductor, a second conductor, and a semiconductor junction diode between the first and second conductors. The semiconductor junction diode is not in contact with a material having a lattice mismatch of less than 12 percent with the semiconductor junction diode. In... Agent:
20120300538 - Sram strap row double well contact: An integrated circuit containing an SRAM array having a strap row. The strap row has a well tap active area that partially overlaps adjacent first polarity wells and a second polarity well that is located between the adjacent first polarity wells. A well contact plug is disposed on a top... Agent: Texas Instruments Incorporated
20120300537 - Sram strap row substrate contact: An integrated circuit containing an SRAM array having a strap row. The strap row has a substrate contact structure that includes a substrate contact plug and a tap layer.... Agent: Texas Instruments Incorporated
20120300536 - Sram strap row well contact: An integrated circuit containing an SRAM array having a strap row and an SRAM cell row. The strap row includes a tap connecting region that connects two columnar regions of a first polarity well. The strap row also includes a well tap active area in a tap connecting well region.... Agent: Texas Instruments Incorporated
20120300539 - Multibit cell with synthetic storage layer: Method for writing and reading more than two data bits to a MRAM cell comprising a magnetic tunnel junction formed from a read magnetic layer having a read magnetization, and a storage layer comprising a first storage ferromagnetic layer having a first storage magnetization, a second storage ferromagnetic layer having... Agent: Crocus-technology Sa
20120300540 - Transient heat assisted sttram cell for lower programming current: A memory cell including magnetic materials and heating materials, and methods of programming the memory cell are provided. The memory cell includes a free region, a pinned region, and a heating region configured to generate and transfer heat to the free region when a programming current is directed to the... Agent: Micron Technology, Inc.
20120300543 - Magnetic tunnel junctions with perpendicular magnetization and magnetic random access memory: In magnetic tunnel junctions manufactured with use of a ferromagnetic material having perpendicular magnetic anisotropy, a difference in record retention time depending on stored information due to an imbalance in thermal stability between a parallel state and an anti-parallel state of magnetization, which correspond to bit information, is alleviated. A... Agent: Hitachi, Ltd.
20120300541 - Storage element and storage device: A storage element includes: a storage layer which retains information by a magnetization state of a magnetic substance; a magnetization pinned layer having magnetization which is used as the basis of the information stored in the storage layer; and an interlayer of a non-magnetic substance provided between the storage layer... Agent: Sony Corporation
20120300542 - Storage element and storage device: A storage element includes a storage layer which has magnetization perpendicular to its film surface and which retains information by a magnetization state of a magnetic substance, a magnetization pinned layer having magnetization perpendicular to its film surface which is used as the basis of the information stored in the... Agent: Sony Corporation
20120300544 - Gated diode memory cells: A gated diode memory cell is provided, including one or more transistors, such as field effect transistors (“FETs”), and a gated diode in signal communication with the FETs such that the gate of the gated diode is in signal communication with the source of a first FET, wherein the gate... Agent: International Business Machines Corporation
20120300547 - 3-dimensional non-volatile memory device and method of manufacturing the same: A non-volatile memory device comprising a plurality of strings each including a drain select transistor, drain-side memory cells, a pipe transistor, source-side memory cells, and a source select transistor coupled in series, wherein the plurality of strings are arranged in a first direction and a second direction, and the strings... Agent:
20120300546 - Apparatus and methods including a bipolar junction transistor coupled to a string of memory cells: Some embodiments include apparatus and methods having a string of memory cells, a conductive line and a bipolar junction transistor configured to selectively couple the string of memory cells to the conductive line. Other embodiments including additional apparatus and methods are described.... Agent: Micron Technology, Inc.
20120300549 - Memory device page buffer configuration and methods: Memory devices and methods are described that include communication circuitry between page buffers in a memory array. Examples include communication circuitry that provide status information of page buffers that are directly adjacent to a given page buffer. The exchanged information can be used to adjust a given page buffer to... Agent:
20120300548 - Memory system and data reading method thereof: A memory system includes a memory and a memory controller operating to control the memory. The memory includes a random accessible memory including a memory cell array operable in a random access mode, a NAND flash memory, and a selection circuit making the memory controller operate either one of the... Agent:
20120300551 - Non-volatile memory cell healing: Embodiments of the present disclosure provide methods, devices, modules, and systems for healing non-volatile memory cells. One method includes biasing a first select gate transistor coupled to a string of memory cells at a first voltage, biasing a second select gate transistor coupled to the string at a second voltage,... Agent: Micron Technology, Inc.
20120300550 - Ramping pass voltage to enhance channel boost in memory device, with optional temperature compensation: In a non-volatile storage system, one or more substrate channel regions for an unselected NAND string are boosted during programming to inhibit program disturb. A voltage applied to one or more unselected word lines associated with at least a first channel region is increased during a program pulse time period... Agent:
20120300552 - Charge pump circuit with fast start-up: A charge pump circuit (300) includes a charge pump (330), and clocking circuitry that includes a clock generator (310) and a bypass circuit (320). The clocking circuitry generates clock signals and higher frequency alternative clock signals, for driving the charge pump. Upon start-up of the charge pump circuit and depending... Agent: Freescale Semiconductor, Inc.
20120300545 - Systems and methods for generating soft information in nand flash: Systems and methods are provided to generate soft information related to the threshold voltage of a memory cell. A range of threshold voltages for the memory cell is divided into subregions of threshold voltage values herein referred to as bins. An output of the memory cell in response to an... Agent: E I Du Pont De Nemours And Company
20120300553 - Method and apparatus of performing an erase operation on a memory integrated circuit: Various discussed approaches improve the over erase issue and the coupling effect, and include (A) multilevel contacts between (i) the first outer selected word line of an erase group, and (ii) the first unselected word line outside the ease group neighboring the first outer selected word line; (B) a sufficient... Agent: Macronix International Co., Ltd.
20120300554 - Sanitizing a non-volatile memory through charge accumulation: Method and apparatus for sanitizing a non-volatile memory, such as a flash memory array. In accordance with various embodiments, a memory cell is sanitized by using a write circuit to accumulate charge on a floating gate of the cell to a level such that application of a maximum available read... Agent: Seagate Technology LLC
20120300555 - Integrated circuit memory device: A semiconductor memory device includes a plurality of memory regions formed on one chip, each of the memory regions having a plurality of volatile memory cells that are formed with a density or capacity of 2̂K bits, where K is an integer greater than or equal to 0, and a... Agent: Samsung Electronics Co., Ltd.
20120300556 - Devices and systems including enabling circuits: Examples of devices and systems including enabling circuits are described. Two voltage supplies may be used to operate different portions of the devices, including peripheral circuits and I/O circuits. When the voltage supply to the peripheral circuits of one or more devices is disabled, the I/O circuits of that device... Agent: Micron Technology, Inc.
20120300558 - Method and apparatus for synchronizing data from memory arrays: According to one embodiment, a device for synchronizing data output from two or more memory arrays that includes a plurality of sense circuits configured to be responsive to a clock signal. The device further includes a plurality of latches and a tracking circuit. The tracking circuit may be configured to... Agent: Micron Technology, Inc.
20120300557 - Semiconductor cell and semiconductor device: A technology is a semiconductor cell and a semiconductor device capable of reducing the coupling capacitance between adjacent bit lines by forming a bit line junction region in a separated island shape when forming a buried bit line, thereby improving characteristics of the semiconductor devices. The semiconductor cell includes a... Agent: Hynix Semiconductor Inc.
20120300559 - Semiconductor memory including pads coupled to each other: A semiconductor memory is provided which includes: a first pad; a second pad disposed adjacent to the first pad; a first output buffer coupled to the first pad; and a second output buffer coupled to the second pad. The first pad is coupled to the second pad by metal.... Agent: Fujitsu Microelectronics Limited
20120300560 - Semiconductor memory devices including precharge using isolated voltages: A semiconductor memory device includes a memory cell array including a plurality of word lines, a plurality of bit lines including complementary pairs of bit lines, and a plurality of memory cells storing data; a sense amplifier coupled to the memory cell array and configured to sense voltage differences between... Agent: Samsung Electronics Co., Ltd.
20120300561 - Memory devices and program methods thereof: Memory devices and program methods thereof, the memory devices including a memory cell array with a three-dimensional structure, a voltage generator configured to supply a pass voltage and a program voltage to the memory cell array, and a control logic configured to make the rising slope of the pass voltage... Agent:
20120300562 - Method and circuit for testing a multi-chip package: A method and circuit for testing a multi-chip package is provided. The multi-chip package includes at least a memory chip, and the memory chip includes a number of memory cells. The method includes performing a normal read operation on the memory cells to check if data read from the memory... Agent: Macronix International Co., Ltd.
20120300563 - Advanced memory device having improved performance, reduced power and increased reliability: An advanced memory having improved performance, reduced power and increased reliability. A memory device includes a memory array, a receiver for receiving a command and associated data, error control coding circuitry for performing error control checking on the received command, and data masking circuitry for preventing the associated data from... Agent: International Business Machines Corporation
20120300564 - Strobe offset in bidirectional memory strobe configurations: A method and apparatus for determining correct timing for receiving, in a host in a memory system, of a normal toggle transmitted by an addressed memory chip on a bidirectional data strobe. An offset in the data strobe is established, either by commanding the addressed memory chip, in a training... Agent: International Business Machines Corporation
20120300565 - Skew signal generator and semiconductor memory device: A skew signal generator is provided which comprises a fuse signal generating unit for generating a plurality of fuse signals, and an encoder for generating skew signals including skew information of a wafer by encoding the fuse signals.... Agent: Hynix Semiconductor Inc.
20120300566 - Current sense amplifier with replica bias scheme: Some embodiments of the present disclosure relate to a sense amplifier architecture that facilitates fast and accurate read operations. The sense amplifier architecture includes a folded cascode amplifier for its first sense amplifier stage, and a pre-charge circuit to establish a pre-charge condition for a senseline and a reference senseline... Agent: Infineon Technologies Ag
20120300567 - Sense amplifier apparatus and methods: Some embodiments include apparatus and methods having a sense amplifier unit, a supply node to receive a supply voltage, and a line coupled to a memory cell of a device. The sense amplifier unit includes a circuit path coupled between the supply node and the line to carry a current... Agent: Atmel Corporation
20120300570 - Advanced memory device having improved performance, reduced power and increased reliability: An advanced memory having improved performance, reduced power and increased reliability. A memory device includes a memory array, a receiver for receiving a command and associated data, error control coding circuitry for performing error control checking on the received command, and data masking circuitry for preventing the associated data from... Agent: International Business Machines Corporation
20120300569 - Memory system and refresh control method thereof: A memory system and a refresh control method thereof are provided. The memory system includes a semiconductor memory device including a plurality of memory cells and a memory controller configured to generate a special command for searching for refresh information stored in the semiconductor memory device and to control a... Agent:
20120300568 - Method of refreshing a memory device, refresh address generator and memory device: A refresh address is generated with a refresh period for refreshing a memory device with refresh leveraging. A respective refresh is performed on a weak cell having a first address when the refresh address is a second address instead of on a first strong cell having the second address. A... Agent: Samsung Electronics Co., Ltd.11/22/2012 > 49 patent applications in 26 patent subcategories. recently filed with US Patent Office
20120294058 - Multi-die memory device: A multi-die memory device includes a first die of a first type and configured to electrically interface with an external processor via a first synchronous interface operating at a first clock rate, and at least one second die of a second type and configured for data storage. Each second die... Agent:
20120294059 - Stacked memory devices and memory systems including the same: At least one example embodiment discloses a stacked memory device including a plurality of stacked memory chips, each of the memory chips including a memory array, a plurality of through silicon vias (TSVs) operatively connected to the plurality of stacked memory chips, micro channels configured to access the memory arrays... Agent:
20120294060 - Semiconductor device: A semiconductor device capable of assessing and rewriting data at a desired timing is provided. A semiconductor device includes a register circuit, a bit line, and a data line. The register circuit includes a flip-flop circuit, a selection circuit, and a nonvolatile memory circuit electrically connected to the flip-flop circuit... Agent: Semiconductor Energy Laboratory Co., Ltd.
20120294061 - Word line divider and storage device: A word line divider which has a simplified circuit structure and can operate stably is provided. A storage device which has a simplified circuit structure and can operate stably is provided. A transistor whose leakage current is extremely low is connected in series with a portion between a word line... Agent: Semiconductor Energy Laboratory Co., Ltd.
20120294062 - Stack processor using a ferroelectric random access memory (f-ram) for code space and a portion of the stack memory space: A stack processor using a ferroelectric random access memory (F-RAM) for code space and a portion of the stack memory space. By storing some of the associated stacks in complementary metal oxide semiconductor (CMOS) or other volatile memory, read/write operations to only F-RAM would be obviated. As compared to an... Agent: Ramtron International Corporation
20120294063 - Memory element and memory device: There are provided a memory element and a memory device excellently operating at a low current, and having the satisfactory retention characteristics. The memory element includes a first electrode, a memory layer, and a second electrode in this order. The memory layer includes a resistance change layer disposed on the... Agent: Sony Corporation
20120294065 - Variable resistance memory device and method of fabricating the same: According to an example embodiment, a variable resistance memory device includes a lower electrode that includes a spacer-shaped first sub lower electrode and a second sub lower electrode covering a curved sidewall of the first sub lower electrode. The second sub lower electrode extends upward to protrude above the top... Agent:
20120294064 - Variable-resistance memory device and its operation method: Disclosed herein is a variable-resistance memory device including a first common line; a second common line; a storage element connected between the first common line and the second common line to serve as a storage element whose resistance changes in accordance with a voltage applied to the storage element; and... Agent: Sony Corporation
20120294068 - Memory device and signal processing circuit: A memory device which can keep a stored logic state even when the power is off is provided. A signal processing circuit including the memory device, which achieves low power consumption by stopping supply of power, is provided. The memory device includes a logic circuit including a first node, a... Agent: Semiconductor Energy Laboratory Co., Ltd.
20120294070 - Method for driving semiconductor device: A semiconductor device includes a nonvolatile memory cell including a writing transistor including an oxide semiconductor, a reading transistor including a semiconductor material different from that of the writing transistor, and a capacitor. Data is written to the memory cell by turning on the writing transistor so that a potential... Agent: Semiconductor Energy Laboratory Co., Ltd.
20120294067 - Semiconductor device and method for driving the same: In a semiconductor device performing pipeline processing with the use of a reading portion reading an instruction and an arithmetic portion performing an operation in accordance with the instruction, the instruction held in the reading portion is transmitted from the flip-flop to the memory when branch prediction turns out to... Agent: Semiconductor Energy Laboratory Co., Ltd.
20120294066 - Semiconductor storage device: A semiconductor storage device which stops and resumes the supply of power supply voltage without the necessity of saving and returning a data signal between a volatile storage device and a nonvolatile storage device is provided. In the semiconductor storage device, data is held in a data holding portion connected... Agent: Semiconductor Energy Laboratory Co., Ltd.
20120294069 - Signal processing circuit: A signal processing circuit includes a memory and a control portion configured to control the memory. The control portion includes a volatile memory circuit including data latch terminals, a first non-volatile memory circuit electrically connected to one of the data latch terminals, a second non-volatile memory circuit electrically connected to... Agent: Semiconductor Energy Laboratory Co., Ltd.
20120294071 - Spin-torque transfer magneto-resistive memory architecture: A system includes a processor and a memory array connected to the processor comprising a first memory cell comprising a first magnetic tunnel junction device having a first terminal connected to a first bit line and a second terminal, and a first field effect transistor having a source terminal connected... Agent: International Business Machines Corporation
20120294076 - Forming sublithographic heaters for phase change memories: A phase change memory with a heater with sublithographic dimensions may be achieved, in some embodiments, with lower thermal budget. The phase change memory may use a controlled etching process to reduce the lateral dimension of the heater.... Agent:
20120294073 - Method of driving phase change memory device capable of reducing heat disturbance: A method of driving phase change memory device which reduces or prevents unwanted heat disturbances from interfering with memory states in adjacent memory cells is presented. The phase change memory cells are disposed at word and bit line intersections. The method includes collectively erasing all of the memory cells as... Agent:
20120294074 - Phase change memory programming method and phase change memory: Disclosed is a method of programming a phase change memory (100) comprising a plurality of memory cells (10), each memory cell comprising a control terminal connected to a word line (30), and a current terminal connected to a bit line (20), comprising applying a first set pulse (Vb) having a... Agent: Nxp B.v.
20120294072 - Phase-change memory and a method of programming the same: According to embodiments of the present invention, a phase-change memory for storing data is provided. The phase-change memory includes a first dielectric material; a second dielectric material; and a phase-change material sandwiched between the first dielectric material and the second dielectric material, at least one of the first or second... Agent: Agency For Science, Technology And Research
20120294075 - Phase-change memory device: A phase-change memory device has a plurality of first wiring lines WL extending in parallel to each other, a plurality of second wiring lines BL which are disposed to cross the first wiring lines WL while being separated or isolated therefrom, and memory cells MC which are disposed at respective... Agent: Kabushiki Kaisha Toshiba
20120294078 - Bipolar spin-transfer switching: Orthogonal spin-transfer magnetic random access memory (OST-MRAM) uses a spin-polarizing layer magnetized perpendicularly to the free layer to achieve large spin-transfer torques and ultra-fast energy efficient switching. OST-MRAM devices that incorporate a perpendicularly magnetized spin-polarizing layer and a magnetic tunnel junction, which consists of an in-plane magnetized free layer and... Agent: New York University
20120294077 - Spin torque transfer memory cell structures and methods: Spin Torque Transfer (STT) memory cell structures and methods are described herein. One or more STT memory cell structures comprise an annular STT stack including a nonmagnetic material between a first ferromagnetic material and a second ferromagnetic material and a soft magnetic material surrounding at least a portion of the... Agent: Micron Technology, Inc.
20120294079 - Memory element and memory device: A memory element including a memory layer to hold the information by the magnetization state of a magnetic substance, a magnetization pinned layer having magnetization serving as a reference of the information stored in the memory layer, an intermediate layer formed from a nonmagnetic substance disposed between the memory layer... Agent: Sony Corporation
20120294080 - Memory device and method for driving memory device: A memory device according to the invention can be operated with a single potential, by which the use of a voltage converter can be excluded, leading to the reduction of power consumption. Such an operation can be achieved by utilizing capacitive coupling of a capacitor connected to a gate of... Agent: Semiconductor Energy Laboratory Co., Ltd.
20120294081 - Semiconductor device: In a sense circuit for DRAM memory cell a switch is provided between the bit line BL and local bit line LBL connected to the memory cells for isolation and coupling of these bit lines. The bit line BL is precharged to the voltage of VDL/2, while the local bit... Agent: Renesas Electronics Corporation
20120294082 - Semiconductor device: A semiconductor device comprises a transistor comprising a gate, a source, a drain, and a gate insulating layer, and an auxiliary line formed over the drain and electrically insulated from the drain. During a turn-off operation of the transistor, voltage to increase a resistance of the drain is supplied to... Agent: Hynix Semiconductor Inc.
20120294083 - Techniques for providing a semiconductor memory device: Techniques for providing a semiconductor memory device are disclosed. In one particular embodiment, the techniques may be realized as a semiconductor memory device including a plurality of memory cells arranged in an array of rows and columns, each memory cell. Each of the memory cell may include a first region... Agent: Micron Technology, Inc.
20120294086 - Adaptive programming for flash memories: A method to adjust the programming voltage in flash memory when the programming time exceeds specification. A method to adjust the programming voltage of flash memory after a predetermined number of erase/write cycles.... Agent: Texas Instruments Incorporated
20120294084 - Flash eeprom system with simultaneous multiple data sector programming and storage of physical block characteristics in other designated blocks: A non-volatile memory system is formed of floating gate memory cells arranged in blocks as the smallest unit of memory cells that are erasable together. One feature is the storage in separate blocks of the characteristics of a large number of blocks of cells in which user data is stored.... Agent:
20120294085 - Multi-partition architecture for memory: A multiple partition memory and architecture for concurrent operations reduces circuit overhead by providing a common read sense amplifier and program path for multiple partitions. Long separate datalines for read and algorithm operations allow concurrent operation and blockout of multiple operations in a single block of the memory.... Agent: Micron Technology, Inc.
20120294088 - Memory segment accessing in a memory device: Bit lines of a memory segment are read at substantially the same time by coupling a selected memory segment and, at some of the data lines of any intervening segments, to respective data caches. The bit lines of the unselected memory segments that are not used to couple the selected... Agent: Micron Technology, Inc.
20120294087 - Program method of nonvolatile memory device: A program method of a nonvolatile memory device includes applying a program voltage to a selected word line, applying a first pass voltage to at least one word line adjacent to the selected word line, applying at least one first middle voltage lower than the first pass voltage but higher... Agent:
20120294089 - Semiconductor memory device capable of memorizing multivalued data: In a memory cell array, a plurality of memory cells connected to word lines and bit lines are arranged in a matrix. A data storage circuit is connected to the bit lines and stores write data. The data storage circuit includes at least one static latch circuit and a plurality... Agent:
20120294090 - Current-sense amplifier with low-offset adjustment and method of low-offset adjustment thereof: A current-sense amplifier with low-offset adjustment and a low-offset adjustment method thereof are disclosed. The current-sense amplifier includes a sensing unit, an equalizing unit and a bias compensation unit. The sensing unit includes a sense amplifier, a latch circuit, a first precharged bit line, and a second precharged bit line.... Agent: National Tsing Hua University
20120294091 - Method for operating non-volatile memory device: A method for operating a non-volatile memory device which includes a plurality of memory cells serially coupled between a source selection transistor and a drain selection transistor, a first dummy memory cell coupled between the source selection transistor and the memory cells, and a second dummy memory cell coupled between... Agent:
20120294092 - Operating method of nonvolatile memory device and operating method of memory system including nonvolatile memory device: A nonvolatile memory device includes a plurality of memory cells and a plurality of monitor cells. The method of operating the device includes erasing the plurality of memory cells and the plurality of monitor cells, programming at least one first memory cell among the plurality of memory cells to a... Agent: Samsung Electronics Co., Ltd.
20120294093 - Semiconductor device and operating method thereof: An operating method of a semiconductor device includes precharging bit lines corresponding to selected memory cells, supplying a first verify voltage to a word line coupled to the selected memory cells and outputting programming states of the selected memory cells to the bit lines during a first time period, sensing... Agent:
20120294097 - Semiconductor memory device and driving method thereof: A semiconductor memory device includes a plurality of wordlines and a driver configured to, when an wordline of the plurality of wordlines is activated by an active command, drive at least one non-activated wordline neighboring the activated wordline and remaining non-activated wordlines with different wordline driving voltage levels during a... Agent:
20120294094 - Method and apparatus for memory fault tolerance: A plurality of data lines and a plurality of bit lines may be used to write to and/or read from an array of memory cells. A switching element may select among different mappings between the plurality of data lines and the plurality of bit lines. The array may, for example,... Agent:
20120294095 - Dynamic level shifter: A dynamic level shifter is disclosed. In one embodiment, a dynamic level shifter circuit may receive an input signal referenced to a first voltage of a first power domain, and may output a corresponding signal referenced to a second voltage into a second power domain. The dynamic level shifter circuit... Agent:
20120294096 - Memory device and semiconductor device including the memory device: A memory device includes a level shifter which includes a first input terminal, a second input terminal, a first output terminal configured to output a first signal, and a second output terminal configured to output an inverted signal of the first signal, a first buffer, a second buffer, a first... Agent: Semiconductor Energy Laboratory Co., Ltd.
20120294098 - Local io sense accelerator: A memory array includes: at least one differential local bit line pair; at least one differential global bit line pair; at least a column selection signal, for charging the differential local bit line pair to a predetermined voltage; at least an enable signal for coupling the differential local bit line... Agent:
20120294099 - Memory controller comprising adjustable transmitter impedance: Memory controllers, memory devices and methods are provided in which test data is transmitted and signal parameters are varied. The transmitted test data is read, and based on a comparison between transmitted test data and read test data a transmitter impedance is adjusted.... Agent: Infineon Technologies Ag
20120294100 - Method and apparatus for memory power and/or area reduction: A method and apparatus for memory power and/or area reduction. An array of memory cells may be scanned to detect faulty memory cells, if any, in the array. A supply voltage Vmem applied to the array of memory cells may be controlled based on a result of the scan, and... Agent:
20120294103 - Controlling ac disturbance while programming: A system and methodology that can minimize disturbance during an AC operation associated with a memory, such as, program, read and/or erase, is provided. The system pre-charges all or a desired subset of the bit lines in a memory array to a specified voltage, during an AC operation to facilitate... Agent: Spansion LLC
20120294102 - Memory device and signal processing circuit: A memory device which can keep a stored logic state even when the power is off is provided. A signal processing circuit including the memory device, which achieves low power consumption by stopping supply of power, is provided. A memory device includes a logic circuit including a first node and... Agent: Semiconductor Energy Laboratory Co., Ltd.
20120294101 - Method and apparatus for selective dram precharge: Apparatus and method for using a precharge command in which a plurality of address lines are individually used to specify which banks of memory cells within a memory device have an open row that is to be closed... Agent:
20120294104 - Nonvolatile memory systems using time-dependent read voltages and methods of operating the same: An elapsed time with respect to a programming operation on a memory cell of a nonvolatile memory is determined, a read voltage is adjusted based on the determined elapsed time and a read operation is performed on the memory cell using the adjusted read voltage. Determining the elapsed time may... Agent: Samsung Electronics Co., Ltd.
20120294105 - Semiconductor device and memory system comprising the same: According to an embodiment, a semiconductor device includes a power supply switch and a first regulator. One end of the power supply switch is connected to an input terminal. The other end of the power supply switch is connected to an output terminal. The first regulator includes a power supply... Agent: Kabushiki Kaisha Toshiba
20120294106 - Internal command generation circuit: The internal command generation circuit includes a burst pulse generation unit and a pulse shifting unit. The burst pulse generation unit is configured to receive a command for a read or write operation, and generate a first burst pulse. The pulse shifting unit is configured to shift the first burst... Agent: Sk Hynix Inc.11/15/2012 > 52 patent applications in 32 patent subcategories. recently filed with US Patent Office
20120287692 - Read threshold setting based on temperature integral: A method for data storage in a memory that includes multiple analog memory cells fabricated using respective physical media, includes identifying a group of the memory cells whose physical media have deteriorated over time below a given storage quality level. A rejuvenation process, which causes the physical media of the... Agent:
20120287693 - Semiconductor device and memory device including semiconductor device: To provide a semiconductor device whose power can be turned off without the need for a peripheral circuit for data to escape temporarily and in which stored data is not lost even in an off state of the power of the device, and a memory device including the semiconductor device.... Agent: Semiconductor Energy Laboratory Co., Ltd.
20120287695 - Semiconductor memory device: A semiconductor memory device includes a first wiring region and a second wiring region located adjacent to the first wiring region. First lines located in the first wiring region include a first portion, a first lead portion and first inclined portion. Second lines located in the second wiring region include... Agent:
20120287694 - Three-dimensional semiconductor memory device: An embodiment is directed to a method of fabricating a semiconductor memory device, the method including preparing a substrate having a cell array region and a contact region, forming a thin film structure on the substrate, including forming sacrificial film patterns isolated horizontally by a lower isolation region, the lower... Agent:
20120287696 - Storage element and storage device: A storage element includes a storage layer having a magnetization perpendicular to a layer surface and storing information according to a magnetization state of a magnetic material; a fixed magnetization layer having the magnetization as a reference of the information of the storage layer and perpendicular to the layer surface;... Agent: Sony Corporation
20120287697 - Semiconductor storage device: A semiconductor storage device crystallizes variable resistive element material layers arranged on side surfaces of multiple semiconductor layers in a stacked structure concurrently by applying a first current to any one of semiconductor layers in the stacked structure, and thereafter applies a second current to semiconductor layers other than a... Agent: Hitachi, Ltd.
20120287698 - Using a bit specific reference level to read a memory: A voltage derived from accessing a selected bit using one read current may be utilized to read a selected bit of an untriggered phase change memory after the read current is changed. As a result, different reference voltages may be used to sense the state of more resistive versus a... Agent:
20120287700 - Gain cell semiconductor memory device and driving method thereof: A memory cell including two transistors and one capacitor, which is known as a gain cell, is improved. One electrode of the capacitor is connected to a bit line, and the other electrode thereof is connected to a drain of a write transistor. A source of the write transistor is... Agent: Semiconductor Energy Laboratory Co., Ltd.
20120287702 - Memory circuit and electronic device: To provide a nonvolatile memory circuit having a novel structure. A first memory circuit, a second memory circuit, a first switch, a second switch, and a phase inverter circuit are included. The first memory circuit includes a first transistor formed using an oxide semiconductor film, a second transistor, a third... Agent: Semiconductor Energy Laboratory Co., Ltd.
20120287703 - Semiconductor device: When a CPU provided with a latch memory is operated, a constant storage method or an end storage method is selected depending on what is processed by the CPU; thus, the CPU provided with a latch memory has low power consumption. When the CPU provided with a latch memory is... Agent: Semiconductor Energy Laboratory Co., Ltd.
20120287701 - Semiconductor device and method for driving semiconductor device: A memory device with low power consumption and a signal processing circuit including the memory device are provided. In a memory element including a phase-inversion element by which the phase of an input signal is inverted and the signal is output such as an inverter or a clocked inverter, a... Agent: Semiconductor Energy Laboratory Co., Ltd.
20120287699 - Semiconductor memory device: A semiconductor memory device selects one of a plurality of memory cells as a dummy memory cell. The dummy memory cell is connected to a bit line that is complementary to a bit line connected to a selected memory cell. This technique advantageously compensates capacitance of the bit line. The... Agent: Hynix Semiconductor Inc.
20120287704 - Spin current generator for stt-mram or other spintronics applications: Spin current generators and systems and methods for employing spin current generators. A spin current generator may be configured to generate a spin current polarized in one direction, or a spin current selectively polarized in two directions. The spin current generator may by employed in spintronics applications, wherein a spin... Agent: Micron Technology, Inc.
20120287705 - Spin-torque transfer magneto-resistive memory architecture: A method for operating a memory array device, includes initiating a write “0” state in the device, wherein the initiating the write “0” state includes inducing a first voltage in a word line of the device; and inducing a second voltage in a first bit line (BLTE) of the device.... Agent: International Business Machines Corporation
20120287706 - Isolation device free memory: An integrated circuit memory is based on isolation device free memory cells. The memory cells are passively coupled to bit lines and word lines. The memory cells include an anti-fuse element and an element of phase change material in series. A rupture filament through the anti-fuse layer acts as an... Agent: Macronix International Co., Ltd.
20120287707 - Optoelectronic memory devices: A structure. The structure includes a substrate, a resistive/reflective region on the substrate, and a light source/light detecting and/or a sens-amp circuit configured to ascertain a reflectance and/or resistance change in the resistive/reflective region. The resistive/reflective region includes a material having a characteristic of the material's reflectance and/or resistance being... Agent: International Business Machines Corporation
20120287709 - Non volatile semiconductor memory device and manufacturing method thereof: In accordance with an embodiment, a non volatile semiconductor memory device includes a substrate, a first electrode, a functional film, and a second electrode. The first electrode is provided on the substrate. The functional film is located on the first electrode and serves as a storage medium. The second electrode... Agent: Kabushiki Kaisha Toshiba
20120287708 - Selection device for a spin-torque transfer magnetic random access memory: A spin-torque transfer magnetic random access memory (STT-MRAM) that includes a magnetic bit coupled between a first conductor line and a selection device. The selection device includes at least two transistors. The selection device is operative to (a) select the magnetic bit for a spin-torque transfer (STT) write operation when... Agent: Honeywell International Inc.
20120287711 - Flash memory device and memory system including the same: A flash memory device includes a memory cell array, a temperature sensing unit, and a control unit. The memory cell array is configured to store a plurality of pieces of configuration data corresponding to respective temperature levels of the flash memory device, the pieces of configuration data indicative of respective... Agent: Samsung Electronics Co., Ltd.
20120287710 - Nonvolatile semiconductor memory device capable of speeding up write operation: According to one embodiment, a nonvolatile semiconductor memory device includes a memory cell array, write circuit, memory unit, and voltage generation unit. A plurality of strings is arranged in the memory cell array, each of which includes a plurality of memory cells connected to word lines. The write circuit selects... Agent:
20120287712 - Semiconductor device: A semiconductor device including a logic circuit capable of decreasing a leakage current occurred during a standby state is provided. The semiconductor device includes a power supply portion for supplying a first operation voltage or a second operation voltage smaller than the first operation voltage; a P-type low-threshold transistor Tp... Agent: Winbond Electronics Corp.
20120287714 - Increased capacity heterogeneous storage elements: Providing increased capacity in heterogeneous storage elements including a method for reading from memory. The method includes receiving a read word from a block of memory cells, where physical characteristics of the memory cells support different sets of data levels. The read word is separated into two or more virtual... Agent: International Business Machines Corporation
20120287713 - Nonvolatile memory device and method for operating the same: A nonvolatile memory device includes a plurality of memory blocks and a high voltage application unit configured to apply a high voltage to a word line of a memory block unselected from among the plurality of memory blocks and float the word line, during the erase operation.... Agent:
20120287715 - Zero cost nvm cell using high voltage devices in analog process: A non-volatile memory cell and array structure is disclosed situated within a high voltage region of an integrated circuit. The cell utilizes capacitive coupling based on an overlap between a gate and a drift region to impart a programming voltage. Programming is effectuated using a drain extension which can act... Agent:
20120287716 - Using channel-to-channel coupling to compensate floating gate-to-floating gate coupling in programming of non-volatile memory: In a non-volatile storage system, during a verify operation, a verify voltage of a currently-sensed target data state is applied to a selected word line. A higher, nominal bit line voltage is used for the storage elements which have the currently-sensed target data state and a verify status of pass... Agent:
20120287717 - Flash memory device and associated charge pump circuit: A charge pump circuit comprises a first booster set, a second booster group, and a detecting circuit. The first booster set receives a supply voltage and generates a first output voltage. The detecting circuit generates a detecting signal depending on the voltage level of the first output voltage. The second... Agent: Elite Semiconductor Memory Technology Inc.
20120287719 - Flash memory device having seed selector circuit: A flash memory device includes a memory cell array, a seed selector circuit, and a randomizing and de-randomizing circuit. The memory cell array includes memory cells forming multiple pages. The seed selector circuit stores seeds corresponding to the multiple pages, respectively. The randomizing and de-randomizing circuit randomizes data to be... Agent: Samsung Electronics Co., Ltd.
20120287718 - Programming memory cells: Methods for programming, memory devices, and methods for reading are disclosed. One such method for programming a memory device (e.g., an SLC memory device) includes encoding a two level data stream to a three level stream prior to programming the memory.... Agent: Micron Technology, Inc.
20120287720 - Semiconductor memory device and method of programming the same: A semiconductor memory device and a method of programming the same are provided which can improve the program accuracy by classifying cells depending on a program status of memory cells during a program operation to control a bit line program voltage. The method comprises classifying memory cells to be programmed... Agent: Sk Hynix Inc.
20120287722 - Dynamic data caches, decoders and decoding methods: Examples described include dynamic data caches (DDCs), decoders and decoding methods that may fit into a smaller width area. The DDCs, decoders and decoding method may be used in flash memory devices. A single column select line may be provided to select a plurality of cached bytes, while a second... Agent: Micron Technology, Inc.
20120287721 - Programming method for nonvolatile semiconductor memory device: A method for programming a plurality of memory cells of a nonvolatile semiconductor memory device comprises the steps of: sequentially performing a plurality of divide-by-2 operations on the plurality of memory cells; generating a plurality of reduced groups from the memory cells after each of the divide-by-2 operations is performed;... Agent: Elite Semiconductor Memory Technology Inc.
20120287723 - Method and circuit to discharge bit lines after an erase pulse: Disclosed here in a method that comprises performing an erase operation on multiple cells in a memory device, the performing comprising applying an erase voltage to the multiple cells, bit lines coupled to the multiple cells being thereby charged up; and discharging the bit lines by coupling the bit lines... Agent: Elpida Memory, Inc.
20120287724 - Method of programming memory and memory apparatus utilizing the method: A method of programming a memory is provided. The memory has a first cell, having a first S/D region and a second S/D region shared with a second cell. The second cell has a third S/D region opposite to the second S/D region. When programming the first cell, a first... Agent: Macronix International Co., Ltd.
20120287726 - Architecture and method for memory programming: Methods of programming a memory, memory devices, and systems are disclosed, for example. In one such method, each data line of a memory to be programmed is biased differently depending upon whether one or more of the data lines adjacent the data line are inhibited. In one such system, a... Agent: Micron Technology, Inc.
20120287725 - Memory controller with selective data transmission delay: A DRAM controller component generates a timing signal and transmits, to a DRAM, (i) write data that requires a first time interval to propagate from the DRAM controller component to the DRAM and to be sampled by the DRAM on one or more edges of the timing signal, (ii) a... Agent:
20120287727 - Dram refresh method and system: A DRAM refresh method used with a memory system organized into rows of memory cells, each of which has an associated data retention time, with the system arranged to refresh predefined blocks of memory cells simultaneously. For each block of memory cells that are to be refreshed simultaneously, the minimum... Agent: Inphi Corporation
20120287728 - Nonvolatile memory device: A nonvolatile memory device is provided relating to a test operation for a Low Power Double-Data-Rate (LPDDR) nonvolatile memory device. The nonvolatile memory device comprises a command decoder configured to decode a test mode signal in a test mode to output program and erasure signals into a memory, an address... Agent: Sk Hynix Inc.
20120287729 - Semiconductor device: A semiconductor device includes a memory cell array including a plurality of memory array basic units, a first bus for transfer of address/control signals, including a first buffer circuit operating as a pipeline register, a second bus for bidirectional transfer of write/read data, including a second buffer circuit operating as... Agent: Renesas Electronics Corporation
20120287730 - Non-volatile memory device and sensing method thereof: A non-volatile memory device and a sensing method thereof are disclosed, which can sense multi-level data using resistance variation. The non-volatile memory device includes a cell array and a sensing unit. The cell array includes a plurality of unit cells where data is read out or written. The sensing unit... Agent: Hynix Semiconductor Inc.
20120287731 - Semiconductor memory apparatus: A semiconductor memory apparatus includes: a plurality of memory blocks; and a plurality of temperature sensors disposed adjacent to the respective memory blocks and configured to output a plurality of preliminary temperature sensing signals whose voltage levels are controlled in response to temperature change. A preliminary temperature sensing signal indicating... Agent: Sk Hynix Inc.
20120287732 - Apparatus and methods of driving signal: Apparatus and methods for driving a signal are disclosed. An example apparatus includes a pre-driver circuit and a driver circuit. The pre-driver circuit includes a step-down transistor and the driver circuit includes a pull-down transistor configured to be coupled to a reference voltage. In a first mode, the step-down transistor... Agent: Micron Technology, Inc.
20120287734 - Continuous programming of non-volatile memory: A system connects a signal driver to a first control line that is connected to a first non-volatile storage element, charges the first control line while the signal driver is connected to the first control line, disconnects the signal driver from the first control line while the first control line... Agent:
20120287733 - Memory circuitry with write boost and write assist: Memory circuitry 2 includes a memory cell 12 coupled to a plurality of bit line pairs 18, 24 providing multiple access ports. Write boost circuitry 36 serves to increase a write voltage applied to write a data value into the memory cell during at least a boost period of a... Agent: Arm Limited
20120287735 - Current control circuit: A current control device is disclosed, which reduces a standby current of a semiconductor memory device and a turn-on current of a transistor. The current control device includes an input controller configured to combine a trigger signal and a set signal controlling a circuit operation status, and a drive unit... Agent: Hynix Semiconductor Inc.
20120287736 - Sram write assist apparatus: An SRAM write assist apparatus comprises a timer unit and a voltage divider. The voltage divider unit is configured to divide a voltage potential down to a lower level. The output of the voltage divider is connected to a memory cell in a write operation. The timer unit is configured... Agent: Taiwan Semiconductor Manufacturing Company, Ltd.
20120287737 - Repairing circuit for memory circuit and method thereof and memory circuit using the same: A novelty repairing method and circuit are provided by the embodiments of the present invention, wherein the input/output (IO) compression manner can be used therein to reduce the access time during the chip probing 1 (CP1) test, and each redundant column selected line (RCSL) can be divided into several partial... Agent: Elite Semiconductor Memory Technology Inc.
20120287738 - Measuring device and a measuring method with histogram formation: A measuring device for the storage of test values and associated addresses provides a first storage region (30) and a second storage region (33). The first storage region (30) comprises a first number of memory cells (32) of a first cell size (31). The second storage region (33) comprises a... Agent: Rohde & Schwarz Gmbh & Co. Kg
20120287739 - Circuit and method for controlling leakage current in random access memory devices: A circuit for controlling leakage current in random access memory devices comprises a pre-charge equalization circuit. The pre-charge equalization circuit provides a pre-charge voltage to a pair of complementary bit lines of a memory cell of a random access memory device in accordance with a pre-charge signal. When the memory... Agent: Elite Semiconductor Memory Technology Inc.
20120287741 - Semiconductor storage: An SRAM macro operates in a normal operation mode in which a plurality of memory-cell array blocks are accessible and in a low power mode in which bit lines in the memory-cell array blocks are left floating. When the SRAM macro returns from the low power mode to the normal... Agent: Fujitsu Semiconductor Limited
20120287740 - Sense amplifiers, memories, and apparatuses and methods for sensing a data state of a memory cell: Sense amplifiers, memories, and apparatuses and methods for sensing a data state of a memory cell are disclosed. An example apparatus includes a differential amplifier configured to amplify a voltage difference between voltages applied to first and second amplifier input nodes to provide an output. The example apparatus further includes... Agent: Micron Technology, Inc.
20120287742 - Circuit and method for outputting refresh execution signal in memory device: A circuit for outputting a refresh execution signal to a memory cell of a memory device in an auto-refresh mode comprises a first frequency dividing unit, a first selection circuit, a second frequency dividing unit, and a second selection circuit. The first frequency dividing unit receives an auto-refresh signal from... Agent: Elite Semiconductor Memory Technology Inc.
20120287743 - Clock handoff circuit and clock handoff method: A clock handoff circuit outputting data in synchronism with a first clock input thereto as output data in synchronism with a second clock, includes: a dual port RAM capable of performing writing and reading independently of each other; a write address control section controlling write addresses of the dual port... Agent:11/08/2012 > 45 patent applications in 29 patent subcategories. recently filed with US Patent Office
20120281449 - Semiconductor chip, memory chip, semiconductor package and memory system: A semiconductor chip includes a plurality of signal and power pads; and a plurality of chip selection pads, wherein at least one of the plurality of chip selection pads includes a normal pad and an inverse pad.... Agent: Samsung Electronics Co., Ltd.
20120281450 - Electrically programmable fuse module in semiconductor device: A semiconductor device has an e-fuse module and a programming current generator. The e-fuse module includes an array of electrically programmable e-fuse elements. The programming current generator has a set of reference transistor elements, a selector for actuating the reference transistor elements to generate a selected reference current, and a... Agent: Freescale Semiconductor, Inc
20120281451 - Ferro-resistive random access memory (ferro-rram), operation method and manufacturing method thereof: The invention provides a Ferro-RRAM, a method of operating the Ferro-RRAM, and a method of fabricating the Ferro-RRAM, and pertains to the technical field of memory. The Ferro-RRAM comprises an upper electrode, a lower electrode, and a ferroelectric semiconducting thin-film layer provided between the upper electrode and the lower electrode... Agent: Fudan University
20120281454 - Method and apparatus for decoding memory: A thin-film memory may include a thin-film transistor-free address decoder in conjunction with thin-film memory elements to yield an all-thin-film memory. Such a thin-film memory excludes all single-crystal electronic devices and may be formed, for example, on a low-cost substrate, such as fiberglass, glass or ceramic. The memory may be... Agent:
20120281452 - Resistive random memory cell and memory: The present disclosure provides a resistive random memory cell and a resistive random memory. The resistive random memory cell comprises an upper electrode, a resistive layer, an intermediate electrode, an asymmetric tunneling barrier layer, and a lower electrode. The upper electrode, the resistive layer, and the intermediate electrode constitute a... Agent:
20120281453 - Variable resistance nonvolatile storage device: The variable resistance nonvolatile storage device includes a memory cell (300) that is formed by connecting in series a variable resistance element (309) including a variable resistance layer (309b) which reversibly changes based on electrical signals each having a different polarity and a transistor (317) including a semiconductor substrate (301)... Agent:
20120281455 - Semiconductor device: A semiconductor device that has a simple peripheral circuit configuration, is unlikely to deteriorate due to repetitive data writing operations, and is used as a nonvolatile switch. Even when supply of a power supply voltage is stopped, data on a conduction state is held in a data retention portion connected... Agent: Semiconductor Energy Laboratory Co., Ltd.
20120281456 - Semiconductor memory device: The semiconductor memory device includes: a memory circuit including a transistor including an oxide semiconductor in a semiconductor layer; a capacitor for storing electric charge for reading data retained in the memory circuit; a charge storage circuit for controlling storage of electric charge in the capacitor; a data detection circuit... Agent: Semiconductor Energy Laboratory Co., Ltd.
20120281457 - Data dependent sram write assist: A semiconductor chip has an SRAM (static random access memory). The SRAM includes a data dependent write assist circuit which, on writes, reduces a supply voltage on one of a cross coupled inverter pair in an SRAM cell, thereby making it easier to overcome the one of the cross coupled... Agent: International Business Machines Corporation
20120281459 - Ultra low power memory cell with a supply feedback loop configured for minimal leakage operation: A memory cell with an internal supply feedback loop is provided herein. The memory cell includes a latch having two storage nodes Q and QB, and a supply node. A gating device couples the supply node of the latch to the supply voltage. The gating device is controlled by a... Agent: Ben-gurion University Of The Negev Research And Development Authority
20120281458 - Ultra low power sram cell circuit with a supply feedback loop for near and sub threshold operation: An SRAM memory cell with an internal supply feedback loop is provided herein. The memory cell includes a latch that has a storage node Q, a storage node QB, a supply node, and a ground node. The supply node is coupled via a gating device to a supply voltage and... Agent: Ben-gurion University Of The Negev Research And Development Authority
20120281465 - High density magnetic random access memory: One embodiment of a magnetic memory device comprises a substrate and a plurality of planar memory arrays stacked on the substrate, each memory array includes a plurality of parallel first conductive lines, each first conductive line includes a ferromagnetic cladding, a plurality of parallel second conductive lines overlapping the first... Agent:
20120281463 - Magnetoresistive effect element, and magnetic random access memory: e
20120281460 - Noncontact writing of nanometer scale magnetic bits using heat flow induced spin torque effect: A mechanism is provided for noncontact writing. Multiple magnetic islands are provided on a nonmagnetic layer. A reference layer is provided under the nonmagnetic layer. A spin-current is caused to write a state to a magnetic island of the multiple magnetic islands by moving a heat source to heat the... Agent: International Business Machines Corporation
20120281464 - Raising programming currents of magnetic tunnel junctions using word line overdrive and high-k metal gate: A method of operating magneto-resistive random access memory (MRAM) cells includes providing an MRAM cell, which includes a magnetic tunneling junction (MTJ) device; and a selector comprising a source-drain path serially coupled to the MTJ device. The method further includes applying an overdrive voltage to a gate of the selector... Agent: Taiwan Semiconductor Manufacturing Company, Ltd.
20120281461 - Semiconductor storage device: A memory includes MTJ elements. Active areas are separated to correspond to cell transistors, respectively, and extend in a first direction substantially orthogonal to an extending direction of gates of the cell transistors. The active areas are arranged in the first direction and constitute a plurality of active area columns.... Agent: Kabushiki Kaisha Toshiba
20120281462 - Storage element and storage device: A storage element includes a storage layer that stores information on the basis of a magnetization state of a magnetic material; a fixed magnetization layer that has a magnetization serving as a reference of the information stored in the storage layer; an interlayer that is formed of a nonmagnetic material... Agent: Sony Corporation
20120281466 - Phase change memory elements using energy conversion layers, memory arrays and systems including same, and methods of making and using same: A phase change memory element and method of forming the same. The memory element includes a phase change material layer electrically coupled to first and second conductive material layers. A energy conversion layer is formed in association with the phase change material layer, and electrically coupled to a third conductive... Agent:
20120281467 - Magnonic magnetic random access memory device: A mechanism is provided for bidirectional writing. A structure includes a reference layer on top of a tunnel barrier, a free layer underneath the tunnel barrier, a metal spacer underneath the free layer, an insulating magnet underneath the metal spacer, and a high resistance layer underneath the insulating layer. The... Agent: International Business Machines Corporation
20120281468 - Semiconductor device and semiconductor memory device: The present disclosure provides a semiconductor device and a semiconductor memory device. The semiconductor device can be used as a memory cell, and may comprise a first P-type semiconductor layer, a first N-type semiconductor layer, a second P-type semiconductor layer, and a second N-type semiconductor layer arranged in sequence. A... Agent:
20120281469 - Semiconductor device: Noise generated on a word line is reduced without increasing a load on the word line. A semiconductor device is provided in which a plurality of storage elements each including at least one switching element are provided in matrix; each of the plurality of storage elements is electrically connected to... Agent: Semiconductor Energy Laboratory Co., Ltd.
20120281473 - Card controller controlling semiconductor memory including memory cell having charge accumulation layer and control gate: A card controller includes an arithmetic processing device. The controller writes data to a semiconductor memory having a first memory block and a second memory block each including a plurality of nonvolatile memory cells each configured to hold at least 2 bits, data in the first memory block and data... Agent:
20120281472 - Highly compact non-volatile memory and method thereof: A non-volatile memory device capable of reading and writing a large number of memory cells with multiple read/write circuits in parallel has an architecture that reduces redundancy in the multiple read/write circuits to a minimum. The multiple read/write circuits are organized into a bank of similar stacks of components. In... Agent:
20120281471 - Memory page buffer: Various embodiments address various difficulties with source side sensing difficulties in various memory architectures, such as 3D vertical gate flash and multilevel cell memory. One such difficulty is that with source side sensing, the signal amplitude is significantly smaller than drain side sensing. Another such difficulty is the noise and... Agent: Macronix International Co., Ltd.
20120281474 - Data line management in a memory device: Methods for programming a memory device, memory devices configured to perform the disclosed programming methods, and memory systems having a memory device configured to perform the disclosed programming methods are provided. According to at least one such method, multiple pages of memory cells are inhibited during a programming operation such... Agent: Micron Technology, Inc.
20120281475 - Nand flash memory device and method of making same: An integrated circuit includes a NAND string including a string selection transistor SST and a ground selection transistor GST disposed at either end of series-connected memory storage cells MC. Each of the memory storage cells is a memory transistor having a floating gate, and at least one of the string... Agent:
20120281476 - Memory apparatus and methods: Embodiments of apparatus and methods having a memory device can include a line to exchange information with a string of memory cells and a transistor coupled between the string of memory cells and the line. Such a memory device can also include a module configured to couple a gate of... Agent: Micron Technology, Inc.
20120281477 - Semiconductor memory device: According to one embodiment, a semiconductor memory device includes a memory cell array includes a plurality of cell units each composed of a plurality of memory cells which are arranged at intersections of a plurality of bit lines and a plurality of word lines and whose current paths are connected... Agent:
20120281478 - Thermally assisted flash memory with diode strapping: A memory includes an array of memory cells including rows and columns. The memory includes circuitry coupled to the word lines applying a first bias voltage to a first set of spaced-apart locations on a word line or word lines in the array, while applying a second bias voltage different... Agent: Macronix International Co., Ltd.
20120281479 - Detection of broken word-lines in memory arrays: Techniques and corresponding circuitry are presented for the detection of broken wordlines in a memory array. One example considers an “inter-word-line” comparison where the program loop counts of different word-lines are compared in order to determine whether a word-line may be defective. For example, the number of programming pulses needed... Agent:
20120281480 - Sensing operations in a memory device: Methods for sensing, method for programming, memory devices, and memory systems are disclosed. In one such method for sensing, a counting circuit generates a count output and a translated count output. The count output is converted into a time varying voltage that biases a word line coupled to memory cells... Agent: Micron Technology, Inc.
20120281470 - Nonvolatile semiconductor memory: A nonvolatile semiconductor memory includes a first power supply voltage pad to which a first power supply voltage required for a writing, reading or erasing operation of the memory cells is applied. The nonvolatile semiconductor memory includes a second power supply voltage pad to which a second power supply voltage... Agent: Kabushiki Kaisha Toshiba
20120281481 - Thermally assisted dielectric charge trapping flash: A memory device includes an array of dielectric charge trapping structures memory cells including word lines and bit lines. Control circuitry is coupled to the array arranged to control read, program and erase operations. A controller is arranged with supporting circuitry thermally annealing charge trapping structures in the memory cells... Agent: Macronix International Co., Ltd.
20120281482 - Word line drivers in non-volatile memory device and method having a shared power bank and processor-based systems using same: A word line driver system that utilizes a voltage selection circuit to supply one of several voltages to an output node coupled to a plurality of word line control circuits. Each word line control circuit is coupled to a respective word line in an array of non-volatile memory cells. The... Agent: Micron Technology, Inc.
20120281483 - Systems and methods for adjusting threshold voltage: Systems and methods for adjusting threshold voltage. A threshold voltage of a transistor of an integrated circuit is measured. A bias voltage, which when applied to a body well of the transistor corrects a difference between the threshold voltage and a desired threshold voltage for the transistor, is determined. The... Agent:
20120281484 - Non-volatile memory device and mosfet using graphene gate electrode: Disclosed herein is a method of remarkably improving the memory characteristics of a non-volatile memory device and the device reliability of the MOSFET using graphene which is a novel material that has a high work function and does not cause the deterioration of a lower insulating film.... Agent: Korea Advanced Institute Of Science And Technology
20120281485 - Data storage system, electronic system, and telecommunications system: A data storage system comprising a plurality of buffers configured to store data, a read pointer to indicate a particular one of the plurality of buffers from which data should be read, and a write pointer to indicate a particular one of the plurality of buffers to which data should... Agent: Micron Technology, Inc.
20120281486 - Semiconductor memory device and method with auxiliary i/o line assist circuit and functionality: A semiconductor memory device includes an I/O line for transmitting read data that has been read from a memory cell, a plurality of driver circuits for driving the I/O line on the basis of the read data, a read circuit for receiving the read data transmitted through the I/O line,... Agent: Elpida Memory, Inc
20120281487 - Semiconductor memory device and method of controlling the same: According to one embodiment, a semiconductor memory device includes a memory cell array includes a plurality of memory cell units which are arranged at intersections of a plurality of bit lines and a plurality of word lines and whose current paths are connected in series, a voltage generator circuit which... Agent:
20120281488 - Semiconductor memory device and method of operation the same: A semiconductor memory device includes a first plane and a second plane each configured to include a plurality of memory cells, and a data transfer circuit configured to transfer first data, stored in the memory cells of the first plane, to the second plane and transfer second data, stored in... Agent:
20120281489 - Low power memory device: “A method of operation within a memory device comprises receiving address information and corresponding enable information. The address information includes a row address that specifies a row of storage cells within a storage array of the memory device, and the enable information includes first and second enable values that correspond... Agent: Rambus Inc.
20120281490 - Semiconductor device, semiconductor module and method of manufacturing the same: A technology is capable of improving a process margin in forming a bit line and reducing bit line resistance to improve characteristic of the semiconductor device by forming a cell bit line in a double layer structure are provided. The semiconductor device includes a buried gate buried within a cell... Agent: Hynix Semiconductor Inc.
20120281491 - Data processing system having brown-out detection circuit: A data processing system includes a brown-out detection circuit with a first resistive element, a first transistor, a second transistor, and a comparator. The first resistive element has a first terminal coupled to a first power supply voltage terminal, and a second terminal. The first transistor has a first current... Agent: Freescale Semiconductor, Inc.
20120281492 - Method and apparatus for decoding memory: A thin-film memory may include a thin-film transistor-free address decoder in conjunction with thin-film memory elements to yield an all-thin-film memory. Such a thin-film memory excludes all single-crystal electronic devices and may be formed, for example, on a low-cost substrate, such as fiberglass, glass or ceramic. The memory may be... Agent:
20120281493 - Apparatus for memory interface configuration and associated methods: An apparatus includes a memory circuit and an interface circuit. The interface circuit is coupled to the memory circuit. The interface circuit selects a phase value of clock signal adapted to clock the memory circuit.... Agent: Altera Corporation11/01/2012 > 51 patent applications in 25 patent subcategories. recently filed with US Patent Office
20120275207 - Sram cell parameter optimization: An integrated circuit having an SRAM cell includes a pair of cross-coupled inverters with first driver and load transistors connected to provide a first storage node and second driver and load transistors connected to provide a second storage node. The SRAM cell also includes first and second pass gate transistors... Agent: Texas Instruments Incorporated
20120275208 - Reliable electrical fuse with localized programming and method of making the same: An electrical fuse has an anode contact on a surface of a semiconductor substrate. The electrical fuse has a cathode contact on the surface of the semiconductor substrate spaced from the anode contact. The electrical fuse has a link within the substrate electrically interconnecting the anode contact and the cathode... Agent: International Business Machines Corporation
20120275209 - Embedded non-volatile memory circuit for implementing logic functions across periods of power disruption: A circuit having an autonomous ferroelectric memory latch (AML) is disclosed. An AML characterized by an AML input, an AML output, a first AML power contact, a second AML power contact and an AML state, and a first switch in series with one of the AML input or the AML... Agent:
20120275210 - Non-volatile storage system with dual block programming: A non-volatile storage system is disclosed that includes a plurality of blocks of non-volatile storage elements, a plurality of word lines connected to the blocks of non-volatile storage elements such that each word line is connected to adjacent blocks of non-volatile storage elements, a plurality of bit lines connected to... Agent:
20120275211 - Reconfigurable crossbar memory array: A two-dimensional array of switching devices comprises a plurality of crossbar tiles. Each crossbar tile has a plurality of row wire segments intersecting a plurality of column wire segments, and a plurality of switching devices each formed at an intersection of a row wire segment and a column wire segment.... Agent:
20120275212 - Self-body biasing sensing circuit for resistance-based memories: A resistance based memory sensing circuit has reference current transistors feeding a reference node and a read current transistor feeding a sense node, each transistor has a substrate body at a regular substrate voltage during a stand-by mode and biased during a sensing mode at a body bias voltage lower... Agent: Qualcomm Incorporated
20120275216 - Low noise memory array: A memory array compatible with dynamic random access memories (DRAM) and static random access memories (SRAM) is disclosed. The memory array includes a first sense amplifier (700) having a signal bit line (710) extending in a first direction and having a memory cell (714) suitable for a read operation. A... Agent:
20120275217 - Low noise memory array: A memory array compatible with dynamic random access memories (DRAM) and static random access memories (SRAM) is disclosed. The memory array includes a first sense amplifier (700) having a first bit line (754) extending in a first direction and a second bit line (752) extending in a second direction parallel... Agent:
20120275214 - Semiconductor device and driving method thereof: In a memory module including a memory cell array including memory cells arranged in matrix, each including a first transistor using an oxide semiconductor and a first capacitor; a reference cell including a p-channel third transistor, a second capacitor, and a second transistor using an oxide semiconductor; and a refresh... Agent: Semiconductor Energy Laboratory Co., Ltd.
20120275215 - Semiconductor device: There is provided a semiconductor device including a word line, a bit line, a power supply node, a memory element, and a capacitor. The memory element includes at least first and second regions that form a PN junction between the bit line and the power supply node, and a third... Agent: Elpida Memory, Inc.
20120275213 - Semiconductor memory device and method for driving the same: In a semiconductor memory device, one electrode of a capacitor is connected to a bit line, and the other electrode of the capacitor is connected to a drain of a cell transistor. A source of the cell transistor is connected to a source line. When a stack capacitor, for example,... Agent: Semiconductor Energy Laboratory Co., Ltd.
20120275219 - Shared transistor in a spin-torque transfer magnetic random access memory (sttmram) cell: A spin-torque transfer memory random access memory (STTMRAM) cell is disclosed comprising a selected magnetic tunnel junction (MTJ) identified to be programmed; a first transistor having a first port, a second port and a gate, the first port of the first transistor coupled to the selected MTJ; a first neighboring... Agent: Avalanche Technology, Inc.
20120275218 - Spin torque transfer cell structure utilizing field-induced antiferromagnetic or ferromagnetic coupling: A magnetic memory cell including a soft magnetic layer and a coupling layer, and methods of operating the memory cell are provided. The memory cell includes a stack with a free ferromagnetic layer and a pinned ferromagnetic layer, and a soft magnetic layer and a coupling layer may also be... Agent: Micron Technology, Inc.
20120275221 - Memory devices and methods of storing data on a memory device: Apparatus and methods are disclosed, such as those involving a flash memory device. One such apparatus includes a memory block including a plurality of memory cells; and a data randomizer configured to randomly or pseudo-randomly change original data to be stored in the memory block to changed data. The original... Agent: Micron Technology, Inc.
20120275220 - Three-dimensional multi-bit non-volatile memory and method for manufacturing the same: The present disclosure relates to the field of microelectronics manufacture and memories. A three-dimensional multi-bit non-volatile memory and a method for manufacturing the same are disclosed. The memory comprises a plurality of memory cells constituting a memory array. The memory array may comprise: a gate stack structure; periodically and alternately... Agent:
20120275222 - Nonvolatile memory apparatus and verification method thereof: A nonvolatile memory apparatus includes: a memory cell array including a plurality of unit memory cells; a page buffer unit configured to read data from a selected memory cell of the memory cell array and store the read data; a controller configured to generate a reference current generation signal, a... Agent: Hynix Semiconductor Inc.
20120275224 - Operating method of semiconductor device: An operating method of a semiconductor device that includes a plurality of memory cell blocks, comprising selecting one of the memory cell blocks in response to a program command, performing a pre-program operation and a pre-erase operation so that threshold voltages of memory cells included in the selected memory cell... Agent:
20120275223 - Semiconductor device and operating method thereof: There is disclosed an operating method of a semiconductor device including programming a memory cell by supplying a program voltage to a control gate of the memory cell and a detrap voltage to a well which is formed in a semiconductor substrate, and subsequently removing electrons trapped in a tunnel... Agent:
20120275226 - Nonvolatile semiconductor memory device capable of reducing power consumption: According to one embodiment, a nonvolatile semiconductor memory device includes an electrically rewritable nonvolatile memory, a grounding pad, a first power supply pad, a second power supply pad, a voltage reduction circuit, and a first pump circuit. A first power supply is supplied to the first power supply pad. A... Agent:
20120275227 - Photosensitive composition and compound for use in the photosenesitive composition: A programming method and memory structure for preventing punch-through in a short channel source-side select gate structure includes adjusting voltages on the selected and unselected bitlines, and the program, pass, and select gate voltages.... Agent: Micron Technology, Inc.
20120275225 - Variable resistance switch suitable for supplying high voltage to drive load: A circuit for supplying a high voltage to load is described. An example of such a circuit could be used in the peripheral circuitry of a non-volatile memory device for supplying a program voltage from a charge pump to a selected word line. The circuit includes a charge pump that... Agent:
20120275229 - Apparatus and method for external charge pump on flash memory module: A memory module is provided. The memory module includes die packages and a charge pump that is external the die packages. Each die package includes a flash memory device, and each of the flash memory devices includes bit lines and memory cells coupled to the bit lines. The charge pump... Agent: Spansion LLC
20120275228 - Internal wordline current leakage self-detection method, detection system and computer-readable storage medium for nor-type flash memory device: A wordline internal current leakage self-detection method, system and a computer-readable storage medium thereof employ the originally existed high voltage supply unit and the voltage detector connected to the wordline in the flash memory device, in which the high voltage supply unit applies the test signal to the selected wordline,... Agent: Eon Silicon Solution Inc.
20120275230 - Method of storing data on a flash memory device: Methods and apparatus are disclosed, such as those involving a flash memory device. One such method includes storing data on memory cells on a memory block including a plurality of word lines and a plurality of memory cells on the word lines. The word lines comprising one or more bottom... Agent: Micron Technology, Inc.
20120275231 - Method, apparatus, and manufacture for flash memory write algorithm for fast bits: A method, apparatus, and manufacture for a memory device is provided. The memory device includes memory cells that each store two bits, and a memory controller. During write operations, for each bit in each memory cell that is to be programmed, the memory controller determines whether both bits of the... Agent: Spansion LLC
20120275232 - Semiconductor device and erase methods thereof: An erase method of a semiconductor device includes performing an operation comprised of supplying an erase pulse to erase the memory cells of a memory block, performing an erase verify operation for detecting memory cells of the memory block having threshold voltages dropped to a target erase voltage, from among... Agent: Sk Hynix Inc.
20120275233 - Soft landing for desired program threshold voltage: Methods of programming memory cells are disclosed. In at least one embodiment, programming is accomplished by applying a first set of programming pulses to program to an initial threshold voltage, and applying a second set of programming pulses to program to a final threshold voltage.... Agent: Micron Technology, Inc.
20120275234 - Nonvolatile memory devices, memory systems and computing systems: A nonvolatile memory device configured to apply a wordline erase voltage to a plurality of wordlines connected to a plurality of memory cells, apply an erase voltage to a substrate where a memory cell string is formed while applying a specific voltage to at least one ground selection line connected... Agent:
20120275235 - Method and apparatus for temperature compensation for programming and erase distributions in a flash memory: A method and apparatus for a memory device is provided. The memory device includes a memory cell, a memory controller, and a temperature-sensing device that detects a temperature. The memory controller enables adjusting, based on the detected temperature, a parameter associated with a bit-altering operation to the memory cell that... Agent: Spansion LLC
20120275237 - Memory controller having a write-timing calibration mode: A memory controller outputs address bits and a first timing signal to a DRAM, each address bit being associated with an edge of the first timing signal and the first timing signal requiring a first propagation delay time to propagate to the DRAM. The memory controller further outputs write data... Agent:
20120275236 - Method and apparatus for power domain isolation during power down: An apparatus and method for isolating circuitry from one power domain from that of another power domain prior to performing a power down operation is disclosed. In one embodiment, circuitry in a first power domain is coupled to receive signals based on outputs from circuitry in a second power domain.... Agent:
20120275239 - Memory apparatus and refresh method therof: A memory apparatus includes a memory cell array comprising a plurality of memory cells connected with a plurality of bit lines and a plurality of word lines, a page buffer unit connected to the plurality of bit lines and latch data read from a memory cell selected from the plurality... Agent: Hynix Semiconductor Inc.
20120275238 - Memory circuit and control method thereof: A memory circuit according to one embodiment of the present invention includes a clock driver and an ODT timer. The clock driver is configured to provide a system clock signal based on a root clock signal when the memory circuit is in a read mode, and is configured to stop... Agent: Nanya Technology Corporation
20120275240 - Semiconductor memory device: A semiconductor memory device includes a random address generation unit configured to receive a multi-bit source address and generate a multi-bit random address and a signal mixing unit configured to mix the multi-bit random address with a data, wherein the random address generation unit has a plurality of transmission lines... Agent:
20120275241 - Semiconductor memory system and method for driving the same: A method for driving a semiconductor memory device includes controlling a plurality of erase voltages for a plurality of memory blocks, respectively, comparing the plurality of controlled erase voltages, and determining whether or not to enable the plurality of memory blocks for a subsequent write operation in response to a... Agent:
20120275242 - Vss-sensing amplifier: Some embodiments regard a circuit comprising a memory cell, a first data line, a second data line, a sensing circuit coupled to the first data line and the second data line, a node selectively coupled to at least three voltage sources via at least three respective switches, a fourth switch,... Agent: Taiwan Semiconductor Manufacturing Company, Ltd.
20120275244 - Semiconductor integrated circuit and semiconductor memory device having fuse circuit: A semiconductor integrated circuit includes: a fuse; a first driving unit configured to drive a sensing node in response to a first fuse sensing signal; a second driving unit configured to drive the sensing node in response to a second fuse sensing signal, wherein the second driving unit and the... Agent:
20120275243 - Semiconductor memory device: A semiconductor memory device includes: a first switch configured to couple a bit line to a first input/output line in response to an output selection signal including a pulse which is generated in response to a read command or write command; and a second switch configured to couple the first... Agent: Hynix Semiconductor Inc.
20120275245 - Semiconductor device and method of driving semiconductor device: A semiconductor device which is capable of high-speed writing with less power consumption and suitable for multi-leveled memory, and verifying operation. A memory cell included in the semiconductor device included a transistor formed using an oxide semiconductor and a transistor formed using a material other than an oxide semiconductor. A... Agent: Semiconductor Energy Laboratory Co., Ltd.
20120275246 - Multi-test apparatus and method for semiconductor chips: An apparatus and method is capable of reducing instantaneously consumed current by allowing write drivers and input buffers not to be simultaneously driven in a multi-test of semiconductor chips. A multi-test apparatus includes an input unit configured to receive data for testing, wherein the data for testing is inputted from... Agent:
20120275249 - Redundancy circuits and operating methods thereof: A memory circuit includes a group of memory arrays and at least one redundancy bit line. The group of memory arrays includes a first memory array coupled with a first input/output (IO) interface and a second memory array coupled with a second IO interface. The at least one redundancy bit... Agent: Taiwan Semiconductor Manufacturing Company, Ltd.
20120275248 - Semiconductor apparatus: A semiconductor apparatus includes a memory block configured to have a normal cell array and a redundancy cell array; a column address buffer configured to compare a plurality of input column addresses with a fail column address signal-stored in a fuse array, and generate a column enable signal or a... Agent: Hynix Semiconductor Inc.
20120275247 - Semiconductor memory device and method for repairing the same: A semiconductor memory device includes a latch address generation unit configured to latch row addresses to generate first and second latch addresses when at least one of memory cells coupled to sub word lines is faulty, wherein the first and second latch addresses select different main word lines, and a... Agent: Hynix Semiconductor Inc.
20120275253 - Differential sense amplifier without dedicated pass-gate transistors: A differential sense amplifier for sensing data stored in a plurality of memory cells of a memory cell array, including a first CMOS inverter having an output connected to a first bit line and an input connected to a second bit line complementary to the first bit line, and a... Agent: Soitec
20120275254 - Differential sense amplifier without dedicated precharge transistors: The invention relates to a differential sense amplifier for sensing data stored in a plurality of memory cells of a memory cell array, including a first CMOS inverter having an output connected to a first bit line and an input connected to a second bit line complementary to the first... Agent: Soitec
20120275252 - Differential sense amplifier without switch transistors: A differential sense amplifier for sensing data stored in a plurality of memory cells of a memory cell array, including a first CMOS inverter having an output connected to a first bit line (BL) and an input connected to a second bit line complementary to the first bit line and... Agent: Soitec
20120275255 - Semiconductor device and data processing system comprising semiconductor device: A semiconductor device comprises a sense amplifier circuit amplifying a signal transmitted through the bit line, first/second data lines transmitting the signal amplified by the sense amplifier circuit, a read amplifier circuit driven by a first voltage and amplifying the signal; first/second switch circuits controlling connection between the above components,... Agent: Elpida Memory Inc.
20120275251 - Semiconductor device, semiconductor memory device and operation method thereof: A semiconductor memory device includes a bit line sense amplification unit configured to sense/amplify data loaded on a bit line, and a driving control unit configured to supply a power line of the bit line sense amplification unit with an overdriving voltage in an overdriving period and supply an internal... Agent:
20120275250 - Semiconductor memory device having a data line sense amplifier: A memory device includes a data line sense amplifier configured to receive a sense amplifying power source voltage and a sense amplifying ground voltage through a sense amplifying power source line and a sense amplifying ground line, respectively, and sense-amplify data loaded on a pair of data lines, and a... Agent:
20120275256 - Semiconductor device: A device may include, but is not limited to, a bit line; a power line supplied with a power voltage; a sense amplifier circuit amplifying a voltage of the bit line by using the power voltage of the power line; and a control circuit configured to respond to an active... Agent: Elpida Memory, Inc.
20120275257 - Semiconductor device and operating method thereof: A semiconductor device includes a first bit line section coupled to a first cell string, a second bit line section coupled to a second cell string, a page buffer coupled to the first bit line section and a switching circuit formed between the first bit line section and the second... Agent: Hynix Semiconductor Inc.Previous industry: Electric power conversion systems
Next industry: Agitating
RSS FEED for 20130516:
Integrate FreshPatents.com into your RSS reader/aggregator or website to track weekly updates.
For more info, read this article.
Thank you for viewing Static information storage and retrieval patents on the FreshPatents.com website. These are patent applications which have been filed in the United States. There are a variety ways to browse Static information storage and retrieval patent applications on our website including browsing by date, agent, inventor, and industry. If you are interested in receiving occasional emails regarding Static information storage and retrieval patents we recommend signing up for free keyword monitoring by email.
FreshPatents.com Support - Terms & Conditions
Results in 1.25865 seconds