|Static information storage and retrieval patents - Monitor Patents|
USPTO Class 365 | Browse by Industry: Previous - Next | All
10/2012 | Recent | 15: May | Apr | Mar | Feb | Jan | 14: Dec | Nov | Oct | Sep | Aug | Jul | Jun | May | Apr | Mar | Feb | Jan | 13: Dec | Nov | Oct | Sep | Aug | Jul | Jun | May | Apr | Mar | Feb | Jan | 12: Dec | Nov | Oct | Sep | Aug | July | June | May | April | Mar | Feb | Jan | 11: Dec | Nov | Oct | Sep | Aug | Jul | Jun | May | Apr | Mar | Feb | Jan | 10: Dec | Nov | Oct | Sep | Aug | Jul | Jun | May | Apr | Mar | Feb | Jan | | 09: Dec | Nov | Oct | Sep | Aug | Jl | Jn | May | Apr | Mar | Fb | Jn | | 2008 | 2007 |
Static information storage and retrieval October categorized by USPTO classification 10/12Below are recently published patent applications awaiting approval from the USPTO. Recent week's RSS XML file available below.
Listing for abstract view: USPTO application #, Title, Abstract excerpt,Patent Agent. Listing format for list view: USPTO National Class full category number, title of the patent application. 10/25/2012 > 47 patent applications in 28 patent subcategories. categorized by USPTO classification
20120268977 - Semiconductor memory device and programming method thereof: A semiconductor memory device includes a memory cell block configured to include a plurality of main cells and a plurality of CAM cells, a plurality of page buffers configured to store data to be programmed into the memory cell block, and a Y decoder configured to transfer CAM data to... Agent: Hynix Semiconductor Inc.
20120268978 - Semiconductor memory device in which capacitance between bit lines is reduced, and method of manufacturing the same: According to one embodiment, a semiconductor memory device includes a plurality of memory cells arranged in a matrix, a plurality of word lines for selecting a plurality of memory cells, and a plurality of bit lines for selecting a plurality of memory cells. Of the plurality of bit lines, first... Agent:
20120268979 - Semiconductor device: A nonvolatile memory is provided. A semiconductor device (a nonvolatile memory) has a circuit configuration similar to that of a general SRAM. By providing a transistor whose off-state current is small between a stored data holding portion and a power supply line of the SRAM, leakage of electric charge from... Agent: Semiconductor Energy Laboratory Co., Ltd.
20120268980 - Nonvolatile variable resistive element and nonvolatile semiconductor memory device: A large-capacity and inexpensive nonvolatile semiconductor memory device that prevents a leak current and is operated at high speed is implemented with a nonvolatile variable resistive element. A memory cell array includes the nonvolatile variable resistive elements each including a variable resistor composed of a metal oxide film to cause... Agent:
20120268981 - Semiconductor device and its manufacturing method: In a semiconductor device including a memory cell array formed of memory cells using a storage element by a variable resistor and a select transistor, a buffer cell is arranged between a sense amplifier and the memory cell array and between a word driver and the memory cell array. The... Agent: Renesas Electronics Corporation
20120268982 - Methods and apparatus of stacking drams: Large capacity memory systems are constructed using stacked memory integrated circuits or chips. The stacked memory chips are constructed in such a way that eliminates problems such as signal integrity while still meeting current and future memory standards.... Agent: Google Inc.
20120268984 - Adaptive wordline programming bias of a phase change memory: The leakage current and power consumption of phase change memories may be reduced using adaptive word line biasing. Depending on the particular voltage applied to the bitline of a programmed cell, the word lines of unselected cells may vary correspondingly. In some embodiments, the word line voltage may be caused... Agent:
20120268983 - Random-access memory with dynamically adjustable endurance and retention: A memory device is provided. The memory device comprises an array of memory cells, each including a volume of material that can stably exhibit at least two different physical states that are each associated with a different data value, word lines that each interconnects a row of memory cells within... Agent:
20120268985 - Resonance nanoelectromechanical systems: Systems and methods for operating a nanometer-scale cantilever beam with a gate electrode. An example system includes a drive circuit coupled to the gate electrode where a drive signal from the circuit may cause the beam to oscillate at or near the beam's resonance frequency. The drive signal includes an... Agent: International Business Machines Corporation
20120268986 - Magnetic memory element and non-volatile storage device: The present invention provides a magnetic memory element that has a spin valve structure formed using a free layer, a non-magnetic layer, and a pinned layer. The free layer has a three-layer structure having a first magnetic layer, an intermediate layer, and a second magnetic layer arranged in this order... Agent: Fuji Electric Co., Ltd.
20120268988 - Nonvolatile memory device including memory cell array with upper and lower word line groups: A nonvolatile memory device includes a memory cell array having multiple memory blocks. Each memory block includes memory cells arranged at intersections of multiple word lines and multiple bit lines. At least one word line of the multiple word lines is included in an upper word line group and at... Agent: Samsung Electronics Co., Ltd.
20120268989 - Novel high speed high density nand-based 2t-nor flash memory design: A two transistor NOR flash memory cell has symmetrical source and drain structure manufactured by a NAND-based manufacturing process. The flash cell comprises a storage transistor made of a double-poly NMOS floating gate transistor and an access transistor made of a double-poly NMOS floating gate transistor, a poly1 NMOS transistor... Agent:
20120268990 - Selective re-programming of analog memory cells: A method for data storage includes defining, in a memory that includes multiple analog memory cells, an erased state, a set of non-erased programming states and a partial subset of the non-erased programming states. Data is initially stored in a first group of the analog memory cells by programming each... Agent:
20120268991 - Data storage device and block selection method for a flash memory: The invention provides a block selection method for a flash memory. First, a flash memory is divided into a plurality of great block groups. Each of the great block groups is then divided into a plurality of block groups. Scores corresponding to the blocks of the flash memory are then... Agent: Silicon Motion, Inc.
20120268994 - Memory system: According to one embodiment, a memory system includes a nonvolatile semiconductor memory device, a voltage generation unit and a control unit. The nonvolatile semiconductor memory device includes a memory cell array having a plurality of blocks each including a plurality of memory cells, and a voltage generation unit configured to... Agent:
20120268995 - Non-volatile semiconductor memory device and electronic apparatus: A memory cell array including non-volatile memory cells is divided into a first block including a non-volatile memory cell for accumulating a degradation over time and a second block including a non-volatile memory cell for storing data. A word line select circuit and a bit line select circuit select a... Agent: Panasonic Corporation
20120268992 - Semiconductor memory device: A semiconductor memory device includes a memory cell array configured to include a plurality of memory blocks, a voltage generator configured to output operating voltages for data input and output to global lines, and a row decoder configured to transfer the operating voltages to local lines of a memory block,... Agent: Sk Hynix Inc.
20120268993 - Semiconductor memory device: A semiconductor memory device includes first and second memory planes that each include a plurality of memory blocks, a first page buffer group coupled to the memory blocks of the first memory plane through first bit lines and configured to perform a read operation and a program operation, a second... Agent:
20120268996 - Semiconductor memory device: A semiconductor memory device includes a memory cell array including memory block groups each coupled to bit lines, a page buffer group coupled to first bit lines of a first memory block group and configured to control voltages of the first bit lines of the first memory block group depending... Agent:
20120268998 - Flash memory device and method for handling power failure thereof: A flash memory device. In one embodiment, the flash memory device comprises a flash memory, a diode, a controller, and a capacitor. The flash memory has a voltage source pin. The diode is coupled between a voltage source and the voltage source pin of the flash memory. The controller is... Agent: Silicon Motion, Inc.
20120268997 - Nonvolatile semiconductor device: A nonvolatile memory device includes a plurality of global word lines, a voltage pump configured to generate a plurality of voltages, a control unit configured to divide the plurality of global word lines into a first group and a second group in response to an input row address and generate... Agent:
20120268999 - Dynamic programming for flash memory: A method is for operating a memory having a group of non-volatile memory cells. A first programming pulse is applied to a subset of the group of non-volatile memory cells. The subset needs additional programming. A portion of the subset still needing additional programming is identified. A ratio of the... Agent:
20120268987 - System and method for detecting disturbed memory cells of a semiconductor memory device: A method of detecting a disturb condition of a memory cell includes application of multiple sets of conditions to the memory cell and determining whether the memory cell behaves as a programmed memory cell in response to the sets of conditions. A disturbed memory cell can be detected if the... Agent: Macronix International Co., Ltd.
20120269003 - Data decision method and memory: A data decision method including checking whether threshold voltages of a plurality of memory cells are greater than a first verification voltage, checking whether the threshold voltages of the plurality of memory cells are greater than a second verification voltage, wherein the second verification voltage is greater than the first... Agent:
20120269004 - Multiple level program verify in a memory device: A series of programming pulses are applied to a memory cell to be programmed. A program verify pulse, at an initial program verify voltage, is applied to the memory cell after each programming pulse. The initial program verify voltage is a verify voltage that has been increased by a quick... Agent: Micron Technology, Inc.
20120269000 - Non-volatile memory device and program method thereof: A method for programming a non-volatile memory device including a plurality of memory cells includes verifying whether the memory cells are programmed or not by applying a program verification bias voltage, which is calculated and stored during an initialization operation preformed before the programming of the memory cells, after a... Agent:
20120269001 - Non-volatile semiconductor memory device: A non-volatile semiconductor memory device according to one embodiment of the present invention includes a memory cell array and a control unit. The control unit is configured to control a repeat of an erase operation, an erase verify operation, and a step-up operation. The control unit is configured to perform... Agent: Kabushiki Kaisha Toshiba
20120269002 - Programming method for nonvolatile memory device: A method of programming memory cells (transistors) of a nonvolatile memory device from a first set of (previous) logic states to a second set of (final) logic states. The method includes applying program voltages to selected memory transistors; and applying a pre-verification voltage and a target verification voltage for verifying... Agent:
20120269008 - Data input device for semiconductor memory device: A data input device for use in a memory device to avoid false data being written due to a postamble ringing phenomenon in a write operation is provided. The data input device comprises a buffer, a combinational logic circuit and a flip-flop unit. The buffer receives the data and outputs... Agent: Elite Semiconductor Memory Technology, Inc.
20120269006 - Semiconductor device: A semiconductor device is capable of reducing the coupling capacitance between adjacent bit lines by forming an air-gap at an opposite side of a one side contact when forming a buried bit line or increasing a thickness of an insulating layer, thereby improving characteristics of the semiconductor devices. The semiconductor... Agent: Hynix Semiconductor Inc.
20120269007 - Semiconductor memory device and method of reading out the same: A semiconductor memory device includes a memory cell array configured to include memory cells, peripheral circuits configured to read out data stored in a selected memory cell in a read operation, and a controller configured to control the peripheral circuits so that the peripheral circuits sense a voltage level of... Agent: Hynix Semiconductor Inc.
20120269005 - Semiconductor memory device and test method thereof: A semiconductor memory device includes a plurality of first pads and a plurality of memory unit blocks. The plurality of first pads are configured to input/output data in a test mode. The plurality of memory unit blocks each include a plurality of second pads configured to input/output data in a... Agent:
20120269009 - Memory array with two-phase bit line precharge: An integrated circuit includes an array of memory cells with a plurality of columns and rows. A plurality of data lines is coupled to the columns in the array and a plurality of word lines is coupled to the rows in the array. Clamp transistors are coupled to respective data... Agent: Macronix International Co., Ltd.
20120269010 - Memory device and method for operating the same: A memory includes at least one first flag cell configured to store first flag data, at least one second flag cell configured to store second flag data, at least one first sensing node having a voltage level determined by the first flag data of the first flag cell, at least... Agent:
20120269011 - Voltage switching in a memory device: Voltage switches, memory devices, memory systems, and methods for switching are disclosed. One such voltage switch uses a pair of switch circuits coupled in series, each switch circuit being driven by a level shift circuit. Each switch circuit uses a group of series coupled transistors with a parallel control transistor... Agent: Micron Technology, Inc.
20120269012 - Semiconductor integrated circuit and method for driving the same: A semiconductor integrated circuit includes a first signal generator configured to generate a third active signal that is selectively enabled in a first duration in response to a first active signal enabled during the first duration and a second active signal enabled during at least one second duration within the... Agent:
20120269013 - Signal processing circuit: A signal processing circuit including a nonvolatile storage circuit with a novel structure. The signal processing circuit includes a circuit that is supplied with a power supply voltage and has a first node to which a first high power supply potential is applied, and a nonvolatile storage circuit for holding... Agent: Semiconductor Energy Laboratory Co., Ltd.
20120269014 - Delay control circuit and semiconductor memory device including the same: A delay control circuit includes a delay locked loop configured to delay an external clock by a first delay amount and generate an internal clock, a first delay unit configured to delay an input signal by a first delay amount, a first replica delay unit having a replica delay amount... Agent:
20120269015 - Command paths, apparatuses, memories, and methods for providing internal commands to a data path: Command paths, apparatuses, memories, and methods for providing an internal command to a data path are disclosed. In an example method, a command is received and propagated through a command path to provide an internal command. Further included in the method is determining a difference between a latency value and... Agent: Micron Technology, Inc.
20120269017 - Delay circuit and latency control circuit of memory, and signal delay method thereof: A delay circuit includes a delay unit configured to generate a delayed transfer signal by delaying a transfer signal corresponding to a first signal or a second signal, a distinguishment signal generation unit configured to generate a distinguishment signal which represents to what signal the transfer signal correspond between the... Agent:
20120269016 - Latency control circuit, latency control method thereof, and semiconductor memory device including the same: A latency control circuit of a semiconductor device includes a phase detection unit configured to generate phase information regarding a phase difference between an external clock and an internal clock, a delay amount deciding unit configured to decide a latency delay amount based on path information of an input signal,... Agent:
20120269018 - Memory system having memory and memory controller and operation method thereof: An operation method of a memory system including a memory and a memory controller includes transmitting defective-cell address information to the memory controller from the memory at an initial operation of the memory, wherein the defective-cell address information includes an address of a defective cell of the memory, and accessing,... Agent:
20120269019 - Semiconductor device having control bitline to prevent floating body effect: A vertical semiconductor device is provided. The semiconductor device includes a cell array including a control bit line connected to cells and electrically isolated from a bit line, and a floating body control circuit for applying a floating control voltage to the control bit line in a predetermined period.... Agent: Hynix Semiconductor Inc.
20120269021 - Memory device using a variable resistive element: A memory device includes a memory cell array including a plurality of memory blocks, each memory block including a plurality of memory cells, a plurality of word lines coupled to rows of the plurality of memory cells, a plurality of bit lines coupled to columns of the plurality of memory... Agent:
20120269020 - Non-volatile memory device and method for operating the same: A method for operating a non-volatile memory device includes selecting a word line of a plurality of word lines in response to a program command and an received address, determining whether the selected word line is a word line set among the word lines, performing an erase operation on a... Agent:
20120269022 - Internal power source voltage generating circuit of semiconductor memory and method for generating internal power source voltage: An internal power source voltage generating circuit of a semiconductor memory and a corresponding method shorten an access delay upon transition of a data reading operation in an address period shorter than a prescribed minimum period to an operation in the prescribed minimum period. While a boosted voltage of an... Agent: Lapis Semiconductor Co., Ltd.
20120269023 - System with controller and memory: According to the system of the present invention, data (DQ) signals are outputted/received between a controller 100 and a memory 200 based on a data strobe signal sent out from the controller 100. The data strobe signal is independently and completely separated from a clock signal. The data strobe signal... Agent: Elpida Memory, Inc.10/18/2012 > 36 patent applications in 23 patent subcategories. categorized by USPTO classification
20120262970 - Selective activation of programming schemes in analog memory cell arrays: A method for data storage includes defining a first programming scheme that programs a group of analog memory cells while reducing interference caused by at least one memory cell that neighbors the group, and a second programming scheme that programs the group of the analog memory cells and does not... Agent:
20120262971 - Selective activation of programming schemes in analog memory cell arrays: A method for data storage includes defining a first programming scheme that programs a group of analog memory cells while reducing interference caused by at least one memory cell that neighbors the group, and a second programming scheme that programs the group of the analog memory cells and does not... Agent:
20120262972 - Content addressable memory: The present invention provides a content addressable memory capable of higher frequency operation than conventional. When a search enable signal supplied from a search control circuit is asserted, each of search line drivers transfers search data to each CAM cell of a CAM memory array via a search line pair.... Agent: Renesas Electronics Corporation
20120262973 - Arrays of nonvolatile memory cells and methods of forming arrays of nonvolatile memory cells: An array of nonvolatile memory cells includes a plurality of vertically stacked tiers of nonvolatile memory cells. The tiers individually include a first plurality of horizontally oriented first electrode lines and a second plurality of horizontally oriented second electrode lines crossing relative to the first electrode lines. Individual of the... Agent:
20120262974 - Memory module and memory system: In a memory module including a plurality of DRAM chips which transmit/receive a system data signal with a predetermined data width and at a transfer rate and which transmit/receive an internal data signal having a larger data width and a lower transfer rate as compared with the system data signal,... Agent: Elpida Memory, Inc.
20120262975 - Semiconductor memory device including plurality of memory chips: A semiconductor memory device includes a plurality of memory chips each including a chip identification (ID) generation circuit. The chip ID generation circuits of the respective memory chips are operatively connected together in a cascade configuration, and the chip ID generation circuits are activated in response to application of a... Agent:
20120262977 - Memory modules and memory devices having memory device stacks, and method of forming same: A memory module, system and method of forming the same includes a memory module including a plurality of memory devices having a first portion of memory devices cooperatively forming a first rank of memory devices and a second portion of memory devices cooperatively forming a second rank of memory devices.... Agent: Micron Technology, Inc.
20120262976 - Semiconductor storage device: When plural diffusion layers are shared in order to save an area of a semiconductor integrated circuit, parasitic capacities of wirings coupled to those diffusion layers are changed. Nonetheless, a semiconductor layout balancing capacitive loads of paired wirings coupled to the diffusion layers with each other is provided. The diffusion... Agent: Renesas Electronics Corporation
20120262979 - Memory device: A memory device includes a memory cell storing data as stored data, an output signal line, and a wiring to which a voltage is applied. The memory cell includes a comparison circuit performing a comparison operation between the stored data and search data and taking a conduction state or a... Agent: Semiconductor Energy Laboratory Co., Ltd.
20120262978 - Semiconductor integrated circuit device: Transistors formed in one identical diffusion layer and performing complementary operations are generally arranged symmetrically with respect to the diffusion layer. A semiconductor integrated device using a layout capable of partially avoiding restriction on the design of the semiconductor integrated circuit device and reducing the size and economizing the manufacturing... Agent: Renesas Electronics Corporation
20120262981 - Data retention structure for non-volatile memory: A data retention structure in a memory element that stores data as a plurality of conductivity profiles is disclosed. The memory element can be used in a variety of electrical systems and includes a conductive oxide layer, an ion impeding layer, and an electrolytic tunnel barrier layer. A write voltage... Agent: Unity Semiconductor Corporation
20120262980 - Random access memory with cmos-compatible nonvolatile storage element and parallel storage capacitor: Systems, methods, and memory device with row lines and column lines arranged in a matrix configuration with a memory cell coupled to one of the column lines and one of the row lines. The memory cell includes a storage capacitor with a first plate coupled to a storage node, a... Agent: S. Aqua Semiconductor, LLC
20120262982 - Memory device and driving method of the memory device: A memory device which can reduce power consumption and a driving method thereof are disclosed. In a memory element including an inverter and the like, a capacitor for holding data and a capacitor switching element for controlling store and release of charge in the capacitor are provided. The capacitor switching... Agent: Semiconductor Energy Laboratory Co., Ltd.
20120262983 - Semiconductor device and driving method thereof: The circuit includes a first wiring for supplying a power supply potential to a signal processing circuit, a transistor for controlling electrical connection between the first wiring and a second wiring for supplying the a power supply potential, and a transistor for determining whether or not the first wiring is... Agent: Semiconductor Energy Laboratory Co., Ltd.
20120262984 - Reducing temporal changes in phase change memories: A phase change memory in the reset state may be heated to reduce or eliminate electrical drift.... Agent:
20120262985 - Mulit-bit cell: A method for forming a device is disclosed. The method includes providing a substrate prepared with a primary gate and forming a charge storage layer on the substrate over the primary gate. A secondary gate electrode layer is formed on the substrate over the charge storage layer. The charge storage... Agent: Globalfoundries Singapore Pte. Ltd.
20120262986 - Source side asymmetrical precharge programming scheme: A method for programming NAND flash cells to minimize program stress while allowing for random page programming operations. The method includes asymmetrically precharging a NAND string from a positively biased source line while the bitline is decoupled from the NAND string, followed by the application of a programming voltage to... Agent: Mosaid Technologies Incorporated
20120262988 - Method and apparatus for leakage suppression in flash memory: Techniques are described herein for detecting and recovering over-erased memory cells in a flash memory device. In one embodiment, a flash memory device is described including a memory array including a plurality of blocks of memory cells. The device also includes a controller to perform a leakage-suppression process. The leakage-suppression... Agent: Macronix International Co., Ltd.
20120262987 - Method and apparatus for leakage suppression in flash memory in response to external commands: Techniques are described herein for detecting and recovering over-erased memory cells in a flash memory device. In one embodiment, a flash memory device includes a memory array including a plurality of blocks of memory cells. The device also includes a command interface to receive a command from a source external... Agent: Macronix International Co., Ltd.
20120262989 - Nonvolatile semiconductor memory device including plural memory cells and a dummy cell coupled to an end of a memory cell: A nonvolatile semiconductor memory device having a plurality of electrically rewritable nonvolatile memory cells connected in series together includes a select gate transistor connected in series to the serial combination of memory cells. A certain one of the memory cells which is located adjacent to the select gets transistor is... Agent: Kabushiki Kaisha Toshiba
20120262990 - Memory device: A memory device comprises a main memory array having a plurality of bit lines, and a select array having a plurality of transistors coupled to the bit lines. Wherein one of the plurality of transistors is electrically programmed to a threshold voltage greater than a threshold voltage of another one... Agent: Macronix International Co., Ltd.
20120262991 - Methods and devices for determining sensing voltages: The present disclosure includes methods and devices for determining sensing voltages. One such method includes comparing data associated with a number of template distributions to data associated with a first threshold voltage distribution and a second threshold voltage distribution associated with a number of memory cells programmed to particular adjacent... Agent: Micron Technology, Inc.
20120262992 - Semiconductor device including multi-chip: In order to implement a memory having a large storage capacity and a reduced data retention current, a non-volatile memory, an SRAM, a DRAM, and a control circuit are modularized into one package. The control circuit conducts assignment of addresses to the SRAM and DRAM, and stores data that must... Agent: Renesas Technology Corp.
20120262993 - Sensing scheme in a memory device: Methods of operating memory devices, generating reference currents in memory devices, and sensing data states of memory cells in a memory device are disclosed. One such method includes generating reference currents utilized in sense amplifier circuitry to manage leakage currents while performing a sense operation within a memory device. Another... Agent: Micron Technology, Inc.
20120262994 - System and method for memory array decoding: A memory system including a memory array, and a read write/module. The memory includes a plurality of bit lines, a plurality of word lines, and a plurality of memory cells, in which each memory cell is formed at a corresponding intersection of a bit line and a word line in... Agent:
20120262996 - Device: Provided is a device, including: a first terminal which receives an external clock signal; a clock generation circuit connected to the first terminal to generate an internal clock signal based on the external clock signal; word lines and bit lines; amplifier circuits connected to the bit lines, respectively; and a... Agent: Elpida Memory, Inc.
20120262995 - Semiconductor element, memory circuit, integrated circuit, and driving method of the integrated circuit: A novel semiconductor element contributing to an increase in circuit scale is provided. In the semiconductor element, two different electrical switches are formed using a single oxide semiconductor layer. For example, in the semiconductor element, formation of a channel (a current path) in the vicinity of a bottom surface (a... Agent: Semiconductor Energy Laboratory Co., Ltd.
20120262998 - Clock synchronization in a memory system: Synchronization is provided in a memory system. During memory write operations a timing reference signal is transmitted with control signals to a memory device, and a calibration signal is received from the memory device. An internal clock signal is adjusted based on the calibration signal, and a data signal is... Agent: Rambus Inc.
20120262997 - Method for searching optimum value of memory: A method for searching an optimum value of a memory includes the following steps. A first and a second phase delay values of the memory are sequentially set to a plurality of first values and a plurality of second values respectively amounts of combinations of the first values combining with... Agent: Himax Technologies Limited
20120263000 - Programmable control block for dual port sram application: A dual-port static random access memory (SRAM) includes a multitude of programmable delay elements disposed along the paths of a number signals used to carry out read, write or read-then-write operations. At least one of the programmable delay elements controls the timing margin between a pair of clock signals that... Agent: Altera Corporation
20120262999 - Semiconductor memory device and operating method thereof: A semiconductor memory device includes a system clock input block configured to be inputted with a system clock, a data clock input block configured to be inputted with a data clock, a first phase detection block configured to compare a phase of the system clock, generate a first phase detection... Agent:
20120263001 - Systems, memories, and methods for refreshing memory arrays: Memories, systems, and methods for refreshing are provided, such as a memory with an array of memory cells divided into sections. Memories include replacement elements having a digit line, and detecting circuitry coupled to a digit line of at least one section of the memory cell array and coupled to... Agent: Micron Technology, Inc.
20120263002 - Test method for screening local bit-line defects in a memory array: A method of detecting manufacturing defects at a memory array may include utilizing test circuitry to provide a selected voltage as drain bias on a bit-line of the memory array where the memory array is configured to employ a first voltage as the drain bias for a read operation and... Agent: Macronix International Co., Ltd.
20120263003 - Device performing refresh operations of memory areas: Disclosed herein is a device that includes a plurality of memory circuits and a refresh control circuit configured to generate a plurality of refresh initiation signals such that one of the refresh initiation signals takes an active level. Each of the memory circuits comprises a memory cell array including a... Agent: Elpida Memory, Inc.
20120263004 - Semiconductor device with refresh control circuit: In a semiconductor device including a row-based control circuit applied with a current reduction circuit having a standby state and an active state, a refresh control circuit generates a refresh request signal every predetermined time interval on a self-refresh mode and time-sequentially generates an internal active signal at N times... Agent: Elpida Memory Inc.
20120263005 - Memory apparatus and system with shared wordline decoder: A memory device includes wordline decoder circuits that share components between adjacent memory blocks. The wordline decoder circuits include multiple levels, where at least one level is split, driving half of the wordlines in one adjacent memory block and driving half of the wordlines in another adjacent memory block. Memory... Agent:10/11/2012 > 37 patent applications in 24 patent subcategories. categorized by USPTO classification
20120257434 - Configurable bandwidth memory devices and methods: Memory devices and methods are described, such as those that include a stack of memory dies and an attached logic die. Method and devices described provide for configuring bandwidth for selected portions of a stack of memory dies. Additional devices, systems, and methods are disclosed.... Agent:
20120257433 - Memory system with data line switching scheme: A storage system includes a three-dimensional memory array that has multiple layers of non-volatile storage elements grouped into blocks. Each block includes a subset of first selection circuits for selectively coupling a subset of array lines (e.g. bit lines) of a first type to respective local data lines. Each block... Agent:
20120257435 - Non-salicide polysilicon fuse: The embodiments of methods and structures disclosed herein provide mechanisms of forming and programming a non-salicided polysilicon fuse. The non-salicided polysilicon fuse and a programming transistor form a one-time programmable (OTP) memory cell, which can be programmed with a low programming voltage.... Agent: Taiwan Semiconductor Manufacturing Company, Ltd.
20120257438 - Contemporaneous margin verification and memory access for memory cells in cross point memory arrays: Circuitry for restoring data values in re-writable non-volatile memory is disclosed. An integrated circuit includes a memory access circuit and a sensing circuit configured to sense a data signal during a read operation to at least one two-terminal non-volatile cross-point memory array. Each memory array includes a plurality of two-terminal... Agent: Unity Semiconductor Corporation
20120257437 - Semiconductor device: A semiconductor device includes first and second interconnects, a variable resistance element that may assume a first resistance value or a second resistance value in response to the current flowing therein, and second transistors connected between the first and second interconnects in series with each other on both sides of... Agent: Elpida Memory, Inc.
20120257436 - Semiconductor intergrated circuit and operating method thereof: A semiconductor integrated circuit includes a variable resistive element, a current supply unit and a control signal generating unit. The resistance of the variable resistive element is changed depending on current flowing therethrough. The current supply unit controls the current in response to a control signal. The control signal generating... Agent: Hynix Semiconductor Inc.
20120257439 - Memory device and semiconductor device using the same: A memory device whose speed at the time of operation such as writing or reading is high and whose number of semiconductor elements per memory cell is small is provided. The memory device includes a control unit, an arithmetic unit, and a buffer memory device. The buffer memory device stores... Agent: Semiconductor Energy Laboratory Co., Ltd.
20120257440 - Memory element and signal processing circuit: An object is to provide a memory device for which a complex manufacturing process is not necessary and whose power consumption can be suppressed, and a signal processing circuit including the memory device. In a memory element including a phase-inversion element such as an inverter or a clocked inverter, a... Agent: Semiconductor Energy Laboratory Co., Ltd.
20120257441 - Memory bit redundant vias: An integrated circuit containing a memory array with memory bits and a differential sense amplifier for reading the logic state of the memory bits. The integrated circuit also contains redundant vias which are in the via path that couples a bitline to Vss. Moreover, an integrated circuit containing a FLASH... Agent: Texas Instruments Incorporated
20120257443 - Semiconductor integrated circuit device with reduced leakage current: The gate tunnel leakage current is increased in the up-to-date process, so that it is necessary to reduce the gate tunnel leakage current in the LSI which is driven by a battery for use in a cellular phone and which needs to be in a standby mode at a low... Agent: Renesas Electronics Corporation
20120257442 - Semiconductor memory device: A semiconductor memory device having a read word line, a write word line and a sub-word driver operable to select the read word line using a main word signal and an inverse read block signal. The sub-word line selects the write word line using the main word signal and an... Agent: Nec Corporation
20120257447 - Magnetic tunnel junction with compensation element: A magnetic tunnel junction having a compsensation element is disclosed. The magnetic tunnel junction includes a reference element, and a compensation element having an opposite magnetization moment to a magnetization moment of the reference element. A free magnetic layer is between the reference element and the compensation element, and an... Agent: Seagate Technology LLC
20120257445 - Nonvolatile memory apparatus having magnetoresistive memory elements and method for driving the same: A semiconductor memory apparatus includes a source line, a first bit line disposed over the source line, a second bit line disposed under the source line, a first memory cell between the source line and the first bit line, and a second memory cell between the source line and the... Agent: Hynix Semiconductor Inc.
20120257446 - Unipolar spin-transfer switching memory unit: A memory unit includes a magnetic tunnel junction data cell electrically coupled to a bit line and a word line. The magnetic tunnel junction data cell is configured to switch between a high resistance state and a low resistance state by passing a unipolar voltage across the magnetic tunnel junction... Agent: Seagate Technology LLC
20120257444 - Write driver circuit for mram, mram and layout structure thereof: A write driver circuit for a magnetic random access memory includes a memory cell array including a plurality of magnetic memory cells in which a pair of magnetic memory cells adjacent to each other in a direction of a bit line share a source line, and each magnetic memory cell... Agent: Hynix Semiconductor Inc.
20120257449 - High density magnetic random access memory: A magnetic memory device that comprises a substrate, a memory cell including a magnetic tunnel junction which comprises a free ferromagnetic layer having a reversible magnetization direction directed perpendicular to the substrate, a pinned ferromagnetic layer having a fixed magnetization direction directed perpendicular to the substrate, and an insulating tunnel... Agent:
20120257448 - Multi-cell per memory-bit circuit and method: A write circuit is adapted to provide a same logical bit to each of a multitude of memory cells for storage. Each of the multitude of memory cells stores either the bit or a complement of the bit in response to the write circuit. A read circuit is adapted to... Agent: Grandis, Inc.
20120257451 - Non-volatile memory with both single and multiple level cells: Memory arrays and methods of operating such memory arrays are described as having a memory cell operated as a single level cell interposed between and coupled to a select gate and a memory cell operated as a multiple level memory cell. In some embodiments, a memory array is described as... Agent: Micron Technology, Inc.
20120257452 - Nonvolatile memory device and method of driving the same: A nonvolatile memory device includes a plurality of memory blocks, and a pass transistor array transmitting a plurality of drive signals to a selected memory block among the plurality of memory blocks in response to a block select signal. The pass transistor array includes high voltage transistors including one common... Agent: Samsung Electronics Co., Ltd.
20120257454 - Flash storage device with data integrity protection: A flash storage device includes a power hold circuit including a double layer capacitor. A power source supplies power to the flash storage device and charges the double layer capacitor. The double layer capacitor supplies power for maintaining integrity of data during a data transfer occurring in the flash storage... Agent: Stec, Inc.
20120257453 - Nonvolatile semiconductor memory device: A nonvolatile semiconductor memory device according to one embodiment of the present invention includes: a memory cell array and a control circuit. The control circuit executes a first reading operation and a second reading operation. The first reading operation is an operation of reading a threshold voltage set in the... Agent: Kabushiki Kaisha Toshiba
20120257450 - Methods and devices for memory reads with precharged data lines: Methods and devices for memory reads involving precharging adjacent data lines to a particular voltage for a read operation. During the operation, a data line associated with a selected memory cell is selectively discharged from the particular voltage depending upon the data value of the selected memory cell while the... Agent: Micron Technology, Inc.
20120257455 - Nonvolatile memory devices and methods of operating nonvolatile memory devices: Methods of operating nonvolatile memory devices including a plurality of cell strings each having at least one ground selection transistor, a plurality of memory cells, and at least one string selection transistor, the operating methods including receiving a command and an address, determining a voltage applying time in response to... Agent: Samsung Electronics Co., Ltd.
20120257456 - Semiconductor memory device and data write method thereof: A semiconductor memory device includes a control circuit. The control circuit executes control to perform a verify operation with respect to only a lowest threshold voltage level of a memory cell at a time of a data write operation, and to skip the verify operation with respect to the other... Agent:
20120257457 - Method and apparatus for pre-charging data lines in a memory cell array: Memories, pre-charge circuits, and methods for pre-charging memory are described. One such method includes providing a voltage to a data line and adjusting the voltage provided to the data line based at least in part on a voltage difference between a target voltage and a voltage of the data line... Agent: Micron Technology, Inc.
20120257458 - Non-volatile semiconductor device, and method of operating the same: A non-volatile semiconductor device and a method for operating the same are disclosed, where the non-volatile semiconductor device includes a gate dielectric layer, a n-type floating gate, a coupling gate, a first n-type source/drain, a second n-type source/drain, a first contact plug and a second contact plug. The gate dielectric... Agent:
20120257459 - Memory buffer for buffer-on-board applications: The present disclosure involves an apparatus. The apparatus includes a decoder that receives an input command signal as its input and generates a first output command signal as its output. The apparatus includes a register component that receives the input command signal as its input and generates a second output... Agent: Dell Products L.p.
20120257461 - Method of testing a semiconductor memory device: A method of testing a semiconductor memory device includes writing first data to a memory cell array in the semiconductor memory device, loading second data from the memory cell array onto a plurality of data pads of the semiconductor memory device, rewriting the second data to the memory cell array,... Agent:
20120257462 - Repair method and integrated circuit using the same: An integrated circuit includes: a memory controller configured to determine whether a memory cell included in a semiconductor memory device is defective or not and extract a fail address having positional information of the defective memory cell, in a test mode; and a fail address storage unit configured to store... Agent: Hynix Semiconductor Inc.
20120257463 - Driver circuit: A driver circuit includes pull-up and pull-down drivers driven by separate pre-drivers operating between different voltage rails. Data signals driving the pull-up driver and the pull-down driver are synchronized, and the pull-up driver and the pull-down driver are coupled together to produce an output signal having a voltage swing based... Agent:
20120257464 - Semiconductor memory and system: A semiconductor memory includes a real memory cull; a sense amplifier configured to amplify data read from the real memory cell in response to activation of a sense amplifier enable signal; a replica circuit including a plurality of replica units connected in series, each of replica units including a plurality... Agent: Fujitsu Semiconductor Limited
20120257465 - Non-volatile memory device with plural reference cells, and method of setting the reference cells: A non-volatile memory device has an array of non-volatile memory cells, a first plurality of non-volatile memory reference cells, with each reference cell capable of being programmed to a reference level different from the other reference cells; and a second plurality of comparators. Each of the comparators is connectable to... Agent:
20120257460 - Method for indicating a non-flash nonvolatile multiple-type three-dimensional memory: Circuitry and a method for indicating a multiple-type memory is disclosed. The multiple-type memory includes memory blocks in communication with control logic blocks. The memory blocks and the control logic blocks are configured to emulate a plurality of memory types. The memory blocks can be configured into a plurality of... Agent: Unity Semiconductor Corporation
20120257466 - Duty cycle distortion correction: Correction of duty cycle distortion of DQ and DQS signals between a memory controller and a memory is corrected by determining a duty cycle correction factor. The duty cycle distortion is corrected by applying the duty cycle correction factor to the plurality of differential DQS signals. The duty cycle distortion... Agent: International Business Machines Corporation
20120257467 - Memory repair analysis apparatus, memory repair analysis method, and test apparatus: A memory repair analysis apparatus that performs a repair analysis on a memory under test, comprising a row-oriented fail number storage section that stores the number of fail cells in each row; a column-oriented fail number storage section that stores the number of fail cells in each column; a row-weighting... Agent: Advantest Corporation
20120257468 - Semiconductor memory device: A semiconductor memory device includes a transmission line configured to transmit a fuse enable signal for performance of a repair operation; a first repair enable signal generation unit configured to receive the fuse enable signal through the transmission line and generate a first repair enable signal for performing a repair... Agent: Hynix Semiconductor Inc.
20120257469 - Leakage and nbti reduction technique for memory: In one embodiment, an integrated circuit includes a logic circuit and a memory circuit that includes multiple bit lines and bit line precharge circuits. The memory circuit may include level shifters for control signals generated from logic circuit inputs, including one or more level shifters that generate precharge enable signals... Agent:10/04/2012 > 60 patent applications in 39 patent subcategories. categorized by USPTO classification
20120250386 - Circuit providing load isolation and noise reduction: Certain embodiments described herein include a memory module having a printed circuit board including at least one connector configured to be operatively coupled to a memory controller of a computer system. The memory module further includes a plurality of memory devices on the printed circuit board and a circuit including... Agent: Netlist, Inc.
20120250387 - Semiconductor device including plural chips stacked to each other: Disclosed herein is a device that includes a plurality of stacked core chips and an interface chip that controls the core chips. Each of the core chips includes a memory cell array, a penetration electrode, and an output circuit that outputs read data that are read from the memory cell... Agent: Elpida Memory, Inc.
20120250388 - Variable memory refresh devices and methods: Memory devices and methods are described such as those that monitor and adjust characteristics for various different portions of a given memory device. Examples of different portions include tiles, or arrays, or dies. One memory device and method described includes monitoring and adjusting characteristics of different portions of a 3D... Agent:
20120250389 - Mosfet fuse and array element: An alternative electrical fuse structure, which may be similar to or identical with an insulated gate field effect transistor (“IGFET”) of advanced CMOS technology, can be very area efficient and programmable at relatively low voltages, e.g., programming voltages between 1.5 V and 2.5 V. A method is provided for programming... Agent: International Business Machines Corporation
20120250390 - Memory cell and memory device including the same: A memory cell includes a light emitting unit, a phosphorescent layer, a polarization filter and a light detecting unit. The light emitting unit selectively generates a first light signal in response to a write data. The phosphorescent layer generates a second light signal using an energy absorbed from the first... Agent:
20120250392 - Data holding device and logic operation circuit using the same: A data holding device includes a loop structure unit configured to hold data using a plurality of logic gates connected in a loop shape, a nonvolatile storage unit including a plurality of ferroelectric elements, the nonvolatile storage unit configured to store the data held in the loop structure unit in... Agent: Rohm Co., Ltd.
20120250391 - Magnetic random access memory cell with a dual junction for ternary content addressable memory applications: The present disclosure concerns a MRAM cell comprising a first tunnel barrier layer comprised between a soft ferromagnetic layer having a free magnetization and a first hard ferromagnetic layer having a first storage magnetization; a second tunnel barrier layer comprised between the soft ferromagnetic layer and a second hard ferromagnetic... Agent: Crocus Technology Sa
20120250394 - Resistance change memory: According to one embodiment, a resistance change memory includes a memory cell including a resistance change element and a stacked layer structure which are connected in series, a control circuit configured to control a first operation of changing the resistance change element from a first resistance value to a second... Agent:
20120250395 - Selector type electronic device: An electronic device includes a first electrode, a second electrode and a solid electrolyte having a base of an ion conducting material. The device remains in the highly resistive state for as long as a first threshold voltage between the first electrode and the second electrode is not reached. The... Agent: Commissariat A L'energie Atomique Et Aux Energies Alternatives
20120250393 - Semiconductor memory device and controlling method thereof: According to one embodiment, a semiconductor memory device includes a memory cell array in which memory cells each including at least a rectification element and a variable resistance element, which are connected in series, a peripheral circuit, a sense amplifier configured to sense the memory cells via the peripheral circuit,... Agent:
20120250396 - Vertically stacked field programmable nonvolatile memory and method of fabrication: A memory cell is provided that includes a steering element, and a non-volatile state change element coupled in series with the steering element. The steering element and state change element are disposed in a vertically-oriented pillar. Other aspects are also provided.... Agent:
20120250397 - Semiconductor device and driving method thereof: The storage device includes a volatile first memory circuit and a nonvolatile second memory circuit which includes a transistor whose channel is formed in an oxide semiconductor layer. In the case of high-frequency driving, during a period when source voltage is applied, a data signal is input to and output... Agent: Semiconductor Energy Laboratory Co., Ltd.
20120250398 - Magnetic storage element, magnetic storage device, and magnetic memory: A magnetic storage element according to an embodiment includes: a magnetic thin wire extending in a first direction and having a plurality of magnetic domains partitioned by domain walls; an electrode capable of applying a current flowing in the first direction and a current flowing in the opposite direction from... Agent: Kabushiki Kaisha Toshiba
20120250399 - Memory circuit using spin mosfets, path transistor circuit with memory function, switching box circuit, switching block circuit, and field programmable gate array: A memory circuit according to an embodiment includes: a first transistor including a first source/drain electrode, a second source/drain electrode, and a first gate electrode; a second transistor including a third source/drain electrode connected to the second source/drain electrode, a fourth source/drain electrode, and a second gate electrode; a third... Agent: Kabushiki Kaisha Toshiba
20120250400 - Semiconductor memory device: The first reference-current setting circuit sets, as the first reference current, a current obtained by adding a first adjusting current to the reading current of the first reference cell. The second reference-current setting circuit sets, as the second reference current, a current obtained by adding a second adjusting current to... Agent: Kabushiki Kaisha Toshiba
20120250403 - Method for programming a resistive memory cell, a method and a memory apparatus for programming one or more resistive memory cells in a memory array: A method for programming a resistive memory cell is provided. The method may include providing a programming signal to the resistive memory cell. The programming signal may include an electrical pulse and a bias pulse coupled with the electrical pulse. The electrical pulse includes an electrical pulse portion, and the... Agent: Agency For Science, Technology And Research
20120250401 - Phase change memory (pcm) architecture and a method for writing into pcm architecture: A phase change memory (PCM) architecture and a method for writing a PCM architecture are described. In one embodiment, a PCM architecture includes a PCM array, word line driver circuits, bit line driver circuits, a source driver circuit and a voltage supply circuit. The bit line driver circuits are connected... Agent: Nxp B.v.
20120250402 - Semiconductor memory apparatus: A semiconductor memory apparatus includes a resistive memory cell; a data sensing unit configured to sense an output voltage, formed by a sensing current supplied to the resistive memory cell, based on a reference voltage, and output data having a value corresponding to the sensing result; and a reference voltage... Agent: Hynix Semiconductor Inc.
20120250405 - Magnetic field assisted stram cells: Memory units that have a magnetic tunnel junction cell that utilizes spin torque and a current induced magnetic field to assist in the switching of the magnetization orientation of the free layer of the magnetic tunnel junction cell. The memory unit includes a spin torque current source for passing a... Agent: Seagate Technology LLC
20120250404 - Magnetic tunnel junction with free layer having exchange coupled magnetic elements: A magnetic tunnel junction device includes a reference magnetic layer and a magnetic free layer including first and second magnetic elements that are magnetically exchange coupled. The magnetic exchange coupling between the first and second magnetic elements is configured to achieve a switching current distribution less than about 200% and... Agent: Seagate Technology LLC
20120250406 - Magnetic memory device and method of magnetic domain wall motion: A magnetic memory device comprises a first electrode, a second electrode, a laminated structure comprising plural first magnetic layers being provided between the first electrode and the second electrode, a second magnetic layer comprising different composition elements from that of the first magnetic layer and being provided between plural first... Agent: Kabushiki Kaisha Toshiba
20120250407 - Memory circuit, memory unit, and signal processing circuit: A memory circuit includes a transistor having a channel in an oxide semiconductor layer, a capacitor, a first arithmetic circuit, a second arithmetic circuit, a third arithmetic circuit, and a switch. An output terminal of the first arithmetic circuit is electrically connected to an input terminal of the second arithmetic... Agent: Semiconductor Energy Laboratory Co., Ltd.
20120250408 - Memory system, controller, and method for controlling memory system: According to one embodiment, a memory system includes nonvolatile memory having a plurality of memory cells of storage capacity of a specified number of bits equal to or greater than two bits, and a number-of-rewrites management table managing numbers of rewrites of the memory cells. The memory system of the... Agent: Kabushiki Kaisha Toshiba
20120250409 - Semiconductor memory and control method thereof: According to one embodiment, a semiconductor memory includes a memory cell array which includes memory cells, the memory cells being arranged along a row direction and a column direction and storing data respectively corresponding to thresholds, a row control circuit which controls a row of the memory cell array, and... Agent:
20120250411 - Nonvolatile semiconductor memory: According to one embodiment, a nonvolatile semiconductor memory includes a memory cell array including memory cells of a first unit in which read and write are parallelly performed, n (n is a natural number of not less than 2) sense amplifiers, n detection circuits corresponding to the n sense amplifiers,... Agent:
20120250410 - Semiconductor integrated circuit and data read method: A semiconductor integrated circuit includes a memory cell area comprising a main cell and a spare cell, and a memory controller configured to set an offset value using a program verify level which is set during a program operation, and set a read level using the offset value during a... Agent: Hynix Semiconductor Inc.
20120250412 - Flash memory apparatus and method for generating read voltage thereof: A flash memory apparatus includes: a cell array including a plurality of main blocks, a code addressable memory (CAM) block, and a security block; a control unit configured to detect a threshold voltage change data of a main block to which a program operation has been performed among the plurality... Agent: Hynix Semiconductor Inc.
20120250413 - Non-volatile semiconductor memory with page erase: In a nonvolatile memory, less than a full block maybe erased as one or more pages. A select voltage is applied through pass transistors to each of plural selected wordlines and an unselect voltage is applied through pass transistor to each of plural unselected wordlines of a selected block. A... Agent: Mosaid Technologies Incorporated
20120250414 - Reducing neighbor read disturb: Methods and devices for sensing non-volatile storage devices in a way that reduces read disturb are disclosed. Techniques are used to reduce read disturb on memory cells that are neighbors to selected memory cells. For example, on a NAND string, the memory cells that are next to the selected memory... Agent:
20120250415 - Simultaneous multi-state read or verify in non-volatile storage: Methods and devices for simultaneously verifying or reading multiple states in non-volatile storage are disclosed. Methods and devices for efficiently reducing or eliminating cross-coupling effects in non-volatile storage are disclosed. Methods and devices for efficiently performing reads at a number of voltages to search for the threshold voltage of a... Agent:
20120250417 - Hot electron injection nanocrystals mos transistor: The disclosure relates to a hot electron injection MOS transistor, comprising source and drain regions formed in a semiconductor substrate, a control gate, and a floating gate comprising electrically conductive nanoparticles. The control gate comprises a first portion arranged at a first distance from the substrate, a second portion arranged... Agent: Stmicroelectronics (rousset) Sas
20120250416 - Semiconductor memory device: A semiconductor memory device includes: a memory cell array including plural memory cells; a first word line connected to a control gate of a first memory cell; a second word line connected to a control gate of a second memory cell and neighboring the first word line on one side;... Agent: Kabushiki Kaisha Toshiba
20120250418 - Natural threshold voltage distribution compaction in non-volatile memory: In a non-volatile memory system, a multi-phase programming operation is performed in which a drain-side select gate voltage (Vsgd) can be adjusted in different programming phases to accommodate different bit line bias (Vbl) levels. A higher Vbl can be used when Vsgd is higher to avoid unnecessary stress on the... Agent:
20120250419 - Method of controlling nonvolatile semiconductor memory device: In one embodiment, method of controlling a semiconductor nonvolatile memory device includes determining data written to an adjacent memory cell which is adjacent to a selection memory cell in memory cells configured as a matrix, the selection memory being selected by a program operation for writing the data to the... Agent: Kabushiki Kaisha Toshiba
20120250420 - Non-volatile semiconductor memory device: A control circuit performs a read operation of reading data held in a memory-cell by supplying a selected word-line with a read voltage that is a voltage between the lower limit and the upper limit of a plurality of threshold-voltage distributions provided to the memory-cell. The control circuit also performs... Agent: Kabushiki Kaisha Toshiba
20120250421 - Charge pump circuit using low voltage transistors: The charge pump circuit has a plurality of cascaded charge pump stages, each provided with a first pump capacitor connected to a first internal node and receiving a first high voltage phase signal, and a second pump capacitor connected to a second internal node and receiving a second high voltage... Agent: Stmicroelectronics S.r.l.
20120250422 - Interleaving charge pumps for programmable memories: Systems and methods, including computer software for performing operations enable interleaving of charging operations in a charging pump. A first charge pump is charged to a predetermined level, and a first operation is performed using a charge stored in the first charge pump after it reaches the predetermined level. A... Agent: Apple Inc., A California Corporation
20120250428 - Memory device, recording method, and recording and reproducing method: A memory device, includes a recording medium; a probe to write a plurality of the signals; a first driving portion to vibratory drive the recording medium; a detecting unit which, when the first driving portion changes a frequency to vibratory drive the recording medium, detects a change in an amplitude... Agent: Kabushiki Kaisha Toshiba
20120250429 - Security-protection of a wafer of electronic circuits: A process is provided for fabricating a wafer including a plurality of chips separated by scribe lines. The method includes locking at least one chip on the wafer using a secret key, and writing the secret key into at least one memory present on the wafer.... Agent: Stmicroelectronics N.v.
20120250423 - Input circuit: The first input circuit detects an input signal to output a first output signal having the same phase as the input signal. The second input circuit is configured to detect a first strobe signal to output a second output signal. The third input circuit is configured to detect a second... Agent: Kabushiki Kaisha Toshiba
20120250425 - Semiconductor memory and semiconductor memory control method: According to one embodiment, the semiconductor memory includes a memory cell array which includes memory cells to store data, a buffer circuit which includes latches, each of the latches including transistors as control elements and a flip-flop, and a control circuit which turns off the transistors to deactivate one or... Agent:
20120250424 - Semiconductor memory device: A sense amplifier circuit is connected to a bit-line and senses and amplifies a signal read from a memory cell. A first data latch is connected to a sense amplifier via a first bus. A second data latch is connected to a second bus. A plurality of circuit groups are... Agent: Kabushiki Kaisha Toshiba
20120250426 - Apparatus and method to adjust clock duty cycle of memory: An embodiment of the invention provides a memory controller for controlling a memory. The memory controller comprises a pulse width modulation module, a voltage comparator and a duty cycle calibration device. The pulse width modulation module is suitable for receiving a clock signal to generate a first voltage. The voltage... Agent: Mediatek Inc.
20120250427 - Multi-mode interface circuit: An interface circuit having a first signal path and a second signal path is disclosed. The first and second signal paths are coupled between a first and second nodes, wherein the first node is coupled to receive signals from a source external to an integrated circuit upon which the interface... Agent:
20120250430 - Circuit for preventing a dummy read in a memory: A memory includes a row decoder, column logic, and a memory array having a plurality of memory cells arranged in rows and columns. A plurality of write word lines are coupled to the row decoder. A plurality of complementary write word lines is coupled to the row decoder. A plurality... Agent:
20120250432 - Semiconductor device: To provide a semiconductor device which can perform initialization to a first state of two states of the first state and a second state, and which can generate a signal having a potential corresponding to the initialized first state. The present invention is the semiconductor device which can perform initialization... Agent: Renesas Electronics Corporation
20120250431 - Semiconductor memory apparatus and method for driving the same: A semiconductor memory apparatus includes: a memory block including first and second planes; and a reset signal generator configured to generate a first reset signal by logically combining a first plane selection signal and a control pulse signal which pulses after a first programming setup pulse signal pulses during a... Agent: Hynix Semiconductor Inc.
20120250433 - Memory devices, systems and methods employing command/address calibration: During a command/address calibration mode, a memory controller may transmit multiple cycles of test patterns as signals to a memory device. Each cycle of test pattern signals may be transmitted at an adjusted relative phase with respect to a clock also transmitted to the memory device. The memory device may... Agent:
20120250434 - Method of accelerating write timing calibration and write timing calibration acceleration circuit in semiconductor memory device: A method of accelerating write timing calibration and a write timing calibration acceleration circuit in a semiconductor memory device are disclosed. The write timing calibration acceleration circuit includes a phase difference detection unit and a detection data output unit. The phase difference detection unit detects a phase difference between a... Agent: Samsung Electronics Co., Ltd.
20120250435 - Semiconductor device and method of cotnroling the same: A device includes a command decoder that is configured to output, in a normal operation mode, a precharge signal in response to a first type transition edge of a synchronous signal, and an active signal in response to a next first type transition edge that is next to the first... Agent: Elpida Memory, Inc.
20120250436 - Impedance matching between fpga and memory modules: Embodiments of the present invention provide impedance matching between a Field Programmable Gate Array (FPGA) and memory modules in a semiconductor storage device (SSD) system architecture. Specifically, a set (at least one) of memory modules is coupled to an FPGA. A damping resistor is placed at the impedance mismatching point... Agent:
20120250437 - Semiconductor device, control method thereof and data processing system: Disclosed herein is a semiconductor device comprising a global bit line, a first local bit line coupled to normal memory cells, a second local bit line coupled to redundant memory cells first and second hierarchical switches, a precharge circuit precharging the global bit line, a redundancy determination circuit determining whether... Agent: Elpida Memory, Inc.
20120250438 - Dynamic random access memory address line test technique: Verification of the address connections of a memory (14) having multiplexed banks rows and columns commences by selecting a first address location having a bank/row/column value and then writing a pattern to a second location corresponding to the first location where one of the column, row, bank addresses could become... Agent:
20120250439 - Degradation equalization for a memory: In an embodiment, an integrated circuit includes a memory and a control circuit configured to cause an inversion of at least a portion of the data stored in the memory to more evenly balance the amount of time that a given memory cell in the memory stores a binary one... Agent:
20120250440 - Differential read write back sense amplifier circuits and methods: A differential read write back sense amplifier circuit and corresponding methods. A memory array comprises a plurality of memory cells arranged in rows and columns; a plurality of read word lines coupled to the memory cells; a plurality of write word lines coupled to the memory cells arranged along rows... Agent: Taiwan Semiconductor Manufacturing Company, Ltd.
20120250442 - Methods for accessing dram cells using separate bit line control: A memory system that includes a first bit line coupled to a first set of dynamic random access memory (DRAM) cells, a second (complementary) bit line coupled to a second set of DRAM cells, and a sense amplifier coupled to the first and second bit lines. The sense amplifier includes... Agent: Mosys, Inc.
20120250441 - Separate pass gate controlled sense amplifier: A memory system that includes a first bit line coupled to a first set of dynamic random access memory (DRAM) cells, a second (complementary) bit line coupled to a second set of DRAM cells, and a sense amplifier coupled to the first and second bit lines. The sense amplifier includes... Agent: Mosys, Inc.
20120250443 - Energy efficient power distribution for 3d integrated circuit stack: m
20120250444 - Pseudo-inverter circuit on seoi: A circuit made on a semiconductor-on-insulator substrate. The circuit includes a first transistor having a first channel, a second transistor having a second channel, with the transistors provided in serial association between first and second terminals for applying a power supply potential, each of the transistors comprising a drain region... Agent: Soitec
20120250445 - Semiconductor apparatus: A semiconductor apparatus includes a programmable logic chip configured to output a control signal, and a memory chip coupled to the programmable logic chip. The memory chip includes a plurality of memory cores, a plurality of bus-interface circuits each configured to couple with the memory cores, and a selection circuit... Agent: Renesas Electronics CorporationPrevious industry: Electric power conversion systems
Next industry: Agitating
RSS FEED for 20150611:
Integrate FreshPatents.com into your RSS reader/aggregator or website to track weekly updates.
For more info, read this article.
Thank you for viewing Static information storage and retrieval patents on the FreshPatents.com website. These are patent applications which have been filed in the United States. There are a variety ways to browse Static information storage and retrieval patent applications on our website including browsing by date, agent, inventor, and industry. If you are interested in receiving occasional emails regarding Static information storage and retrieval patents we recommend signing up for free keyword monitoring by email.
Advertise on FreshPatents.com - Rates & Info
FreshPatents.com Support - Terms & Conditions
Results in 0.25059 seconds