|Static information storage and retrieval patents - Monitor Patents|
USPTO Class 365 | Browse by Industry: Previous - Next | All
09/2012 | Recent | 14: | Sep | Aug | Jul | Jun | May | Apr | Mar | Feb | Jan | 13: Dec | Nov | Oct | Sep | Aug | Jul | Jun | May | Apr | Mar | Feb | Jan | 12: Dec | Nov | Oct | Sep | Aug | July | June | May | April | Mar | Feb | Jan | 11: Dec | Nov | Oct | Sep | Aug | Jul | Jun | May | Apr | Mar | Feb | Jan | 10: Dec | Nov | Oct | Sep | Aug | Jul | Jun | May | Apr | Mar | Feb | Jan | | 09: Dec | Nov | Oct | Sep | Aug | Jl | Jn | May | Apr | Mar | Fb | Jn | | 2008 | 2007 |
Static information storage and retrieval September class, title,number 09/12Below are recently published patent applications awaiting approval from the USPTO. Recent week's RSS XML file available below.
Listing for abstract view: USPTO application #, Title, Abstract excerpt,Patent Agent. Listing format for list view: USPTO National Class full category number, title of the patent application. 09/27/2012 > 83 patent applications in 43 patent subcategories. class, title,number
20120243283 - Using storage cells to perform computation: A method includes activating at least two rows of pure memory cells and reading at least one column of activated the memory cells, the reading generating a binary function of data stored in the activated memory cells.... Agent: Zikbit Ltd.
20120243284 - Using storage cells to perform computation: A content addressable memory (CAM) unit does not have any in-cell comparator circuitry. The CAM unit includes a memory array, a multiple row decoder, a controller and an output unit. The memory array has storage cells arranged as data rows and complement rows. The multiple row decoder activates more than... Agent: Zikbit Ltd.
20120243285 - Multiple write during simultaneous memory access of a multi-port memory device: A memory system may provide for a successful write of a multi-port memory cell (e.g., dual-port 2WR SRAM cell) when it is simultaneously accessed by more than one port. This multi-port memory cell may include at least two independent accesses to the memory cell, where each access may be controlled... Agent: Easic Corporation
20120243286 - Semiconductor storage device: A semiconductor storage device according to the present embodiment includes a plurality of bit lines, a plurality of word lines, and a plurality of memory cells each including a storage element and a switching element which are connected in series between adjacently paired ones of the bit lines. Gates of... Agent: Kabushiki Kaisha Toshiba
20120243287 - Semiconductor memory device capable of improving disturbability and writability: According to one embodiment, a semiconductor memory device includes memory cells and sense amplifiers. Each of the memory cells comprises a flip-flop circuit and first to fourth transistors. The flip-flop circuit includes a first storage node and a second storage node. The first and second transistors are connected between the... Agent: Kabushiki Kaisha Toshiba
20120243289 - Electric fuse, semiconductor device, and information writing method of electric fuse: An electric fuse includes: a filament having a first conductive layer and a second conductive layer formed on the first conductive layer, wherein at least three discernible resistive states are generated in the filament by changing of a combination of a state of the first conductive layer and a state... Agent: Sony Corporation
20120243288 - Method for leakage reduction in memory circuits: An apparatus includes a bit cell of a programmable memory circuit. The bit cell includes a programmable device. The bit cell includes a first device having a first type. The first device is configured to conduct a first current between a first node and a second node in response to... Agent:
20120243290 - Multi-level electrical fuse using one programming device: A method for programming a multi-level electrical fuse system comprises providing a fuse box with an electrical fuse and providing one of at least two fuse writing voltages to the electrical fuse to program the electrical fuse to one of at least two resistance states. The fuse box comprises at... Agent: Taiwan Semiconductor Manufacturing Co., Ltd.
20120243291 - Crosspoint array and method of use with a crosspoint array having crossbar elements having a solid electrolyte material used as a rectifier with a symmetric or substantially symmetric resistive memory: A crosspoint array has been shown having a plurality of bitlines and wordlines; and a plurality of crossbar elements, with each crossbar element being disposed between a bitline and a wordline and with each crossbar element having at least a solid electrolyte material used as a rectifier in series with... Agent: International Business Machines Corporation
20120243292 - Memory device: According to one embodiment, a memory device includes a first electrode including a crystallized SixGe1-x layer (0≦x<1), a second electrode including a metal element, a variable resistance part between the first and second electrode, the part including an amorphous Si layer, and a control circuit controlling a filament in the... Agent:
20120243298 - Method and apparatus providing a cross-point memory array using a variable resistance memory cell and capacitance: The invention relates to a method and apparatus providing a memory cell array in which each resistance memory cell is connected in series to a capacitive element. Access transistors are not necessary to perform read and write operations on the memory cell. In one exemplary embodiment, the capacitive element is... Agent:
20120243293 - Nonvolatile semiconductor memory device: According to one embodiment, a nonvolatile semiconductor memory device includes a memory cell includes a variable resistance element and a capacitor connected in series between first and second conductive lines, and a control circuit applying one of first and second voltage pulses to the memory cell. The capacitor is charged... Agent:
20120243295 - Nonvolatile semiconductor memory device and method of control therein: A nonvolatile semiconductor memory device comprises a memory cell array, a control circuit, a current limiting circuit and a current suppression circuit. The memory cell array has a first line, a second line, and a memory cell arranged therein, the memory cell being connected between the first line and the... Agent: Kabushiki Kaisha Toshiba
20120243297 - Resistance change type memory: According to one embodiment, a resistance change type memory includes first to third bit lines, a word line and a memory cell connected to the first to third bit lines and the word line. The memory cell includes a first transistor and a first memory element between the first and... Agent:
20120243294 - Resistance-change memory: According to one embodiment, a resistance-change memory includes bit lines, word lines, a memory cell array including memory cells arranged at intersections between the bit lines and the word lines, each of the memory cells including a variable-resistance element and a diode, a control circuit configured to apply a reverse... Agent:
20120243296 - Semiconductor memory device: A semiconductor memory device includes: plural word lines extending in a first direction; first to third bit lines extending in a second direction that intersects with the first direction; plural variable resistance elements each having a first terminal connected to either one of the first and third bit lines; plural... Agent: Kabushiki Kaisha Toshiba
20120243299 - Power efficient dynamic random access memory devices: The present invention provides methods and structures for improving refresh power efficiency of dynamic random access memory devices. By measuring charge retention properties of reference cells that have substantially the same structures as normal DRAM memory cells, the refresh rate of DRAM devices can be adjusted with better reliability. The... Agent:
20120243300 - Combined data level-shifter and de-skewer: Various embodiments of this disclosure may describe a circuit for transmitting data from a transmitting region of an integrated circuit to a receiving region of the integrated circuit. The circuit may level-shift the data to the appropriate voltage level and may have good tolerance to clock skews. Other embodiments, including... Agent:
20120243301 - Memory devices and methods for high random transaction rate: A memory device can include a plurality of double data rate data (DDR) ports, each configured to receive write data and output read data on a same set of data lines independently and concurrently in synchronism with at least a first clock signal; an address port configured to receive address... Agent: Cypress Semiconductor Corporation
20120243302 - Semiconductor memory device that can stably perform writing and reading without increasing current consumption even with a low power supply voltage: Cell power supply lines are arranged for memory cell columns, and adjust impedances or voltage levels of the cell power supply lines according to the voltage levels of bit lines in the corresponding columns, respectively. In the data write operation, the cell power supply line is forced into a floating... Agent: Renesas Electronics Corporation
20120243305 - Magnetoresistance effect element and magnetic memory: According to one embodiment, a magnetoresistance effect element includes first and second magnetic layers having an axis of easy magnetization in a direction perpendicular to a film surface, a first nonmagnetic layer formed between the first and second magnetic layers, a first interface magnetic layer formed between the first magnetic... Agent:
20120243303 - Semiconductor storage device: A semiconductor storage device according to the present embodiment includes a magnetic tunnel junction element capable of storing data according to a change in resistance state and rewriting the data using a current. A cell transistor is provided for the magnetic tunnel junction element and is placed in a conducting... Agent: Kabushiki Kaisha Toshiba
20120243304 - Semiconductor storage device: A semiconductor storage device according to the present embodiment comprises a plurality of bit lines, a plurality of word lines, and a plurality of memory cells corresponding to intersections between the bit lines and the word lines, respectively, and including magnetic tunnel junction elements capable of storing data. A plurality... Agent: Kabushiki Kaisha Toshiba
20120243306 - Method and apparatus to reset a phase change memory and switch (pcms) memory cell: The present disclosure relates to the fabrication of non-volatile memory devices. In at least one embodiment, the non-volatile memory of the present disclosure may include a phase change memory and switch (hereinafter “PCMS”) memory cell and a process for resetting the PCMS memory utilizing a “look-up” table to calculate a... Agent:
20120243307 - Resistance change nonvolatile semiconductor memory device: According to one embodiment, a phase change memory includes a memory cell, a select transistor, and a memory cell array. The memory cell includes a chalcogenide wiring, resistance wirings and a cell transistor. The chalcogenide wiring becomes a heater. One end of a plurality of memory cells with sources and... Agent: Kabushiki Kaisha Toshiba
20120243308 - Magnetic element and nonvolatile memory device: According to one embodiment, a magnetic element includes first and second conductive layers, an intermediate interconnection, and first and second stacked units. The intermediate interconnection is provided between the conductive layers. The first stacked unit is provided between the first conductive layer and the interconnection, and includes first and second... Agent: Kabushiki Kaisha Toshiba
20120243309 - Non-volatile semiconductor memory device: When performing a data erase operation, the control circuit generates positive holes at least at any one of the drain side select transistor and the source side select transistor, and supply the positive holes to a body of the memory string to raise a voltage of the body of the... Agent: Kabushiki Kaisha Toshiba
20120243310 - Method of programming a multi-bit per cell non-volatile memory: A method of programming a multi-bit per cell non-volatile memory is disclosed. In one embodiment, the non-volatile memory is read to obtain a first data of a most-significant-bit (MSB) page on a current word line that succeeds in data reading, wherein the current word line follows a preceding word line... Agent: Skymedi Corporation
20120243311 - Non-sequential encoding scheme for multi-level cell (mlc) memory cells: Apparatus and method for managing an array of multi-level cell (MLC) memory cells. In accordance with various embodiments, a non-sequential encoding scheme is selected that assigns a different multi-bit logical value to each of a plurality of available physical states of a selected MLC memory cell in relation to write... Agent: Seagate Technology LLC
20120243312 - Semiconductor memory device comprising memory cell having charge accumulation layer and control gate and method of erasing data thereof: A semiconductor memory device includes a memory cell, a bit line, a source line, and a sense amplifier. The memory cell has a stacked gate including a charge accumulation layer and a control gate. The bit line is electrically connected to a drain of the memory cell. The source line... Agent:
20120243314 - Nonvolatile semiconductor memory device: A nonvolatile semiconductor memory device according to one aspect includes a semiconductor substrate, a memory string, a plurality of first conductive layers, a second conductive layer, and a third conductive layer. The memory string has a plurality of memory cells, a dummy transistor and a back gate transistor connected in... Agent: Kabushiki Kaisha Toshiba
20120243313 - Semiconductor memory array and method for programming the same: The invention provides a flash memory array structure and a method for programming the same, which relates to a technical field of nonvolatile memories in ultra large scale integrated circuit fabrication technology. The flash memory array of the present invention includes memory cells, word lines and bit lines connected to... Agent:
20120243315 - Semiconductor memory device: In a semiconductor memory device in which each memory cell is constituted by one transistor, in a memory cell pattern, two adjacent bits form one diffusion pattern, two adjacent transistors share a source region, and two drain regions are separated from each other. A plurality of arrays in each of... Agent: Panasonic Corporation
20120243316 - Memory devices and their operation with different sets of logical erase blocks: Methods of operating memory devices include storing data of a first type in a first set of logical erase blocks and storing data of a second type in a second set of logical erase blocks. The logical erase blocks of the first set of logical erase blocks each have a... Agent: Round Rock Research, LLC
20120243317 - Non-volatile semiconductor memory device: According to one embodiment, a non-volatile semiconductor memory device includes a writing unit that performs a writing operation on memory cells while stepping up a writing voltage based on a check result of a verifying operation on the memory cells, a threshold-value determining unit that determines threshold values of the... Agent: Kabushiki Kaisha Toshiba
20120243318 - Non-volatile memory programming: Some embodiments include a memory device and a method of programming memory cells of the memory device. One such method can include applying a signal to a line associated with a memory cell, the signal being generated based on digital information. The method can also include, while the signal is... Agent: Micron Technology, Inc.
20120243319 - Nonvolatile semicondcutor memory device, ic card and portable apparatus: According to one embodiment, a nonvolatile semiconductor memory device includes a first nonvolatile memory, and a voltage generation circuit configured to apply a voltage to the first nonvolatile memory, the voltage generation circuit includes a charge pump and an oscillator configured to generate a clock to be used to operate... Agent: Kabushiki Kaisha Toshiba
20120243322 - Semiconductor integrated circuit adapted to output pass/fail results of internal operations: In a semiconductor integrated circuit, an internal circuit is capable of executing a first operation and a second operation concurrently, and an output circuit outputs to the outside of the semiconductor integrated circuit information indicating whether or not the first operation is being executed and information indicating whether or not... Agent:
20120243320 - Semiconductor memory device: According to one embodiment, a semiconductor memory device includes a plurality of memory cells, a logic gate chain, and a counter. The memory cells are capable of retaining data and are associated with the columns. The logic gate chain includes a plurality of logic gates associated with the columns. Each... Agent:
20120243321 - Semiconductor memory device: According to one embodiment, there is provided a semiconductor memory device including a memory cell array, a storage unit, a selection unit, a startup processing unit, and an operation control unit. The memory cell array includes memory cells. The storage unit stores a plurality of operating parameters. The selection unit... Agent: Kabushiki Kaisha Toshiba
20120243324 - Non-volatile semiconductor storage device: A non-volatile semiconductor storage device according to one embodiment includes a memory cell array that has NAND cell units in which a plurality of memory cells connected in series, the control gate of each of the plurality of memory cells being connected to a word line, and a control circuit... Agent: Kabushiki Kaisha Toshiba
20120243323 - Nonvolatile memory and method for improved programming with reduced verify: A group of memory cells of a nonvolatile memory is programmed in parallel in a programming pass with a minimum of verify steps from an erased state to respective target states by a staircase waveform. The memory states are demarcated by a set of increasing demarcation threshold values (V1, .... Agent:
20120243327 - Nonvolatile semiconductor memory: A memory includes first and second select gate transistors, memory cells, a source line, a bit line, a selected word line which is connected to a selected memory cell as a target of a verify reading, a non-selected word line which is connected to a non-selected memory cell except the... Agent:
20120243325 - Semiconductor memory device: A semiconductor memory device according to one embodiment includes: a memory cell array including electrically-rewritable memory cells; bit lines each connected to one end of the memory cells and charged in response to a certain operation; and a voltage generating circuit configured to control a charging operation on the bit... Agent: Kabushiki Kaisha Toshiba
20120243326 - Semiconductor storage device: According to one embodiment, a device includes transistors each with a path connected to a bit line, and circuits each includes a switch, the circuit being connected to the bit line. The device includes a amplifier connected to the transistor and to the circuit, and a latch connected to the... Agent:
20120243333 - Apparatus comparing verified data to original data in the programming of memory cells: Apparatus configured to perform a programming operation on a row of memory cells in response to original data, and further configured to perform a comparison of verified data of the row of memory cells to the original data following success of the programming of the row of memory cells.... Agent: Micron Technology, Inc.
20120243329 - Memory system: According to one embodiment, there is provided memory system including a non-volatile memory device, a monitoring unit, and a changing unit. The non-volatile memory device stores data. The monitoring unit monitors a characteristic of the non-volatile memory device when writing and erasing processes are performed to write and erase the... Agent: Kabushiki Kaisha Toshiba
20120243332 - Non-volatile memory and method with power-saving read and program-verify operations: A non-volatile memory device capable of reading and writing a large number of memory cells with multiple read/write circuits in parallel has features to reduce power consumption during read, and program/verify operations. A read or program verify operation includes one or more sensing cycles relative to one or more demarcation... Agent:
20120243328 - Nonvolatile semiconductor memory device and data erase method of the same: According to one embodiment, a nonvolatile semiconductor memory device includes a memory cell array includes a plurality of pages formed in a common semiconductor region, each of the pages includes a plurality of electrically programmable memory cells, a control circuit configured to performs an erase operation for a selected page,... Agent: Kabushiki Kaisha Toshiba
20120243330 - Nonvolatile semiconductor storage device: A nonvolatile semiconductor storage device according to an embodiment includes an erase circuit executing an erase sequence, wherein in the erase sequence, the erase circuit executes: an erase operation to change a selection memory cell group to an erased state, after the erase operation, a soft program operation on the... Agent: Kabushiki Kaisha Toshiba
20120243331 - Semiconductor memory device: According to one embodiment, a semiconductor memory device includes a cell array, a voltage generator, and a controller. The memory cells are formed along rows and columns. The voltage generator generates a write voltage and a verify voltage. The voltage generator transfers a first voltage to the memory cell having... Agent:
20120243334 - Flash memory device and programming method thereof: A flash memory device including a memory array, a row decoder and M page buffers is provided, wherein M is a positive integer. The memory array includes a plurality of memory cells and is electrically connected to a plurality of word lines and a plurality of bit lines. The row... Agent: Macronix International Co., Ltd.
20120243335 - Non-volatile semiconductor memory with bit line hierarchy: Local bit lines (LBL) are respectively provided for a plurality of sectors, corresponding to each of the global bit lines (GBL). Sector select transistors connect a LBL to a GBLector select lines control the on/off state of the sector select transistors for the corresponding sectors. A plurality of word lines... Agent: Fujitsu Semiconductor Limited
20120243336 - Nonvolatile programmable logic switch: An aspect of the present embodiment, there is provided a nonvolatile programmable logic switch including a first memory cell transistor, a second memory cell transistor, a pass transistor and a first substrate electrode applying a substrate voltage to the pass transistor, wherein a writing voltage is applied to the first... Agent:
20120243339 - Nonvolatile memory devices including notched word lines: Nonvolatile memory devices can include a floating gate on a substrate, with a first tunnel insulating film therebetween. A memory gate can be on the floating gate, with a blocking insulating film therebetween. A word line can be located at a first side of both the memory gate and the... Agent: Samsung Electronics Co., Ltd.
20120243338 - Nonvolatile semiconductor storage device: A nonvolatile semiconductor storage device of an embodiment includes: a cell array including a plurality of memory cells formed on a well and configured by a charge accumulating layer and a control gate; a plurality of control gate lines that are paths for supplying a voltage necessary to access the... Agent: Kabushiki Kaisha Toshiba
20120243337 - P-/metal floating gate non-volatile storage element: Non-volatile storage elements having a P−/metal floating gate are disclosed herein. The floating gate may have a P− region near the tunnel oxide, and may have a metal region near the control gate. A P− region near the tunnel oxide helps provide good data retention. A metal region near the... Agent:
20120243346 - Control method for memory cell: A control method for at least one memory cell. The memory cell includes a transistor and a resistor. The resistor is connected to the transistor in series between a first node and a second node. In a programming mode, the memory cell is programmed. When it is determined that the... Agent: Industrial Technology Research Institute
20120243345 - Output driver circuit, output driver system and semiconductor memory device: The output driver circuit includes a plurality of pull-up sub-drivers that pull up a voltage at the output terminal according to a pull-up signal based on the output data. The output driver circuit includes a plurality of pull-down sub-drivers that pull down the voltage at the output terminal according to... Agent: Kabushiki Kaisha Toshiba
20120243341 - Semiconductor device having plural data buses and plural buffer circuits connected to data buses: Disclosed herein is a device that includes a plurality of buffer circuits and data buses coupled to the buffer circuits. Each of the data buses includes first and second portions. The first portions of the data buses are arranged at a first pitch in the second direction, and the second... Agent: Elpida Memory, Inc.
20120243342 - Sense amplification circuits, output circuits, nonvolatile memory devices, memory systems, memory cards having the same, and data outputting methods thereof: An output circuit of a nonvolatile memory device includes a sense amplification circuit configured to, during a sensing operation, generate output data based on a comparison between a first voltage on a data line and a reference voltage on a reference data line during a sensing operation, the first voltage... Agent:
20120243343 - Methods for sensing memory elements in semiconductor devices: A memory device that, in certain embodiments, includes a plurality of memory elements connected to a bit-line and a delta-sigma modulator with a digital output and an analog input, which may be connected to the bit-line. In some embodiments, the delta-sigma modulator includes a circuit with first and second inputs... Agent: Micron Technology, Inc.
20120243344 - Row address decoding block for non-volatile memories and methods for decoding pre-decoded address information: Decoding blocks, memories, and methods for decoding pre-decoded address information are disclosed. One such decoding block includes a first latch and voltage shift circuit configured to receive first pre-decoded address information at first voltage levels and further configured to latch the first pre-decoded address information and shift the voltage levels... Agent:
20120243347 - Memory cells having a row-based read and/or write support circuitry: A method of controlling a plurality of memory cells in a row. The method includes controlling a switching element using at least one write word line signal to raise a voltage of a node connected to the plurality of memory cells in the row when the plurality of memory cells... Agent: Taiwan Semiconductor Manufacturing Company, Ltd.
20120243348 - Method and apparatus of changing device identification codes of a memory integrated circuit device: In the disclosed technology, the device identification code of a memory integrated circuit is changeable. In some cases, multiple device identification codes are stored on the memory integrated circuit, and multiple device identification code selection data are stored on the memory integrated circuit.... Agent: Macronix International Co., Ltd.
20120243349 - Program cycle skip: A non-volatile storage system includes technology for skipping programming cycles while programming a page (or other unit) of data. While programming a current subset of the page (or other unit) of data, the system will evaluate whether the next subsets of the page (or other unit) of data should be... Agent:
20120243340 - Signal processing circuit: To provide a signal processing circuit including a nonvolatile memory circuit with a novel structure, the signal processing circuit includes an arithmetic portion, a memory, and a control portion for controlling the arithmetic portion and the memory. The control portion includes a set of a volatile memory circuit and a... Agent: Semiconductor Energy Laboratory Co., Ltd.
20120243350 - Address delay circuit of semiconductor memory apparatus: An address delay circuit of a semiconductor memory apparatus includes a first group control pulse generation unit configured to generate a first control pulse after input of a first group column address strobe pulse and passage of a time corresponding to a first set multiple of one cycle of a... Agent: Hynix Semiconductor Inc.
20120243351 - Semiconductor device: A semiconductor device controls read-out operation of a semiconductor memory that outputs a parallel data signal and a strobe signal at a timing in synchronism with each other. The semiconductor device has a first phase control circuit configured to output a delay strobe signal which delays the strobe signal for... Agent: Kabushiki Kaisha Toshiba
20120243352 - Semiconductor memory device, method of controlling read preamble signal thereof, and data transmission system: A system, includes a controller comprising a plurality of first external terminals configured to supply a command, a clock signal and an address, and communicate a data, and communicate a strobe signal related to the data, and a semiconductor memory device including a plurality of second external terminals corresponding to... Agent: Elpida Memory, Inc.
20120243353 - Digital dll for timing control in semiconductor memory: A semiconductor memory includes a delay locked loop (DLL) configured to generate a timing code based on a clock signal. A plurality of memory devices are coupled to the DLL. Each of the plurality of memory devices is configured to generate internal control signals for operating a memory array based... Agent: Taiwan Semiconductor Manufacturing Co., Ltd.
20120243354 - Repairing soft failures in memory cells in sram arrays: An embodiment of the invention provides a method of repairing soft failures in memory cells of an SRAM array. The SRAM array is tested to determine the location and type of soft failures in the memory cells. An assist circuit is activated that changes a voltage in a group of... Agent: Texas Instruments Incorporated
20120243355 - Semiconductor apparatus: Various embodiments of a semiconductor apparatus are disclosed. In one exemplary embodiment, a semiconductor apparatus may include a memory block chip and a signal input/output chip. The memory block chip is configured to control a data access size according to specifications. The signal input/output chip is configured to transmit input... Agent: Hynix Semiconductor Inc.
20120243356 - Semiconductor storage device: According to one embodiment, a memory cell stores therein data. In a bit line, a potential changes according to write data to be written in the memory cell. A precharge circuit precharges the bit line. A precharge control circuit controls precharge of the bit line based on the potential of... Agent: Kabushiki Kaisha Toshiba
20120243357 - Nonvolatile semiconductor storage: According to one embodiment, a memory cell is configured using a field effect transistor and includes n anti-fuse elements, one ends of which are connected in common. A program voltage selection circuit selects, out of the n anti-fuse elements, an anti-fuse element to which a program voltage is applied. A... Agent: Kabushiki Kaisha Toshiba
20120243358 - Semiconductor device and method of manufacturing the same: According to one embodiment, a semiconductor device includes a semiconductor substrate including a device region which is isolated by a device isolation film, a first conductive layer provided on the device region via a gate insulation film, an inter-gate insulation film provided on the first conductive layer and including an... Agent:
20120243360 - Semiconductor memory having staggered sense amplifiers associated with a local column decoder: A semiconductor memory having bit lines and wordlines crossing each other, a memory cell array formed by memory cells arranged in rows and columns on crossover points of the bit lines and wordlines, and sense amplifier banks arranged on opposite sides of the memory cell array. Each sense amplifier bank... Agent:
20120243359 - Sense amplifier: A circuit comprises a first node, a second node, a sense amplifier, at least one first transistor, at least one second transistor, and one or a combination of a first control circuit and a second control circuit. The first control circuit is configured to generate a first control signal for... Agent: Taiwan Semiconductor Manufacturing Company, Ltd.
20120243361 - Data serializers, output buffers, memory devices and methods of serializing: Data serializers, output buffers, memory devices and methods for serializing are provided, including a data serializer that may convert digits of parallel data to a stream of corresponding digits of serial data digits. One such data serializer may include a logic system receiving the parallel data digits and clock signals... Agent: Micron Technology, Inc.
20120243362 - Advanced detection of memory device removal, and methods, devices and connectors: Memory devices, connectors and methods for terminating an operation are provided, including a memory device configured to terminate an internal operation such as a programming or erase operation responsive to receiving a signal during removal of the memory device from a connector, such as a socket. The memory device may... Agent:
20120243363 - Power line layout techniques for integrated circuits having modular cells: An integrated circuit (IC) chip includes a first memory cell array block having a first metal layer containing at least two power lines, and a second memory cell array block containing at least two power lines independent of each other, wherein all the power lines on the first metal layer... Agent: Taiwan Semiconductor Manufacturing Company, Ltd.
20120243364 - Method and system for dynamic power management of memories: A method and apparatus for dynamic power management of memories. In one embodiment of the invention, the power consumption of the memories is reduced based on the operating state of the memories. For example, in one embodiment of the invention, the power supply to the memories is reduced when the... Agent:
20120243365 - Semiconductor memory device and method of setting operation environment therein: A semiconductor memory device comprises: a memory cell array including a plurality of memory cells; an internal circuit having a function required in a storage operation of the memory cell array; a parameter storage unit configured to store a certain parameter and to have a storage place specified by a... Agent: Kabushiki Kaisha Toshiba09/20/2012 > 59 patent applications in 34 patent subcategories. class, title,number
20120236618 - Semiconductor memory device and operating method thereof: A semiconductor memory device includes a memory array configured to include memory cells for storing input data and Code Address Memory (CAM) cells for storing setting data used to set an operation condition; an operation circuit configured to perform a CAM read operation by supplying a read voltage to the... Agent: Hynix Semiconductor Inc.
20120236620 - Nonvolatile memory device and manufacturing method thereof: The present invention relates to a nonvolatile memory device and a manufacturing method thereof, the device comprising a plurality of word lines; a plurality of bit lines perpendicular to the word lines; and a plurality of memory cells including a transistor with a source connected to a source line, a... Agent:
20120236621 - Semiconductor device: A semiconductor device including a memory cell is provided. The memory cell comprises a transistor and a capacitor, and one of a resistor and a diode. A gate of the transistor is electrically connected to a word line, and one of a source and a drain of the transistor is... Agent: Semiconductor Energy Laboratory Co., Ltd.
20120236619 - Semiconductor memory device: According to one embodiment, a semiconductor memory device includes a memory array and a peripheral circuit. The memory array has a plurality of memory cells, word lines, and bit lines, in which a first, second, and third blocks are set in the order along the bit line. The peripheral circuit... Agent: Kabushiki Kaisha Toshiba
20120236622 - Non-volatile graphene-drum memory chip: The present invention relates to non-volatile memory chips having graphene drums. In some embodiments, the non-volatile memory chips have one or more layers that each includes a plurality of graphene-drum memory chip cells.... Agent:
20120236624 - Balanced method for programming multi-layer cell memories: Improved methods for programming multi-level metal oxide memory cells balance applied voltage and current to provide improved performance. Set programming, which transitions the memory cell to a lower resistance state, is accomplished by determining an appropriate programming voltage and current limit for the objective resistance state to be achieved in... Agent: Sandisk 3d LLC
20120236626 - Memory cell: The object of the present invention is a non-volatile memory cell (10) containing at least two distinct memory zones (17), each formed in a resistivity-change material (14), the memory cell (10) containing at least one heating element (16) for each memory zone (17), each heating element (16) having at least... Agent: Commissariat A L'energie Atomique Et Aux Ene Alt
20120236625 - Memory element and memory device: There are provided a memory element and a memory device with improved writing and erasing characteristics during operations at a low voltage and a low current. The memory element includes a first electrode, a memory layer, and a second electrode in this order. The memory layer includes a resistance change... Agent: Sony Corporation
20120236627 - Multi-level memory devices and methods of operating the same: The present invention provides a multi-level memory device and method of operating the same. The device comprises a memory structure in which a distribution density of resistance levels around its minimum value is higher than that around its maximum value.... Agent: Samsung Electronics Co., Ltd.
20120236623 - Sensing resistive states: A memory device capable of being sensed with an oscillating signal includes a first terminal of a memristive element connected to an oscillating signal supply, and a second terminal of the memristive element connected to sensing circuitry, the sensing circuitry to determine an attenuation of an oscillating signal from the... Agent:
20120236628 - Variable resistance nonvolatile memory device: In a nonvolatile memory device, basic array planes (0 to 3) have respective first via groups (121 to 124) that interconnect only even-layer bit lines in the basic array planes, and respective second via groups (131 to 134) that interconnect only odd-layer bit lines in the basic array planes, the... Agent:
20120236630 - Bypass capacitor circuit and method of providing a bypass capacitance for an integrated circuit die: A bypass capacitor circuit for an integrated circuit (IC) comprises one or more capacitive devices, each arranged in a segment of a seal ring area of a die, which comprises the IC. A method of providing a bypass capacitance for an IC comprises providing a semiconductor wafer device comprising a... Agent: Freescale Semiconductor, Inc.
20120236629 - Multi-level dram cell using chc technology: A DRAM memory cell includes: a first finFET structure; and a second finFET structure adjacent to the first finFET structure. The second finFET structure includes: a source follower transistor in a first fin of the second finFET structure; an access transistor in a second fin of the second fin FET... Agent:
20120236632 - Data storage methods and devices: A data storage method includes writing data to a ferromagnetic shape-memory material in its ferromagnetic state, the material exhibiting more than two stable states. A data storage device includes a non-volatile memory element containing a ferromagnetic shape-memory alloy in a martensite state, the shape-memory alloy being ferromagnetic in a plurality... Agent:
20120236631 - Magnetic tunneling junction devices, memories, electronic systems, and memory systems, and methods of fabricating the same: Provided is a magnetic tunneling junction device including a fixed magnetic structure; a free magnetic structure; and a tunnel barrier between the fixed magnetic structure and the free magnetic structure, at least one of the fixed magnetic structure and the free magnetic structure including a perpendicular magnetization preserving layer, a... Agent: Samsung Electronics Co., Ltd.
20120236633 - Magnetic recording element and nonvolatile memory device: According to one embodiment, a magnetic recording element includes a stacked body. The stacked body includes a first and a second stacked unit. The first stacked unit includes first and second ferromagnetic layers and a first nonmagnetic layer. The first nonmagnetic layer is provided between the first and second ferromagnetic... Agent: Kabushiki Kaisha Toshiba
20120236634 - Memory device and electronic device: A selection operation is performed for individual memory cells. A device includes a first memory cell and a second memory cell provided in the same row as the first memory cell, each of which includes a field-effect transistor having a first gate and a second gate. The field-effect transistor controls... Agent: Semiconductor Energy Laboratory Co., Ltd.
20120236640 - Reducing effects of erase disturb in a memory device: A method for programming includes initially biasing a subset of a plurality of control gates of a string of memory cells with a negative voltage, wherein the subset is less than all of the plurality of control gates of the string. The control gate of a selected memory cell is... Agent: Micron Technology, Inc.
20120236639 - Reduction of read disturb errors in nand flash memory: Methods and apparatuses for reduction of Read Disturb errors in a NAND FLASH memory system utilizing modified or extra FLASH memory cells.... Agent: Texas Memory Systems, Inc.
20120236641 - Asymmetric log-likelihood ratio for mlc flash channel: Disclosed is an system and method for reading a flash memory cell with an adjusted read level. A current read level is adjusted to a new read level associated with increasing a first error rate to decrease a second error rate. The first error rate is associated with determining that... Agent: Stec, Inc. A California Corporation
20120236642 - Integrated circuit self aligned 3d memory array and manufacturing method: A 3D memory device includes a plurality of ridge-shaped stacks, in the form of multiple strips of conductive material separated by insulating material, arranged as bit lines which can be coupled through decoding circuits to sense amplifiers. The strips of conductive material have side surfaces on the sides of the... Agent: Macronix International Co., Ltd.
20120236635 - Logic-based multiple time programming memory cell: A non-volatile memory system includes one or more non-volatile memory cells. Each non-volatile memory cell comprises a floating gate, a coupling device, a first floating gate transistor, and a second floating gate transistor. The coupling device is located in a first conductivity region. The first floating gate transistor is located... Agent:
20120236643 - Interleaved flash storage system and method: A flash storage system accesses data interleaved among flash storage devices. The flash storage system receives a data block including data portions, stores the data portions in a data buffer, and initiates data transfers for asynchronously writing the data portions into storage blocks interleaved among the flash storage devices. Additionally,... Agent: Stec, Inc.
20120236645 - Semiconductor memory device: A semiconductor memory device includes a memory cell array having a plurality of memory cells arranged in a shape of a matrix along a plurality of parallel bit lines and a plurality of word lines intersecting orthogonally to the bit lines, and that have their data read out to the... Agent: Kabushiki Kaisha Toshiba
20120236644 - Semiconductor storage device: A semiconductor storage device according to an embodiment includes: a memory cell array including plural word lines, plural bit lines, and plural memory cells each of which is selected by the word line and the bit line, the memory cell array being divided into plural blocks, some of the word... Agent: Kabushiki Kaisha Toshiba
20120236646 - Non-volatile memory cell: The non-volatile memory cell includes a coupling device and a first select transistor. The coupling device is formed in a first conductivity region. The first select transistor is serially connected to a first floating gate transistor and a second select transistor, all formed in a second conductivity region. An electrode... Agent:
20120236647 - Hierarchical common source line structure in nand flash memory: Each memory cell string in a generic NAND flash cell block connects to a Common Source Line (CLS). A value for applying to the CSL is centrally generated and distributed to a local switch logic unit corresponding to each NAND flash cell block. For source-line page programming, the distribution line... Agent:
20120236648 - Electrically addressed non-volatile memory maintentance: An electrically addressed non-volatile memory is maintained by measuring a voltage threshold for each selected memory cell in the electrically addressed non-volatile memory. The voltage threshold is a voltage around which a controllable voltage signal applied to a control gate of a selected memory cell produces a change in value... Agent:
20120236649 - Hot carrier programming of nand flash memory: A NAND memory device includes strings of NAND memory cells, where each memory cell includes a charge trapping structure formed over a lightly-doped substrate region. A selected one of the NAND memory cells can be programmed by application of a relatively low program voltage in combination with a previously-applied set-up... Agent: Macronix International Co., Ltd.
20120236650 - Nand archtecture including resitive memory cells: A non-volatile memory device includes a first select transistor, a second select transistor, and a first string of first memory cells provided between the first and second select transistors. Each first memory cell has a first resistive memory cell and a first transistor. The first resistive memory cell is in... Agent: Crossbar, Inc.
20120236652 - Nonvolatile semiconductor memory device and method for manufacturing the same: According to one embodiment, a nonvolatile semiconductor memory device includes a first memory string including a first memory cell and a second memory cell aligned along a first axis, a source contact provided at a source-side end of the first memory string, a second memory string that extends along the... Agent: Kabushiki Kaisha Toshiba
20120236651 - System and method for determining data dependent noise calculation for a flash channel: Disclosed is an system and method for determining a probability that a memory cell was programmed to a certain input level. An output level is received from a memory cell and a probability is determined that the output level corresponds to each of a plurality of programming levels. Each probability... Agent: Stec, Inc.
20120236654 - Programming non-volatile memory with variable initial programming pulse: Multiple programming processes are performed for a plurality of non-volatile storage elements. Each of the programming process operates to program at least a subset of the non-volatile storage elements to a set of target conditions using programming pulses. For at least a subset of the programming processes, a programming pulse... Agent:
20120236653 - Self-check calibration of program or erase and verify process using memory cell distribution: Subject matter disclosed herein relates to a memory device, and more particularly to write or erase performance of a memory device.... Agent: Micron Technology, Inc.
20120236636 - Non-volatile semiconductor storage device: A non-volatile semiconductor storage device according to an embodiment includes a memory cell array and a control circuit configured to execute a read operation. The control circuit refers to data of a reference memory cell which is adjacent to a selected memory cell and in which data is written after... Agent: Kabushiki Kaisha Toshiba
20120236637 - Non-volatile semiconductor storage device: A non-volatile semiconductor storage device according to one embodiment includes a memory cell array that has NAND cell units in which a plurality of memory cells are connected in series, the control gate of each of the plurality of memory cells being connected to a word line, and a control... Agent: Kabushiki Kaisha Toshiba
20120236638 - Obtaining soft information using a hard interface: A flash memory controller, a computer readable medium and a method for generating reliability information using a hard information interface, the method may include performing multiple read attempts, while using the hard information interface, of a plurality of flash memory cells to provide multiple read results; wherein each flash memory... Agent: Densbits Technologies Ltd.
20120236655 - Reference voltage optimization for flash memory: A system includes a voltage generator and a reference voltage setting module. The voltage generator is configured to generate K voltages to be applied to memory cells. The K voltages are used to determine a reference voltage used to read the memory cells, where K is an integer greater than... Agent:
20120236656 - Apparatus and method for determining a read level of a memory cell based on cycle information: Disclosed is an apparatus and method for determining a read level voltage to apply to a block of memory cells in a non-volatile memory circuit. A prediction value is compared to a prediction indicator to determine whether a new read level voltage to be applied to read the memory cells... Agent: Stec, Inc.
20120236657 - Non-volatile semiconductor memory device adapted to store a multi-valued data in a single memory cell: A non-volatile semiconductor memory device includes an electrically data rewritable non-volatile semiconductor memory cell and a write circuit for writing data in the memory cell, the write circuit writing a data in the memory cells by supplying a write voltage Vpgm and a write control voltage VBL to the memory... Agent: Kabushiki Kaisha Toshiba
20120236658 - Systems and methods for refreshing non-volatile memory: Systems and methods are disclosed for managing a non-volatile memory (“NVM”), such as a flash memory. To prevent data errors due to leakage effects, the NVM may be refreshed. For example, a reserved portion of the NVM may be selected, and a predetermined pattern can be stored into the reserved... Agent: Apple Inc.
20120236659 - Staggered mode transitions in a segmented interface: A memory integrated circuit comprises first and second memory arrays and first and second interfaces. The first interface receives a signal for accessing a memory location in one of the first and the second memory arrays during a first time interval. The second interface receives a signal for accessing a... Agent: Rambus Inc.
20120236660 - Test system and test method for memory: The test system for memory includes a controlling device, an address generating device, a data disturbing device and a comparing device. The controlling device is used for writing a first data into a memory. The address generating device is used for generating a plurality of first addresses and a plurality... Agent: Nanya Technology Corp.
20120236661 - Semiconductor storage device: According to one embodiment, when a row address of a port A matches a row address of a port B, a memory cell is accessed only from the port A by controlling a word line potential of the port A based on a third clock, and data is exchanged between... Agent: Kabushiki Kaisha Toshiba
20120236662 - Word-line-potential control circuit: According to one embodiment, in a memory cell array, a plurality of memory cells is arranged in an array. A read circuit reads out data from the memory cells. A word line driver drives a word line of the memory cells. A characteristic control unit controls a specific characteristic of... Agent: Kabushiki Kaisha Toshiba
20120236663 - Program cycle skip: A non-volatile storage system includes technology for skipping programming cycles while programming a page (or other unit) of data. While programming a current subset of the page (or other unit) of data, the system will evaluate whether the next subsets of the page (or other unit) of data should be... Agent:
20120236664 - Semiconductor memory device: According to one embodiment, there is provided a semiconductor memory device including a memory cell array, a plurality of signal lines, and a plurality of signal-line-lead-out portions. In the memory cell array, a plurality of memory cells are arranged. The plurality of signal lines connected to the plurality of memory... Agent: Kabushiki Kaisha Toshiba
20120236665 - Semiconductor memory device, method of controlling read preamble signal thereof, and data transmission system: A semiconductor memory device, includes a data terminal provided to transfer a data therethrough, a strobe terminal provided to be related in the data terminal and to transfer a strobe signal therethrough a command terminal provided to receive a command that communicates the data with an outside thereof, and a... Agent: Elpida Memory, Inc.
20120236666 - Semiconductor memory device, method of controlling read preamble signal thereof, and data transmission system: A system, includes a controller comprising a plurality of first external terminals configured to supply a command and an address, and communicate a data, and communicate a strobe signal related to the data; and a semiconductor memory device including a plurality of second external terminals corresponding to the plurality of... Agent: Elpida Memory, Inc.
20120236667 - Semiconductor memory device, method of controlling read preamble signal thereof, and data transmission system: A semiconductor memory device, includes a clock terminal provided to receive a clock signal, a data terminal provided to transfer a data therethrough in synchronization with the clock signal, a strobe terminal provided to be related in the data terminal and to transfer a strobe signal therethrough, a command terminal... Agent: Elpida Memory, Inc.
20120236668 - Memory module with discrete heating element: A memory module includes multiple memory devices mounted to a substrate and one or more discrete heating elements disposed in thermal contact with the memory devices. Each of the memory devices includes charge-storing memory cells subject to operation-induced defects that degrade ability of the memory cells to store data. The... Agent:
20120236669 - Semiconductor device having compensation capacitance: Disclosed herein is a device that includes: first and second memory mats each including a plurality of bit lines; a sense area arranged between the first and second memory mats; a column selection line provided on the first memory mat; and a compensation capacitance provided on the second memory mat.... Agent: Elpida Memory, Inc.
20120236670 - Non-volatile storage with temperature compensation based on neighbor state information: Data is programmed into and read from a set of target memory cells. When reading the data, temperature compensation is provided. The temperature compensation is based on temperature information and the state of one or more neighbor memory cells. In one embodiment, when data is read from set of target... Agent:
20120236671 - Refreshing data of memory cells with electrically floating body transistors: A semiconductor device along with circuits including the same and methods of operating the same are described. The device comprises a memory cell including one transistor. The transistor comprises a gate, an electrically floating body region, and a source region and a drain region adjacent the body region. Data stored... Agent: Micron Technology, Inc.
20120236674 - Circuit and method for operating a circuit: A circuit and method for operating a circuit is provided that includes a circuit section that has a number of memory elements, a first voltage regulator that can be connected or is connected to the circuit section in order to operate the circuit section, a second voltage regulator that can... Agent:
20120236672 - High voltage generating circuit and method of operating the same: A high voltage generating circuit includes first and second high voltage pump circuits and an oscillator. The oscillator is configured to output a first clock signal driving the first high voltage pump circuit and a second clock signal driving the second high voltage pump circuit. The oscillator includes a first... Agent: Samsung Electronics Co., Ltd.
20120236673 - Semiconductor device: Disclosed herein a device that includes a memory cell array including plurality of word lines, a plurality of bit lines each intersecting the word lines and a plurality of memory cells each disposed at an associated one of intersections of the word and bit lines, and the device further includes... Agent: Elpida Memory, Inc.
20120236675 - Methods and apparatus for memory word line driver: A word line driver circuit and corresponding methods are disclosed. An apparatus, comprising a decoder circuit coupled to receive address inputs, and having a decoder output; and a word line clock gating circuit coupled to the decoder output and to a word line clock signal, configured to selectively output a... Agent: Taiwan Semiconductor Manufacturing Company, Ltd.
20120236676 - Single transistor driver for address lines in a phase change memory and switch (pcms) array: The present disclosure relates to the fabrication of non-volatile memory devices. In at least one embodiment, a single transistor may be used to drive each address line, either a wordline or a bitline. Both an inhibit voltage and a selection voltage may be driven through these single transistor devices, which... Agent:09/13/2012 > 67 patent applications in 35 patent subcategories. class, title,number
20120230078 - Storage circuit: A storage circuit includes a volatile storage portion in which storage of a data signal is controlled by a clock signal and an inverted clock signal, and a nonvolatile storage portion in which a data signal supplied to the volatile storage portion can be held even after supply of power... Agent: Semiconductor Energy Laboratory Co., Ltd.
20120230079 - Actuator and storage device: In one embodiment, an actuator has a movable member, a frame, and first and second electrodes. Each of the first electrodes has a pair of first and second planes perpendicular to a third direction which is orthogonal to the first and the second directions approximately. The second electrodes are provided... Agent: Kabushiki Kaisha Toshiba
20120230084 - Apparatus for variable resistive memory punchthrough access method: Variable resistive punchthrough access methods are described. The methods include switching a variable resistive data cell from a high resistance state to a low resistance state by passing a write current through the magnetic tunnel junction data cell in a first direction. The write current is provided by a transistor... Agent: Seagate Technology LLC
20120230081 - Cell-state measurement in resistive memory: Apparatus and method for measuring the state of a resistive memory cell. A bias voltage controller applies a bias voltage to the cell and controls the level of the bias voltage. A feedback signal generator senses cell current due to the bias voltage and generates a feedback signal (SFB) dependent... Agent: International Business Machines Corporation
20120230085 - Forming method of performing forming on variable resistance nonvolatile memory element, and variable resistance nonvolatile memory device: In forming, an automatic forming circuit (210) included in a nonvolatile memory device (200) causes a constant current IL to flow in a selected memory cell having a considerably high initial resistance. When the forming generates a filament path in the memory cell and thereby a resistance value is decreased,... Agent:
20120230082 - Nonvolatile semiconductor memory device and method of resetting the same: A nonvolatile semiconductor memory device includes: a plurality of memory cell arrays stacked on a semiconductor substrate and including a plurality of first wires, a plurality of second wires and memory cells disposed at intersections of the first wires and the second wires and having a rectifier element and a... Agent: Kabushiki Kaisha Toshiba
20120230083 - Semiconductor memory device: A semiconductor memory device comprising: a memory cell array in which memory cells each containing a variable resistive element and a rectifier element connected in series are arranged at intersections of a plurality of first wirings and a plurality of second wirings; and a control circuit for selectively driving said... Agent: Kabushiki Kaisha Toshiba
20120230080 - Variable resistance device, semiconductor device including the variable resistance device, and method of operating the semiconductor device: According to an example embodiment, a method of operating a semiconductor device includes applying a first voltage to the variable resistance device so as to change a resistance value of the variable resistance device from a first resistance value to a second resistance value that is different from the first... Agent: Samsung Electronics Co., Ltd.
20120230088 - 8t sram cell with one word line: An integrated circuit with SRAM cells containing dual passgate transistors and a read buffer, all connected to one word line is disclosed. The read buffer and one passgate transistor may be variously configured to a separate read data line and write data line, or a combined data line, in different... Agent: Texas Instruments Incorporated
20120230087 - Sram circuits for circuit identification using a digital fingerprint: Circuitry that includes static random access memory (SRAM) access circuitry and a group of SRAM memory cells is disclosed. A digital fingerprint of the group of SRAM memory cells is determined by using the SRAM access circuitry to force at least a portion of the group of SRAM memory cells... Agent: Arizona Technology Enterprises, LLC
20120230086 - Static random access memory cell and method of operating the same: A static random access memory cell includes a latch unit. The latch unit includes a bi-inverting circuit and a switching circuit. The bi-inverting circuit has a first terminal and a second terminal. The switching circuit is electrically connected between the first terminal and the second terminal, wherein when the switching... Agent: National Chiao Tung University
20120230094 - Bit line charge accumulation sensing for resistive changing memory: A memory array includes a plurality of magneto-resistive changing memory cells. Each resistive changing memory cell is electrically between a source line and a bit line and a transistor electrically between the resistive changing memory cell and the bit line. The transistor has a gate electrically between a source region... Agent: Seagate Technology LLC
20120230091 - Magnetic memory: According to one embodiment, a magnetic memory includes at least one memory cell including a magnetoresistive element, and first and second electrodes. The element includes a first magnetic layer, a tunnel barrier layer, a second magnetic layer, and a third magnetic layer provided on the second magnetic layer and having... Agent:
20120230089 - Magnetoresistance element and non-volatile semiconductor storage device using same magnetoresistance element: A magnetoresistance element is disclosed. The magnetoresistance element includes a magnetic tunnel junction portion configured by sequentially stacking a perpendicularly magnetized first magnetic body, an insulation layer, and a perpendicularly magnetized second magnetic body. The second magnetic body has a configuration wherein a ferromagnetic layer and a rare earth-transition metal... Agent: Fuji Electric Co., Ltd.
20120230095 - Non-volatile magnetic memory element with graded layer: A non-volatile magnetic memory element includes a number of layers one of which is a free layer which is graded. The graded free layer may include various elements with each element having a different anisotropy or it may include nonmagnetic compounds and magnetic regions with the non-magnetic compounds forming graded... Agent: Avalanche Technology, Inc.
20120230090 - Semiconductor memory: A semiconductor memory has a first switch circuit and a second switch circuit. The semiconductor memory has a row decoder that controls a voltage of a word line. The semiconductor memory has a first writing circuit including a first signal terminal connected to one end of the first switch circuit... Agent: Kabushiki Kaisha Toshiba
20120230092 - Thermally assisted multi-bit mram: Methods of writing to a multi-bit MRAM memory unit are described. The method includes to self-detected writing to a multi-bit (i.e., multilevel) thermally assisted MRAM. The self-detected writing increases a reading margin between data state levels and decreases reading margin variability due to cell resistance variation.... Agent: Seagate Technology LLC
20120230093 - Transmission gate-based spin-transfer torque memory unit: A transmission gate-based spin-transfer torque memory unit is described. The memory unit includes a magnetic tunnel junction data cell electrically coupled to a bit line and a source line. A NMOS transistor is in parallel electrical connection with a PMOS transistor and they are electrically connected with the source line... Agent: Seagate Technology LLC
20120230097 - Determining cell-state in phase-change memory: A method, an apparatus, and a device for determining the state of a phase-change memory cell. The method includes the steps of: biasing a cell with a time-varying read voltage (Vread); making a measurement (TM) that satisfies a predetermined condition where the predetermined condition depends on a cell current when... Agent: International Business Machines Corporation
20120230096 - Devices and methods to program a memory cell: Subject matter disclosed herein relates to memory devices and, more particularly, to programming a memory cell.... Agent: Micron Technology, Inc.
20120230099 - Phase change memory: A phase change memory with an operating current that can be gradually increased or gradually decreased. The phase change memory has a phase change storage element, a transistor, and a control circuit. The transistor is operable to adjust the operating current flowing through the phase change storage element. The transistor... Agent: Higgs Opl. Capitol LLC
20120230100 - Programmable phase-change memory and method therefor: A non-volatile memory is disclosed. A contiguous layer of phase change material is provided. Proximate the contiguous layer of phase change material is provided a first pair of contacts for providing an electrical current therebetween, the electrical current for passing through the contiguous layer of phase change material for inducing... Agent:
20120230098 - Programming of phase-change memory cells: A method and apparatus for programming a phase-change memory cell. A bias voltage signal (VBL) is applied to the cell. A measurement portion (m) of this bias voltage signal has a profile which varies with time. A measurement (TM), which is dependent on a predetermined condition being satisfied, is then... Agent: International Business Machines Corporation
20120230101 - Method and apparatus for writing to a magnetic tunnel junction (mtj) by applying incrementally increasing voltage level: A method of writing to magnetic tunnel junctions (MTJs) of a magnetic memory array includes storing in-coming data in a cache register, reading the present logic state of a first one of a set of at least two MTJs, the set of at least two MTJs including the first MTJ... Agent: Avalanche Technology, Inc.
20120230102 - Flash memory storage apparatus: A flash memory storage apparatus is provided. The flash memory storage apparatus includes a substrate, a control and storage circuit unit, a ground lead, at least a signal lead, and a power lead. The control and storage circuit unit, the power lead, the signal lead, and the ground lead are... Agent: Phison Electronics Corp.
20120230104 - Non-volatile memory device and read method thereof: Disclosed is a non-volatile memory device which includes a memory cell array having memory cells arranged in rows and columns, a page buffer circuit configured to read data from the memory cell array, and a control logic and input/output interface block including a normal read scheduler controlling a normal read... Agent:
20120230105 - Semiconductor integrated circuit: In one embodiment, a semiconductor integrated circuit has memory cells. Each of the memory cells has non-volatile memories and switching elements. The non-volatile memories and switching elements are connected in series between a first power source and a second power source. Output wirings of at least two of the memory... Agent:
20120230107 - Semiconductor memory device having memory block configuration: A semiconductor device includes a semiconductor substrate having first and second edge lines, address pads along the first edge line, and memory mats, each including normal memory blocks and a spare memory block. Each normal memory block has nonvolatile memory cells and is a unit of batch erase. The memory... Agent: Renesas Electronics Corporation
20120230106 - Semiconductor memory devices, reading program and method for memory devices: A semiconductor memory device, having a memory array which has two memory banks which can be accessed simultaneously is provided. A word line selection circuit selects the word line according to the row address information, and a controller controls the word line selection circuit according to the received instruction. The... Agent:
20120230111 - Level shifting circuit: A level shifting circuit having an input and an output where the level shifting circuit is configured to receive a logical high level having a first voltage level at the input and to output a logical high level having a second voltage level at the output where the second voltage... Agent: Micron Technology, Inc.
20120230108 - Memory device with multiple planes: Disclosed herein is a device that comprises at least one selection/non-selection voltage receiving line, at least one word line operatively coupled to the selection/non-selection voltage receiving line, and a plurality of memory cells coupled to the word line; a selection voltage source line; and a selection voltage supply circuit comprising... Agent: Elpida Memory, Inc.
20120230110 - Method and apparatus for addressing memory arrays: The present description relates to non-volatile memory arrays and the operation thereof In at least one embodiment, the non-volatile memory array may include a plurality of memory modules coupled in a daisy chain with enable in/out signals, and a single chip enable signal coupled in parallel to each memory module.... Agent:
20120230109 - Method of setting trim codes for a flash memory and related device: A flash memory device with auto-trimming functionality includes a memory cell array comprising first memory cells and a fuse sector, a read circuit for reading a memory state of the first memory cells, an offset circuit for outputting offset current values, and an auto-trimming circuit. The auto-trimming circuit has a... Agent:
20120230112 - Nonvolatile memory device, driving method thereof, and memory system having the same: A nonvolatile memory device (NVM), memory system and apparatus include control logic configured to perform a method of applying negative voltage on a selected wordline of the NVM. During a first time a first high voltage level is applied to the channel of a transistor of a address decoder and... Agent:
20120230113 - Random telegraph signal noise reduction scheme for semiconductor memories: Embodiments are provided that include a method including providing a first pulsed gate signal to a selected memory cell, wherein the pulsed gate signal alternates between a first voltage level and a second voltage level during a time period and sensing a data line response to determine data stored on... Agent: Micron Technology, Inc.
20120230103 - Nonvolatile memory device and operating method thereof: According to example embodiments, a nonvolatile memory device includes a substrate, at least one string extending vertically from the substrate, and a bit line current controlling circuit connected to the at least one string via at least one bit line. The at least one string may include a channel containing... Agent: Samsung Electronics Co., Ltd.
20120230115 - High-speed verifiable semiconductor memory device: A memory cell stores several data using n (n: natural number more than 1) threshold voltages. A voltage supply circuit supplies a predetermined voltage to a gate of the memory cell in a verify operation of verifying whether or not the memory cell reaches a predetermined threshold voltage. A detection... Agent:
20120230114 - Semiconductor device and method of driving semiconductor device: An object is to provide a semiconductor device to reduce variation in the threshold voltages of memory cells after writing, reduce the operation voltage, or increase the storage capacity. The semiconductor device includes memory cells each including a transistor including an oxide semiconductor, a driver circuit that drives the memory... Agent: Semiconductor Energy Laboratory Co., Ltd.
20120230116 - Sense operation in a stacked memory array device: Methods for sensing and memory devices are disclosed. One such method for sensing includes changing a sense condition of a particular layer responsive to a programming rate of that particular layer (e.g., relative to other layers).... Agent: Micron Technology, Inc.
20120230118 - Non-volatile memory cell having a heating element and a substrate-based control gate: The number of times that a non-volatile memory (NVM) can be programmed and erased is substantially increased by utilizing a localized heating element that anneals the oxide that is damaged by tunneling charge carriers when the NVM is programmed and erased. The program and erase voltages are also reduced when... Agent: Texas Instruments Incorporated
20120230117 - Nonvolatile semicondcutor memory device: According to one embodiment, a nonvolatile semiconductor memory device includes semiconductor regions provided on a substrate and electrically separated from each other, a memory cell block provided in each of the semiconductor regions and includes nonvolatile memory cells, word lines connected to control gates of memory transistors so as to... Agent: Kabushiki Kaisha Toshiba
20120230120 - Nonvolatile semiconductor memory device and erasing method of nonvolatile semiconductor memory device: A nonvolatile semiconductor memory device including a first bit line commonly coupling drain sides memory cells; a word line commonly coupling control gates of memory cell transistors; a column decoder coupled to a second bit line; a row decoder coupled to a word line; a first transistor having a source... Agent: Fujitsu Semiconductor Limited
20120230119 - Word line driver in flash memory: A memory device of the non-volatile type including a memory array having a plurality of memory cells organized as sectors, each sector having a main word line associated with a plurality of local word lines, each local word line coupled to the main word line by a respective local word... Agent: Mosaid Technologies Incorporated
20120230128 - Integrated circuitry, switches, and methods of selecting memory cells of a memory device: Some embodiments include switches that have a graphene structure connected to a pair of spaced-apart electrodes. The switches may further include first and second electrically conductive structures on opposing sides of the graphene structure from one another. The first structure may extend from one of the electrodes, and the second... Agent: Micron Technology, Inc.
20120230130 - Memory cell system and method: A memory cell system/method incorporating reduced transistor counts and/or improved design-for-manufacturability (DFM) is disclosed. The system/method incorporates cross-coupled feedthru (3410)/feedback (3420) amplifiers to implement memory cell state memory, wherein the feedback amplifier incorporates a multi-state output drive capability (3423) allowing the memory cell to be read/written using only one access... Agent:
20120230129 - Method of altering distribution of a chosen characteristic of a plurality of memory cells forming a memory device: A method is provided for altering distribution of a chosen characteristic of a plurality of memory cells forming a memory device. The method comprises identifying a subset of the memory cells whose value of the chosen characteristic is within a predetermined end region of the distribution, and then performing a... Agent: Arm Limited
20120230121 - Data bus power-reduced semiconductor storage apparatus: In one or more of the disclosed embodiments, the number of times toggle operations of a data bus are performed at the time of a data transmission in a semiconductor storage apparatus is reduced, thereby reducing the power consumption. For example, a semiconductor storage apparatus according to one embodiment of... Agent: Micron Technoloy, Inc.
20120230122 - Memory device and method of controlling a write operation within a memory device: A memory device and method are provided incorporating a technique for controlling a write operation within the memory device. The memory device has an array of memory cells, each memory cell supporting writing and simultaneous reading of that memory cell. Write circuitry is arranged, during a write operation, to provide... Agent: Arm Limited
20120230123 - Method of maintaining the state of semiconductor memory having electrically floating body transistor: Methods of maintaining a state of a memory cell without interrupting access to the memory cell are provided, including applying a back bias to the cell to offset charge leakage out of a floating body of the cell, wherein a charge level of the floating body indicates a state of... Agent:
20120230124 - Latch system applied to a plurality of banks of a memory circuit: A latch system applied to a plurality of banks of a memory circuit includes a front latch circuit and a plurality of rear latch circuit. The front latch circuit is used for receiving a datum and a front latch enabling signal, and generating and outputting an intermediate signal according to... Agent:
20120230125 - Semiconductor memory device and methods thereof: According to example embodiments, a semiconductor memory device includes a memory cell array, a multi-purpose register, a data output circuit, and a mode register. The memory cell array is configured to store data. The multi-purpose register is configured to store a data pattern. The data output circuit is configured to... Agent: Samsung Electronics Co., Ltd.
20120230126 - Memory voltage regulator with leakage current voltage control: A voltage regulator for a memory that regulates a voltage provided to the memory cells based on a measured leakage current from a second set of memory cells. In one embodiment, based on the measured leakage current, the voltage to the cells is raised or lowered to control the amount... Agent:
20120230127 - Providing row redundancy to solve vertical twin bit failures: A circuit includes a failure address register configured to store a first row address, a row address modifier coupled to the failure address register, wherein the row address modifier is configured to modify the first row address received from the failure address register to generate a second row address. A... Agent: Taiwan Semiconductor Manufacturing Company, Ltd.
20120230132 - Data processing device and method of reading trimming data: A data processing device including a nonvolatile memory comprising a plurality of memory regions in which a same trimming data is stored, and a trimming data read control circuit configured to read the trimming data from a random memory region. The trimming data read control circuit comprises a region selection... Agent: Renesas Electronics Corporation
20120230131 - Semiconductor storage device: According to one embodiment, a semiconductor storage device includes cells, and a sense amplifier. Each of the cells is connected to a bit line. The sense amplifier reads out data. The sense amplifier includes a first transistor to third transistor, and a switch. The first transistor has one end of... Agent: Kabushiki Kaisha Toshiba
20120230133 - Nonvolatile semiconductor memory device and data writing method: A nonvolatile semiconductor memory quickly and precisely accumulates a desired amount of charges corresponding to data-to-be-written in a charge accumulating part of a memory cell. When charges are injected into the charge accumulating part of the memory cell by applying a writing voltage corresponding to the data-to-be-written to the drain... Agent: Lapis Semiconductor Co., Ltd.
20120230134 - Dram sense amplifier that supports low memory-cell capacitance: The disclosed embodiments provide a sense amplifier for a dynamic random-access memory (DRAM). This sense amplifier includes a bit line to be coupled to a cell to be sensed in the DRAM, and a complement bit line which carries a complement of a signal on the bit line. The sense... Agent: Rambus Inc.
20120230135 - Delay locked loop circuit and method: Delay locked loop circuits and methods are disclosed. In the embodiments, a delay locked loop may include a phase detector to detect a phase difference between a clock signal and a reference clock signal, and a charge pump that receives the detected phase difference. A low pass filter may filter... Agent:
20120230136 - Selectable repair pass masking: The present invention relates to a method and circuit for selectively repairing an embedded memory module having memory elements in an integrated circuit chip. The method comprises performing a plurality of tests on the embedded memory module under operating conditions to identify a plurality of non-operational memory elements in the... Agent: International Business Machines Corporation
20120230137 - Memory device and test method for the same: A memory device includes a first bank, a second bank, a plurality of interface pads, and a data output unit configured to output compressed data of the first bank through at least one interface pad among the plurality of interface pads and subsequently output compressed data of the second bank... Agent:
20120230138 - Memory element and signal processing circuit: A memory element having a novel structure and a signal processing circuit including the memory element are provided. A first circuit, including a first transistor and a second transistor, and a second circuit, including a third transistor and a fourth transistor, are included. A first signal potential and a second... Agent: Semiconductor Energy Laboratory Co., Ltd.
20120230139 - Semiconductor memory device having a hierarchical bit line scheme: A semiconductor memory device including a bit line connected to a memory cell and a sense amplifier configured to drive a voltage level of a global bit line in response to a voltage level of the bit line. The sense amplifier provides data that is complementary to data stored in... Agent:
20120230140 - Maintenance of amplified signals using high-voltage-threshold transistors: Systems, apparatus, memory devices, sense amplifiers and methods are provided, such as a system that includes an input node, a first transistor having a gate that couples to the input node, and a second transistor having another gate that couples to the input node. In one or more embodiments, the... Agent: Micron Technology, Inc.
20120230141 - Semiconductor device and data processing system: Disclosed herein is a semiconductor device comprising local bit lines, a global bit line, local switch control lines, main switch control lines, hierarchical switches controlling electrical connections between the local bit lines and the global bit line in response to potentials of the local switch control lines, local switch drivers... Agent: Elpida Memory, Inc.
20120230142 - Table lookup voltage compensation for memory cells: Systems and methods of regulating voltage at a memory cell are disclosed. An address for the memory cell is determined. Table lookups based on the address are performed. The table lookups yield voltage compensation parameters that can be used to set voltages on the terminals (e.g., source and drain) of... Agent:
20120230143 - Static memory with segmented clear: Described embodiments provide a static memory system with multiple memory cell that, in response to a reset signal, simultaneously resets or clears a segment of the memory cells in the memory. Clearing the entire memory or a portion thereof is accomplished by sequencing though a subset of address bits while... Agent: Lsi Corporation
20120230144 - Semiconductor device: A device includes a first clock generation circuit that receives an external clock signal supplied to the device, delays the external clock signal to output a first clock signal synchronized with the external clock signal, and a circuit that generates a control signal to control output of data, based on... Agent: Elpida Memory, Inc.09/06/2012 > 45 patent applications in 29 patent subcategories. class, title,number
20120224404 - Enhanced programming and erasure schemes for analog memory cells: A method for data storage includes setting a group of analog memory cells to respective analog values by performing an iterative process that applies a sequence of pulses to the memory cells in the group. During the iterative process, a progress of the iterative process is assessed, and a parameter... Agent: Anobit Technologies Ltd.
20120224405 - Semiconductor device: A semiconductor device with a memory unit of which the variations in the operation timing are reduced is provided. For example, the semiconductor device is provided with dummy bit lines which are arranged collaterally with a proper bit line, and column direction load circuits which are sequentially coupled to the... Agent: Renesas Electronics Corporation
20120224406 - Circuit and system of using junction diode as program selector for one-time programmable devices: Junction diodes fabricated in standard CMOS logic processes can be used as program selectors for One-Time Programmable (OTP) devices, such as electrical fuse, contact/via fuse, contact/via anti-fuse, or gate-oxide breakdown anti-fuse, etc. The OTP device has at least one OTP element coupled to at least one diode in a memory... Agent:
20120224407 - Integrated circuit having a clock deskew circuit that includes an injection-locked oscillator: Methods and apparatuses featuring an injection-locked oscillator (ILO) are described. In some embodiments, an ILO can have multiple injection points and a free-running frequency that is capable of being adjusted based on a control signal. In some embodiments, each injection point of an ILO can correspond to a phase tuning... Agent: Rambus Inc.
20120224411 - Non-volatile semiconductor storage device and forming method: According to one embodiment, a control unit multiple-selects a first line for every N lines from a plurality of first lines. N is an integer greater than or equal to one. The control unit sets the multiple-selected first lines to a selection potential, and fixes potentials of non-selected first lines... Agent: Kabushiki Kaisha Toshiba
20120224413 - Non-volatile storage system using opposite polarity programming signals for mim memory cell: A reversible resistance-switching metal-insulator-metal (MIM) stack is provided which can be set to a low resistance state with a first polarity signal and reset to a higher resistance state with a second polarity signal. The first polarity signal is opposite in polarity than the second polarity signal. In one approach,... Agent:
20120224412 - Semiconductor storage device and test method thereof: A memory includes memory cells each storing data according to a change in a resistance state, and reference cells referred to in order to detect data stored in the memory cells. Sense amplifiers compare reference data in the reference cells with data in the memory cells to detect the data... Agent: Kabushiki Kaisha Toshiba
20120224408 - Three dimensional memory system with column pipeline: A monolithic three dimensional array of non-volatile storage elements is arranged in blocks. The non-volatile storage elements are connected to bit lines and word lines. The bit lines for each block are grouped into columns of bit lines. The columns of bit lines include top columns of bit lines that... Agent:
20120224410 - Three dimensional memory system with intelligent select circuit: A three dimensional monolithic memory array of non-volatile storage elements includes a plurality of word lines and a plurality of bit lines. The plurality of bit lines are grouped into columns. Performing memory operation on the non-volatile storage elements includes selectively connecting bit lines to sense amplifiers using selection circuits... Agent:
20120224409 - Three dimensional memory system with page of data across word lines: A three dimensional monolithic memory array of non-volatile storage elements includes a plurality of word lines and a plurality of bit lines. The plurality of bit lines are grouped into columns. One page of data is stored across multiple word lines by programming non-volatile storage elements connected to one column... Agent:
20120224414 - Solid-state memory cell with improved read stability: MOS transistors connected in parallel, and receiving complementary isolation control signals. In read cycles, or in unselected columns during write cycles, the isolation gate is turned off slightly before the word line is energized, and turned on at or after the word line is de-energized. By isolating the input of... Agent: Texas Instruments Incorporated
20120224415 - Transistor with reduced charge carrier mobility and associated methods: One or more embodiments of the invention relate to a method comprising: treating a fin of a first n-channel access transistor in a static random access memory cell to have a lower charge carrier mobility than a fin of a first n-channel pull-down transistor in a first inverter in the... Agent:
20120224417 - Diode assisted switching spin-transfer torque memory unit: A memory array includes a cross-point array of bit and source lines. A memory is disposed at cross-points of the cross-point array. The memory unit includes a magnetic tunnel junction data cell electrically coupled to a bit line and a source line. The magnetic tunnel junction data cell is configured... Agent: Seagate Technology LLC
20120224416 - Magnetic memory and magnetic memory apparatus: A magnetic memory includes a first magnetic layer, a second magnetic layer, a third magnetic layer, a first intermediate layer, a second intermediate layer, an insulator film, and an electrode. The third magnetic layer is provided between the first magnetic layer and the second magnetic layer in a first direction... Agent: Kabushiki Kaisha Toshiba
20120224418 - Multi-bit memory with selectable magnetic layer: An apparatus and associated method for a multi-bit memory capable of being selected with a magnetic layer. Various embodiments of the present invention are generally directed to a first selection layer with a low coercivity that is disposed between first and second storage layers that each have a high coercivity.... Agent: Seagate Technology LLC
20120224419 - Semiconductor storage device: A semiconductor storage device according to an embodiment includes wells in a semiconductor substrate, fins formed on the wells, gate electrodes provided on one side and another opposite side of each fin via a gate insulating film to form a channel region in the fin, impurity-diffused layers that each form... Agent: Kabushiki Kaisha Toshiba
20120224422 - Nonvolatile semiconductor memory device: A memory cell array has a first and a second storage area. The first storage area has a memory elements selected by an address signal. The second storage area has a memory elements selected by a control signal. A control circuit has a fuse element. When the fuse element has... Agent: Kabushiki Kaisha Toshiba
20120224423 - Programming and erasure schemes for analog memory cells: A method for data storage, in a memory that includes multiple analog memory cells, includes setting a parameter of an iterative process applied to a group of the memory cells based on one or more data values stored in at least one of the memory cells in the memory. The... Agent: Anobit Technologies Ltd.
20120224420 - Semiconductor memory device and decoding method: A memory card decodes three bits of data stored in one memory cell and belonging to different pages, each being a unit of reading, by iterative calculation using probability based on eight threshold voltage distributions. The memory card includes a word line controlling section configured to select one required to... Agent: Kabushiki Kaisha Toshiba
20120224421 - System and method of decoding data from memory based on sensing information and decoded data of neighboring storage elements: Systems and methods to decode data stored in a data storage device are disclosed. Data bits stored in a first group of storage elements are decoded using data in a second group of storage elements together with physical characteristics of the second group of storage elements to aid in the... Agent: Sandisk Technologies Inc.
20120224424 - Nonvolatile memory device, method for fabricating the same, and method for operating the same: A nonvolatile memory device includes bit and source lines alternately arranged parallel to each other and even strings and odd strings alternately arranged between the bit lines and the source lines and each including drain selection transistors, memory transistors, and a source selection transistor. The drain selection transistors include a... Agent:
20120224425 - Using temperature sensors with a memory device: In one implementation, a method for performing memory operations includes receiving, at a memory device, a request to read data from one or more non-volatile memory cells; and retrieving stored temperature information associated with the non-volatile memory cells, wherein the temperature information is associated with a temperature at approximately at... Agent: Apple Inc.
20120224426 - Nonvolatile memory device and read method thereof: According to example embodiments, a read method of a nonvolatile memory device includes Disclosed is a read method of a nonvolatile memory device which includes selecting one of a plurality of vertical strings in a nonvolatile memory device, judging a channel length between a common source line and a selected... Agent:
20120224427 - Nonvolatile semiconductor memory device: According to an embodiment, a block dividing unit groups l word lines into p groups, to divide a block into p divisional blocks. An erasing unit has an erasing operation performed on data stored in memory cells in a memory cell array, on a divisional block basis. An erasing verifying... Agent: Kabushiki Kaisha Toshiba
20120224428 - Charge pump operation in a non-volatile memory device: A charge pump in a memory device is activated to produce a programming voltage prior to data loading during a programming operation. During an initial programming cycle, first and second load voltages are charged from the charge pump. The first load is removed from the charge pump during a verify... Agent: Micron Technology, Inc.
20120224429 - Methods for programming a memory device and memory devices: Methods for programming memory cells and memory devices are disclosed. One such method for programming includes performing a program verify operation of a group of memory cells. A number of potential CS2 situations are detected. If the number of detected potential CS2 situations is greater than a threshold, programming compensation... Agent: Micron Technology, Inc.
20120224431 - Programming and/or erasing a memory device in response to its program and/or erase history: For one embodiment, a programming method includes programming one or more memory cells of a memory device during a programming operation, determining, internal to the memory device, a number of program pulses required to program a sample of the one or more memory cells of the memory device during the... Agent: Micron Technology, Inc.
20120224430 - Reading memory cell history during program operation for adaptive programming: Subject matter disclosed herein relates to a memory device, and more particularly to write performance of a memory device.... Agent: Micron Technology, Inc.
20120224432 - Over-erase verification and repair methods for flash memory: Over-erase verification and repair methods for a flash memory. The flash memory is an NOR type stack flash. The disclosed method performs an over-erased column verification test on a sector of the NOR type stack flash column by column. An over-erased column repair process is individually performed on the columns... Agent:
20120224434 - Interleaving charge pumps for programmable memories: Systems and methods, including computer software for performing operations enable interleaving of charging operations in a charging pump. A first charge pump is charged to a predetermined level, and a first operation is performed using a charge stored in the first charge pump after it reaches the predetermined level. A... Agent: Apple Inc., A California Corporation
20120224433 - Semiconductor device and production method thereof: A semiconductor device includes a differential circuit and a power supply circuit that provides a power supply to the differential circuit. Current to be supplied to the differential circuit by the power supply circuit is controlled, based on logics of a burn-in mode signal and an activation control signal for... Agent: Elpida Memory, Inc.
20120224438 - Semiconductor memory device: According to one embodiment, a fin formed on a semiconductor substrate, a gate electrode provided on both sides of the fin via a gate dielectric film, a depletion layer that forms a potential barrier, which confines a hole in a body region between channel regions of the fin, in the... Agent: Kabushiki Kaisha Toshiba
20120224435 - Multiple-port memory device comprising single-port memory device with supporting control circuitry: A multiple-port memory device having at least first and second ports each configured to support read and write operations. The multiple-port memory device further comprises a single-port memory device and control circuitry coupled between the first and second ports and the single-port memory device. The control circuitry is configured to... Agent:
20120224436 - Setting a reference voltage in a memory controller trained to a memory device: Systems and methods to set a voltage value associated with a memory controller coupled to a memory device are disclosed. A particular method includes comparing test data of a test path to functional data of a functional path. The functional data may be generated based on device data received at... Agent:
20120224437 - Non-volatile memory device using variable resistance element with an improved write performance: A non-volatile memory device using a variable resistive element is provided. The non-volatile memory device includes a memory cell array having a plurality of non-volatile memory cells, a first voltage generator configured to generate a first voltage, a voltage pad configured to receive an external voltage that has a level... Agent:
20120224439 - Mask-write apparatus for a sram cell: Disclosed herein is a device that comprises a SRAM cell, a pair of bit-lines coupled with the SRAM cell, a writing circuit producing at first and second output nodes thereof true and complementary data signals responsive to data to be written, a first pass transistor coupled between one of the... Agent: Elpida Memory, Inc.
20120224440 - Memory device and method of writing data to a memory device: In a memory device, a bitline write voltage is applied to a first bitline. A wordline voltage is applied to a first wordline for writing data to a first memory cell connected to the first wordline and the first bitline. The first bitline and the second bitline are electrically connected... Agent: Stmicroelectronics Pvt Ltd (india)
20120224441 - Semiconductor memory apparatus: Various embodiments of a semiconductor memory apparatus are disclosed. In one exemplary embodiment, a semiconductor memory apparatus may include a page size control unit configured to generate first and second block enable signals having a level corresponding to one of a plurality of row selection signals or one of a... Agent: Hynix Semiconductor Inc.
20120224442 - Circuit with remote amplifier: A circuit comprises a first driver, a second driver, and a remote sense amplifier. The first driver is configured to generate a first data signal on a first data line. The second driver is configured to generate a control signal on a control signal line. An RC delay of the... Agent: Taiwan Semiconductor Manufacturing Company, Ltd.
20120224443 - Sense amplifier with shielding circuit: A sense amplifier includes a first transistor, a second transistor, an output circuit, and a shielding circuit. The first transistor has a gate bias established by a cell current, and the second transistor has a gate bias established by a reference current. The output circuit is coupled to the first... Agent: Macronix International Co., Ltd.
20120224444 - Methods of operating dram devices having adjustable internal refresh cycles that vary in response to on-chip temperature changes: An integrated circuit memory device includes a refresh control circuit that generates an internal memory refresh command signal having a period that is changed relative to a period of an external memory refresh command signal received by the memory device. This change in the period of the internal memory refresh... Agent:
20120224445 - Apparatus and method to measure energy capacity of a backup power supply without compromising power delivery: A device includes a backup power supply configured to provide power to an external system upon loss of primary system power. The backup power provided by at least one capacitor. While the capacitor is available as a backup power supply to the external system, a transient elevation of the capacitor's... Agent: Agiga Tech Inc.
20120224446 - Capacitor charge balance system: “A circuit includes a series arrangement of capacitor stages, each stage including a single capacitor or a plurality of capacitors in parallel, the series arrangement configured such that each capacitor stage receives charge current via a common charging terminal. A controller is configured to separately measure a stored potential of... Agent: Agiga Tech Inc.
20120224447 - Semiconductor memory device having selective activation circuit for selectively activating circuit areas: A semiconductor memory device includes a plurality of memory banks each including a plurality of circuit areas selected based on an address signal, any one of which is selected by a corresponding bank selective signal (source transistor control signals), and a selective activation circuit that, from among circuit areas included... Agent: Elpida Memory, Inc.
20120224448 - Delay efficient gater repeater: A gater repeater circuit is disclosed. In one embodiment, the circuit includes an activation circuit coupled to receive an input signal and a clock signal and configured to activate an output circuit. The output circuit is configured to drive an output signal. The output circuit includes first and second devices... Agent:Previous industry: Electric power conversion systems
Next industry: Agitating
RSS FEED for 20141002:
Integrate FreshPatents.com into your RSS reader/aggregator or website to track weekly updates.
For more info, read this article.
Thank you for viewing Static information storage and retrieval patents on the FreshPatents.com website. These are patent applications which have been filed in the United States. There are a variety ways to browse Static information storage and retrieval patent applications on our website including browsing by date, agent, inventor, and industry. If you are interested in receiving occasional emails regarding Static information storage and retrieval patents we recommend signing up for free keyword monitoring by email.
Results in 1.80421 seconds