|Static information storage and retrieval patents - Monitor Patents|
USPTO Class 365 | Browse by Industry: Previous - Next | All
08/2012 | Recent | 14: Jul | Jun | May | Apr | Mar | Feb | Jan | 13: Dec | Nov | Oct | Sep | Aug | Jul | Jun | May | Apr | Mar | Feb | Jan | 12: Dec | Nov | Oct | Sep | Aug | July | June | May | April | Mar | Feb | Jan | 11: Dec | Nov | Oct | Sep | Aug | Jul | Jun | May | Apr | Mar | Feb | Jan | 10: Dec | Nov | Oct | Sep | Aug | Jul | Jun | May | Apr | Mar | Feb | Jan | | 09: Dec | Nov | Oct | Sep | Aug | Jl | Jn | May | Apr | Mar | Fb | Jn | | 2008 | 2007 |
Static information storage and retrieval August inventions list 08/12Below are recently published patent applications awaiting approval from the USPTO. Recent week's RSS XML file available below.
Listing for abstract view: USPTO application #, Title, Abstract excerpt,Patent Agent. Listing format for list view: USPTO National Class full category number, title of the patent application. 08/30/2012 > 49 patent applications in 32 patent subcategories. inventions list
20120218802 - Content addressable memory: One embodiment provides a content addressable memory, including: a pair of spin MOSFETs including: a first spin MOSFET whose magnetization state is set in accordance with stored data; and a second spin MOSFET whose magnetization state is set in accordance with the stored data, the second spin MOSFET being connected... Agent:
20120218804 - Magnetic memory device: The present invention provides a magnetic memory device capable of providing high-speed access without increasing an array area. Gate word lines are respectively linearly disposed between source impurity regions and drain impurity regions within a memory cell array area. Gate word line protrusions are respectively provided at boundary regions of... Agent: Renesas Electronics Corporation
20120218803 - Memeory device interface methods, apparatus, and systems: Apparatus and systems may include an interface chip, a first memory die having at least one memory array disposed on the interface chip, and a second memory die having at least one memory array disposed on the first memory die. The first memory die can include a plurality of vias... Agent:
20120218805 - Configurable memory array: Embodiments disclosed include a memory array having a plurality of bit lines and a plurality of source lines disposed in columns. A plurality of word lines is disposed in rows. A plurality of storage elements have a first subset of storage elements electrically decoupled from the memory array and a... Agent: Qualcomm Incorporated
20120218806 - Memory cells, methods of forming memory cells, and methods of programming memory cells: Some embodiments include methods in which a memory cell is formed to have programmable material between first and second access lines, with the programmable material having two compositionally different regions. A concentration of ions and/or ion-vacancies may be altered in at least one of the regions to change a memory... Agent: Micron Technology, Inc.
20120218808 - Memory element and memory device: There are provided a memory element and a memory device with improved repetition characteristics during operations at a low voltage and current. The memory element includes a first electrode, a memory layer, and a second electrode in this order. The memory layer includes a resistance change layer disposed on the... Agent: Sony Corporation
20120218810 - Methods of reading and using memory cells: Some embodiments include methods of reading memory cells. The memory cells have a write operation that occurs only if a voltage of sufficient absolute value is applied for a sufficient duration of time; and the reading is conducted with a pulse that is of too short of a time duration... Agent: Micron Technology, Inc.
20120218807 - Resistive memory sensing methods and devices: The present disclosure includes resistive memory sensing methods and devices. One such method includes performing a voltage based multiple pass sensing operation on a group of cells coupled to a selected conductive line of an array of resistive memory cells. The voltage based multiple pass sensing operation can include providing... Agent: Micron Technology, Inc.
20120218809 - Storage apparatus and operation method for operating the same: A storage apparatus includes: a plurality of storage elements configured to have the resistance state thereof changed in accordance with an applied voltage; and a drive portion configured to perform a resistance change operation and a read operation, the resistance change operation involving writing or erasing information to or from... Agent: Sony Corporation
20120218811 - Circuit: An object of the current invention is to provide DRAM that is not limited by capacitors.... Agent:
20120218812 - Semiconductor device: A semiconductor device having an SRAM macro which has a power-off function and facilitates a design associated with a change in storage capacity is provided. The semiconductor device has plural layout units each including a memory array having plural memory cells in an SRAM, a first peripheral circuit that writes... Agent: Hitachi, Ltd.
20120218813 - Magnetic memory devices: Magnetic memory devices are provided, the devices include at least memory cell and a reference cell on a substrate. The memory cells include a first base magnetic layer, a free layer, and a first tunnel barrier layer between the first base magnetic layer and free layer. The reference memory cell... Agent: Samsung Electronics Co., Ltd.
20120218814 - Write bandwidth in a memory characterized by a variable write time: A memory system that includes a plurality of memory arrays having memory cells characterized by a variable write time. The memory system also includes a memory bus configured to receive write commands, and a plurality of data buffers configured to communicate with the memory arrays. The memory system further includes... Agent: International Business Machines Corporation
20120218815 - Magnetic random access memory (mram) read with reduced disburb failure: Magnetic tunnel junctions (MTJs) in magnetic random access memory (MRAM) are subject to read disturb events when the current passing through the MTJ causes a spontaneous switching of the MTJ due to spin transfer torque (STT) from a parallel state to an anti-parallel state or from an anti-parallel state to... Agent: Qualcomm Incorporated
20120218816 - Non-volatile memory devices: A non-volatile memory device may include a semiconductor substrate including an active region at a surface thereof, a ground select line crossing the active region, and a string select line crossing the active region and spaced apart from the ground select line. A plurality of memory cell word lines may... Agent:
20120218818 - Nonvolatile memory device and method for operating the same: A nonvolatile memory device includes a page region including a plurality of normal cells and a plurality of auxiliary cells, a detecting unit configured to output a pass signal when at least one cell is programmed with a voltage higher than a reference voltage among program target cells of the... Agent:
20120218821 - Non-volatile semiconductor storage device: A non-volatile semiconductor storage device includes: a memory string including a plurality of memory cells connected in series; a first selection transistor having one end connected to one end of the memory string; a first wiring having one end connected to the other end of the first selection transistor; a... Agent: Kabushiki Kaisha Toshiba
20120218819 - Nonvolatile semiconductor memory: Disclosed is a nonvolatile memory system including at least one nonvolatile memory each having a plurality of nonvolatile memory cells and a buffer memory; and a control device coupled to the nonvolatile memory. The control device is enabled to receive external data and to apply the data to the nonvolatile... Agent:
20120218820 - Three dimensional stacked nonvolatile semiconductor memory: A three dimensional stacked nonvolatile semiconductor memory according to examples of the present invention includes a memory cell array comprised of first and second blocks disposed side by side and a driver disposed between the first and second blocks. At least two conductive layers having the same structure as that... Agent:
20120218822 - Content addressable memory: NAND architecture non-volatile content addressable (CAM) memory devices and methods are described that allows for high density, low cost CAM devices. In addition, the NAND architecture non-volatile CAM memory operates with reduced power consumption characteristics for low power and portable applications. In one NAND architecture non-volatile CAM memory embodiment a... Agent: Micron Technology, Inc.
20120218824 - Independent well bias management in a memory device: Methods for programming a memory device, memory devices configured to perform the disclosed programming methods, and memory systems having a memory device configured to perform the disclosed programming methods, for example, are provided. According to at least one such method, multiple independent semiconductor well regions each having strings of memory... Agent: Micron Technology, Inc.
20120218823 - Voltage generation and adjustment in a memory device: Voltage generation devices and methods are useful in determining a data state of a selected memory cell in a memory device. Voltages applied to an access line coupled to a selected memory cell can be determined at least partially in response to a sensed operating characteristic of the memory device,... Agent: Micron Technology, Inc.
20120218825 - Wordline voltage transfer apparatus, systems, and methods: The apparatus and systems described herein may comprise a plurality of memory cells coupled to a local wordline, and a wordline drive circuit that includes a regulator coupled to a plurality of pass transistors and a string driver. The regulator may comprise a regulator transistor having a threshold voltage that... Agent:
20120218826 - Non-volatile memory device and program method thereof: A non-volatile memory device and a program method thereof are disclosed. The non-volatile memory device includes a page buffer section connected to the bit lines further connected to memory cells and where the page buffer section is for controlling a potential of the bit lines in response to control signals,... Agent: Hynix Semiconductor Inc.
20120218817 - Nonvolatile memory device, memory system including the same, and method of operating nonvolatile memory device: A non-volatile memory device includes a non-volatile memory cell array including a plurality of word lines, a voltage generator configured to generate a first high-voltage using a supply voltage and a second high-voltage using an external voltage which is higher than the supply voltage, and a word line selection circuit... Agent: Samsung Electronics Co., Ltd.
20120218827 - Memory apparatus and method for controlling erase operation of the same: An erase operation of a memory apparatus is controlled by, inter alia, selecting one or more memory cell blocks to be erased among a plurality of memory cell blocks, performing an erase operation on the selected one or more memory cell blocks in response to an erase command, performing a... Agent: Hynix Semiconductor Inc.
20120218828 - Methods for programming nonvolatile memory devices: Provided is a method for programming a nonvolatile memory device. The nonvolatile memory device includes a local word line to divide a memory cell string into a first area including a selected word line and a second area not including the selected word line. In the method, word lines of... Agent: Samsung Electronics Co., Ltd.
20120218829 - Nand flash architecture with multi-level row decoding: A NAND flash memory device is disclosed. The NAND flash memory device includes a NAND flash memory array defined as a plurality of sectors. Row decoding is performed in two levels. The first level is performed that is applicable to all of the sectors. This can be used to select... Agent: Mosaid Technologies Incorporated
20120218836 - Semiconductor memory device: According to one embodiment, a semiconductor memory device comprises a first silicon pillar including a first pair of columnar portions and a first connection portion, a second silicon pillar including a second pair of columnar portions and a second connection portion in the shunt region, the second silicon pillar being... Agent:
20120218837 - Voltage regulator: A voltage regulator may include an input terminal for receiving an input voltage and an output terminal for providing a respective output voltage, a regulation transistor having a first conduction terminal coupled to the input terminal for receiving the input voltage, a second conduction terminal coupled to the output terminal,... Agent: Stmicroelectronics S.r.l.
20120218830 - Method and system for reading from memory cells in a memory device: A method and a system for reading from memory cells in a memory device are provided. In one embodiment, the memory device comprises a first plurality of data lines and a second plurality of data lines, at least one first multiplexer coupled to the first plurality of data lines and... Agent: Infineon Technologies Ag
20120218832 - Data transmission circuit: A data transmission circuit includes: a driving voltage generation unit configured to generate a driving voltage having a lower level than an external driving voltage; a switch unit configured to transmit the driving voltage when any one of a write enable signal and a read enable signal is enabled; and... Agent: Hynix Semiconductor Inc.
20120218831 - Integrated circuit for storing information: An integrated circuit includes a variable resistance unit including at least one transistor that receives a control signal and changes a resistance through the transistor in response to the control signal in a programming operation mode and an information detection unit configured to detect programming information in response to an... Agent:
20120218833 - Leakage measurement systems: Described examples include leakage measurement systems and methods for measuring leakage current between a word line at a boosted voltage and a word line at a supply voltage. The boosted voltage may be generated by charge pump circuitry. Examples of leakage measurement systems described herein may be included in memory... Agent: Micron Technology, Inc.
20120218834 - Semiconductor memory device and method for operating the same: A semiconductor memory device includes a signal processing unit configured to generate a control signal corresponding to burst length information and an output controlling unit configured to control an output of a data strobe signal in response to the control signal.... Agent:
20120218835 - Semiconductor apparatus with open bit line structure: A semiconductor apparatus with an open bit line structure includes a memory bank including a plurality of memory cell blocks and dummy mats, in which a plurality of bit lines are formed, a bit line sense amplifier configured to be arranged between the plurality of memory cell blocks and the... Agent: Hynix Semiconductor Inc.
20120218838 - Semiconductor memory device: A semiconductor memory device includes a read circuit configured to sequentially output a plurality of compressed data corresponding to all banks which are to be tested in response to a plurality of bank addresses and a read enable signal during a test mode and a pad configured to transfer the... Agent:
20120218839 - Data interface circuit, nonvolatile memory device including the same and operating method thereof: A data interface unit is used in a semiconductor memory device and includes a data alignment unit configured to separate consecutive input data into rising data and falling data, and a data transfer unit configured to selectively transfer the rising data and falling data to an even column line and... Agent:
20120218840 - Integrated circuit: An integrated circuit includes a plurality of data lines on which data aligned by a plurality of pulse signals are loaded, a plurality of transfer lines, a data transfer unit configured to transfer the data of the plurality of data lines to the plurality of transfer lines in response to... Agent:
20120218842 - Semiconductor memory device, method of controlling read preamble signal thereof, and data transmission system: A controller, includes a plurality of external terminals configured to supply a command and an address to a semiconductor memory device, communicate a data with the semiconductor memory device, and communicate a strobe signal related to the data, at least one external terminal among the plurality of external terminals being... Agent: Elpida Memory, Inc.
20120218841 - Utilizing two algorithms to determine a delay value for training ddr3 memory: A method for training an electronic memory may include receiving a first delay value and a second delay value. The first delay value and the second delay value may be associated with a first data strobe indicating when to sample data on a first memory lane of the electronic memory.... Agent: Lsi Corporation
20120218844 - Memory controller, system including the controller, and memory delay amount control method: A memory controller coupled to a DRAM includes a delay control section including a delay holding section, and coupled to the DRAM to output a delay set value to the DRAM and a delay adjustment section coupled to the DRAM to receive data from the DRAM, and to arrange a... Agent: Renesas Electronics Corporation
20120218843 - Semiconductor device: Provided is a semiconductor device which performs a refresh operation by sequentially counting a refresh address including a main word line address, a mat address, and a sub word line address in order of the main word line address, the mat address, and the sub word line address. The semiconductor... Agent: Hynix Semiconductor Inc.
20120218845 - Semiconductor device and control method thereof: Disclosed herein is a semiconductor device comprising an array having a hierarchical bit line structure, global bit lines adjacent to each other, local bit lines corresponding to the global bit lines, hierarchical switches, precharge circuits precharging the global bit lines, precharge circuits precharging the local bit lines, and a control... Agent: Elpida Memory Inc.
20120218846 - Test circuit, semiconductor memory apparatus using the same, and test method of the semiconductor memory apparatus: A test circuit of a semiconductor memory apparatus includes: a test control signal generating unit configured to enable a control signal if an active signal is enabled after a test signal is enabled, and substantially maintain the control signal in an enable state until a precharge timing signal is enabled;... Agent: Sk Hynix Inc.
20120218847 - Techniques for reducing disturbance in a semiconductor memory device: Techniques for reducing disturbance in a semiconductor memory device are disclosed. In one particular exemplary embodiment, the techniques may be realized as a semiconductor memory device having reduced disturbance. The semiconductor memory device may comprise a plurality of memory cells arranged in arrays of rows and columns. The semiconductor memory... Agent: Micron Technology, Inc.
20120218848 - Semiconductor memory device for controlling operation of delay-locked loop circuit: A semiconductor memory device for controlling an operation of a delay-locked loop (DLL) circuit is provided. The semiconductor memory device includes a DLL circuit that receives an external clock signal and that performs a locking operation on the external clock signal and an internal clock signal, thereby obtaining a locked... Agent:
20120218850 - Non-volatile memory device and memory system including the same: A non-volatile memory device and a read method thereof are disclosed. The read method includes providing a memory block having memory cells connected to word lines and connected in serial to a bit line, sensing potential of the bit line by applying a first read voltage to a selected word... Agent: Hynix Semiconductor Inc.
20120218849 - Semiconductor memory apparatus: A semiconductor memory apparatus includes a memory cell array including a plurality of chips, a control circuit configured to control an internal operation of the memory cell array, a power circuit configured to supply power to the control circuit, and a mode setting circuit configured to output a flag signal... Agent: Hynix Semiconductor Inc.08/23/2012 > 41 patent applications in 30 patent subcategories. inventions list
20120212989 - Memory core and semiconductor memory device including the same: A semiconductor memory device is disclosed. The semiconductor memory device includes a memory array block, a first word line and a second word line. The memory array block includes a plurality of adjacent columns of memory cells, each column of memory cells including a plurality of consecutive memory cells having... Agent:
20120212988 - Semiconductor device: According to an embodiment, a semiconductor device includes a substrate, a connector, a volatile semiconductor memory element, multiple nonvolatile semiconductor memory elements, and a controller. A wiring pattern includes a signal line that is formed between the connector and the controller and that connects the connector to the controller. On... Agent: Kabushiki Kaisha Toshiba
20120212990 - Semiconductor apparatus: A semiconductor apparatus includes a multi-chip module which multi-chip module comprises a first and a second chips. The semiconductor apparatus comprises a first data line in the first chip to carry first read data; a first controller, in the first chip, configured to generate first output data on a first... Agent: Hynix Semiconductor Inc.
20120212991 - Semiconductor device and operation method thereof: An operation method of a semiconductor device, includes providing one or more memory elements each including a first semiconductor layer of a first conductivity type, second and third semiconductor layers of a second conductivity type, which are disposed to be separated from each other in the first semiconductor layer, a... Agent: Sony Corporation
20120212992 - Semiconductor device and operation method thereof: An operation method of a semiconductor device, includes providing one or more memory elements each including a first semiconductor layer, second and third semiconductor layers, a dielectric film and a conductive film, a first electrode, a second electrode, and a third electrode, and performing operation of writing information on a... Agent: Sony Corporation
20120212993 - One time programming bit cell: A one time programming (OTP) memory cell includes a first transistor and a second transistor. The first transistor has a first drain, a first source, a first gate, and a first normal operational voltage value higher that a second normal operational voltage value of the second transistor. The second transistor... Agent: Taiwan Semiconductor Manufacturing Company, Ltd.
20120212994 - Memory apparatus: A memory apparatus includes: a plurality of memory cells which includes a first resistance change element; and a read-out circuit which determines the size of a resistance value of the first resistance change element by comparing the resistance state of a memory cell selected among the plurality of memory cells... Agent: Sony Corporation
20120212995 - Programmable lsi: A low-power programmable LSI that can perform configuration (dynamic configuration) at high speed and can quickly start is provided. The programmable LSI includes a plurality of logic elements and a memory element for storing configuration data to be input to the plurality of logic elements. The plurality of logic elements... Agent: Semiconductor Energy Laboratory Co., Ltd.
20120212996 - Memory device having memory cells with write assist functionality: A memory device includes a memory array comprising a plurality of memory cells. At least a given one of the memory cells comprises a pair of cross-coupled inverters and associated write assist circuitry. The write assist circuitry comprises first switching circuitry coupled between a supply node of a device of... Agent:
20120212997 - Test structure for characterizing multi-port static random access memory and register file arrays: A test structure for characterizing a production static random access memory (SRAM) array. The test structure includes a characterization circuit having multiple memory cell columns connected in series to form a ring configuration. The characterization circuit is fabricated on a wafer substrate in common with and proximate to a production... Agent: International Business Machines Corporation
20120212998 - Non-volatile perpendicular magnetic memory with low switching current and high thermal stability: A non-volatile current-switching magnetic memory element includes a bottom electrode, a pinning layer formed on top of the bottom electrode, and a fixed layer formed on top of the pinning layer. The non-volatile current-switching magnetic memory element further includes a tunnel layer formed on top of the pinning layer, a... Agent: Avalanche Technology, Inc.
20120212999 - Methods of forming programmed memory cells: In some embodiments, a memory cell includes a transistor gate spaced from a channel region by gate dielectric; a source region on one side of the channel region; and a drain region on an opposing side of the channel region from the source region. The channel region has phase change... Agent: Micron Technology Inc.
20120213000 - Semiconductor memory device and method of manufacturing semiconductor memory device: A highly integrated gain cell-type semiconductor memory is provided. A first insulator, a read bit line, a second insulator, a third insulator, a first semiconductor film, first conductive layers, and the like are formed. A projecting insulator is formed thereover. Then, second semiconductor films and a second gate insulating film... Agent: Semiconductor Energy Laboratory Co., Ltd.
20120213002 - Semiconductor memory device having faulty cells: In response to a read command received by a system interface unit for accessing a plurality of blocks of data stored in said non-volatile semiconductor memory, a controller carries out selective read operations of blocks of data to two memories from the non-volatile semiconductor memory. The controller also carries out... Agent:
20120213003 - Non-volatile memory device and related read method: A nonvolatile memory device comprises a memory cell array, a page buffer, and a bit line connection signal controller. The memory cell array comprises a plurality of word lines and bit lines arranged in rows and columns, and a plurality of memory cells connected to the respective word lines and... Agent: Samsung Electronics Co., Ltd.
20120213004 - Non-volatile memory device and related read method: A nonvolatile memory device comprises a memory cell array and a voltage generator. The memory cell array comprises a plurality of memory cells connected in series between a string selection transistor connected to a bit line and a ground selection transistor connected to a source line. The voltage generator provides... Agent: Samsung Electronics Co., Ltd.
20120213005 - Non-volatile memory device, memory controller, and methods thereof: The method includes receiving a block address and an erase command output from a controller, and changing, until an erase operation performed according to the erase command on a block corresponding to the block address is completed, a parameter value related to the erase operation. The method further includes storing... Agent: Samsung Electronics Co., Ltd.
20120213006 - Semiconductor storage device and manufacturing method of semiconductor storage device: A semiconductor storage device according to an embodiment comprises a memory cell string in which a plurality of memory cells each having a gate are serially connected to each other. A selective transistor is connected to an end memory cell at an end of the memory cell string. A sidewall... Agent: Kabushiki Kaisha Toshiba
20120213007 - Controlling a non-volatile memory: Controlling a non-volatile memory. The non-volatile memory includes a plurality of memory cells in an integrated circuit substrate. The non-volatile memory also includes a high-voltage node in power-transmissive communication with the plurality of memory cells. Further, the non-volatile memory includes an intermediate-voltage node in power-transmissive communication with the plurality of... Agent: Synopsys Inc.
20120213001 - Reliability metrics management for soft decoding: Embodiments provide a method for reading a target memory sector of a memory. The method comprises, based on read data corresponding to a plurality of memory sectors of the memory, estimating first one or more reference voltages and, using the first one or more reference voltages, performing a first read... Agent:
20120213008 - Nonvolatile memory device and program verify method thereof: A program verify method of the nonvolatile memory device includes supplying a first program verify voltage to a word line coupled to memory cells of a memory cell array, sensing a voltage of a bit line coupled to the memory cells in response to a first sense signal, supplying a... Agent: Hynix Semiconductor Inc.
20120213009 - Nonvolatile memory device and operating method thereof: A nonvolatile memory device includes a channel vertically extending from a substrate, a plurality of memory cells stacked along the channel; a source region connected to a first end portion of the channel, and a bit line connected to a second end portion of the channel, wherein the first end... Agent:
20120213013 - Memory building blocks and memory design using automatic design tools: The memory building blocks can be used in conjunction with ASIC automatic design tools to generate a memory macro (e.g., a memory array) using a known ASIC design flow including, for example, register transfer level (RTL), synthesis, automatic place and route (APR) and timing analysis.... Agent: Taiwan Semiconductor Manufacturing Company, Ltd.
20120213010 - Asymmetric sense amplifier design: A circuit includes a first inverter including a first PMOS transistor and a first NMOS transistor, and a second inverter including a second PMOS transistor and a second NMOS transistor. A first node is connected to gates of the first PMOS transistor and the first NMOS transistor and drains of... Agent: Taiwan Semiconductor Manufacturing Company, Ltd.
20120213011 - Semiconductor memory apparatus: A semiconductor memory apparatus includes: a data output signal transmitter configured to receive a data signal and a data mask signal and transmit a data output signal through a global data line, the data output signal being outputted by determining whether the data signal is masked or not; and a... Agent: Hynix Semiconductor Inc.
20120213012 - Strobe apparatus, systems, and methods: A strobe signal is received in a device and execution of an operation in the device is delayed when the strobe signal includes a preamble. Additional apparatus, systems, and methods are disclosed.... Agent:
20120213014 - Write control circuit and semiconductor device: In a semiconductor device and a write control circuit, a voltage detection unit detects a write voltage supplied to a storage element (electrical fuse element) in which only single writing is electrically performed and, when the write voltage is equal to or more than a predetermined threshold voltage, allows the... Agent: Fujitsu Semiconductor Limited
20120213017 - Apparatus and methods for communicating with programmable devices: A circuit arrangement includes a programmable logic device. The programmable logic device includes configuration logic circuitry. The programmable logic device also includes configurable interconnects. The circuit arrangement further includes a storage device configured to provide data to the programmable logic device. The storage device communicates with the programmable logic device... Agent: Altera Corporation
20120213018 - Device and method generating internal voltage in semiconductor memory device: A semiconductor memory device and a method of generating an internal voltage in the semiconductor memory device are provided. The semiconductor memory device includes a controller configured to activate a sensing enable signal when an active command is applied from outside, inactivate the sensing enable signal when a precharge command... Agent: Samsung Electronics Co., Ltd.
20120213016 - Semiconductor memory device: At a succeeding stage of a sense amplifier, a first data latch is provided which has the same bit number as the page length and is controlled to invariably hold the same data as that of the sense amplifier. When a column address strobe (CAS) access begins, data is transferred... Agent: Panasonic Corporation
20120213015 - Sense amplifier: A sense amplifier includes a first PMOS transistor, a second PMOS transistor, a third PMOS transistor, a fourth PMOS transistor, a first NMOS transistor, a second NMOS transistor, a third NMOS transistor, and a fourth NMOS transistor. The first PMOS transistor, the second PMOS transistor, the first NMOS transistor, and... Agent: Taiwan Semiconductor Manufacturing Company, Ltd.
20120213020 - Memory controller: A memory component having a first and second interface. The first interface is provided to sample address information in response to a first clock signal. The first interface includes inputs to sample at least two bits of the address information in succession during a clock cycle of the first clock... Agent:
20120213019 - Semiconductor memory apparatus and data input/output method thereof: A semiconductor memory apparatus includes: a first bit line of to a first memory bank; a first middle input/output line configured to be electrically connected to the first bit line; a second bit line of a second memory bank; a second middle input/output line configured to be electrically connected to... Agent: Hynix Semiconductor Inc.
20120213021 - Semiconductor device having redundant bit line provided to replace defective bit line: Disclosed herein is a device that responds to mat selection information, which is used to select one of memory mats, and selects at least one defective address from a plurality of defective addresses which are stored, for example, in a fuse circuit. When the access address information is coincident with... Agent: Elpida Memory, Inc.
20120213022 - Sip semiconductor system: A system in package (SIP) semiconductor system includes a memory device, a controller, a first input/output terminal, a test control unit, and a second input/output terminal. The controller communicates with the memory device. The first input/output terminal performs communication between the controller and a device external to the SIP semiconductor... Agent: Hynix Semiconductor Inc.
20120213024 - Memory device with data prediction based access time acceleration: A memory device includes a memory array comprising a plurality of memory cells, sensing circuitry coupled to at least a given bitline associated with a particular column of the memory cells of the memory array, and access time acceleration circuitry coupled to the bitline. The access time acceleration circuitry is... Agent:
20120213023 - Systems and methods for memory device precharging: Systems and methods for determining optimal memory device precharge voltages are provided herein. In addition, systems and methods for providing localized sense amplification and circuit assist circuitry are described herein. Embodiments provide for determining precharge multipliers that may be used to determine the optimal precharge voltage based on a precharge... Agent: International Business Machines Corporation
20120213025 - Semiconductor memory device for minimizing mismatch of sense amplifier: A semiconductor memory device is provided. The semiconductor memory device includes a cross-coupled latch type sense amplifier and a buffer that prevents mismatch. The buffer is formed between PMOS transistors and NMOS transistors of the sense amplifier so that mismatch for transistors operating in pair can be minimized.... Agent: Hynix Semiconductor Inc.
20120213026 - Memory device and method for sensing a content of a memory cell: A memory device and a method for sensing a content of a memory cell. The memory device includes: a pair of bit-lines; a memory cell coupled between the pair of bit-lines; a sensing circuit having at least two inputs for receiving respective currents from a current conveyor, said sensing circuit... Agent: Freescale Semiconductor, Inc.
20120213027 - Method and apparatus to implement a reset function in a non-volatile static random access memory: A system and method for resetting semiconductor memory is disclosed. The present invention uses an array reset circuit to independently drive the bit lines of a volatile memory cell high or low so as to reset either a single memory cell or all memory cells in an array with all... Agent: Cypress Semiconductor Corporation
20120213028 - Memory cell and memory array utilizing the memory cell: A memory cell comprising a first switch device, a second switch device and a capacitor is disclosed. The first switch device has: a control terminal coupled to a select line, wherein the first switch device is controlled by the select line; a first terminal, coupled to a bit line parallel... Agent:08/16/2012 > 39 patent applications in 26 patent subcategories. inventions list
20120206951 - High density cam array architectures with adaptive current controlled match-line discharge: An integrated circuit having a CAM array includes a plurality of CAM cells organized in rows and columns where each row corresponds to an address word and each column corresponds to a bit position, and a match line for each row connected to be shared by CAM cells in that... Agent:
20120206952 - Semiconductor device having multiport memory: A semiconductor device enabling expansion of a noise margin. For example, in a memory area in which each memory cell MC is coupled to a word line WLA for a first port and a word line WLB for a second port, and a plurality of memory cells MC are disposed... Agent: Renesas Electronics Corporation
20120206953 - Memory edge cell: A circuit comprises a first PMOS transistor, a second PMOS transistor, a first NMOS transistor, a second NMOS transistor, a third NMOS transistor, and a fourth NMOS transistor. The PMOS transistors and the NMOS transistors are configured to provide a first voltage reference node having a first reference voltage and... Agent: Taiwan Semiconductor Manufacturing Company, Ltd.
20120206954 - Semiconductor device and electronic device: There is a need to provide a semiconductor device and an electronic device capable of easily allowing a bypass capacitor to always improve noise suppression on a signal path in order to transmit a reference potential between chips in different power supply noise states. There is provided a specified signal... Agent: Renesas Electronics Corporation
20120206955 - Memory module having high data processing rate: A memory module having a high data processing rate and high capacity is provided. The memory module may include a memory chip, a controller controlling an operation of the memory chip, an optical detector converting an external input signal into an internal input signal to transmit the converted signal to... Agent:
20120206956 - Memory circuit: While the supply of power is stopped, a data signal that has been held in a volatile memory section can be held in a nonvolatile memory section. In the nonvolatile memory section, a transistor having an extremely low off-state current allows a data signal to be held in the capacitor... Agent: Semiconductor Energy Laboratory Co., Ltd.
20120206957 - Identifying and correcting a bit error in a fram storage unit of a semiconductor device: An embodiment of semiconductor device including a control unit and an FRAM storage unit is disclosed. The FRAM storage unit contains FRAM cells. The control unit includes a predetermined test data pattern. The control unit is configured to read the FRAM cells that contain a test data pattern in a... Agent: Texas Instruments Incorporated
20120206959 - Magnetic memory cell and magnetic random access memory: A magnetic memory cell 1 is provided with a magnetic recording layer 10 which is a ferromagnetic layer and a pinned layer 30 connected with the magnetic recording layer 10 through a non-magnetic layer 20. The magnetic recording layer 10 has a magnetization inversion region 13, a first magnetization fixed... Agent:
20120206958 - Magnetic random access memory with field compensating layer and multi-level cell: A spin toque transfer magnetic random access memory (STTMRAM) element comprises a reference layer formed on a substrate, with a fixed perpendicular magnetic component. A junction layer is formed on top of the reference layer and a free layer is formed on top of the junction layer with a perpendicular... Agent: Avalanche Technology, Inc.
20120206960 - Nonvolatile semiconductor memory device using mis transistor: A nonvolatile semiconductor memory device includes an MIS transistor having nodes, a control circuit configured to apply a first set of potentials to the nodes to cause an irreversible change in transistor characteristics, to apply a second set of potentials to the nodes to cause a first current to flow... Agent: Nscore, Inc.
20120206962 - Method of handling reference cells in nvm arrays: A memory chip includes memory cells storing data to be read; at least one reference cell having a reference cell current level and a reference gate voltage adjuster to adjust, for each reference cell, a reference gate voltage level to compensate for a shift of the reference cell current level... Agent: Infinite Memories Ltd.
20120206963 - Semiconductor associative memory device: According to one embodiment, a semiconductor associative memory device comprises a retrieval block having retrieval word strings arranged in a column direction, each of the retrieval word strings includes memory cells arranged in a row direction between a word input terminal and a word output terminal, each of the memory... Agent: Kabushiki Kaisha Toshiba
20120206964 - Programming rate identification and control in a solid state memory: Memory devices adapted to receive and transmit analog data signals representative of bit patterns of two or more bits facilitate increases in data transfer rates relative to devices communicating data signals indicative of individual bits. Programming of such memory devices includes determining a rate of programming (i.e., rate of movement... Agent: Micron Technology, Inc.
20120206966 - Method for modifying data more than once in a multi-level cell memory location within a memory array: A method and apparatus for marking a block of multi-level memory cells for performance of a block management function by programming at least one bit in a lower page of the memory cell block such that a first logic state is stored in the at least one bit in the... Agent:
20120206965 - Nonvolatile semiconductor memory device: According to one embodiment, an erase verification execution unit that makes an erase verify operation of a memory cell, on which an erase operation is performed, to be performed, a number-of-erase-verifications counting unit that counts the number of erase verifications of a memory cell on which the erase operation is... Agent: Kabushiki Kaisha Toshiba
20120206968 - Nonvolatile semiconductor memory device: A nonvolatile semiconductor memory device includes a control circuit configured to control a soft program operation of setting nonvolatile memory cells to a first threshold voltage distribution state of the nonvolatile memory cells. When a characteristic of the nonvolatile memory cells is in a first state, the control circuit executes... Agent: Kabushiki Kaisha Toshiba
20120206967 - Programming and selectively erasing non-volatile storage: A non-volatile storage system performs programming for a plurality of non-volatile storage elements and selectively performs re-erasing of at least a subset of the non-volatile storage elements that were supposed to remain erased, without intentionally erasing programmed data.... Agent:
20120206969 - Memory array: A memory array used in the field of semiconductor technology includes a plurality of memory cells, bit lines, word lines perpendicular to the bit lines, and first/second control lines. The memory array uses split-gate memory cells, wherein two memory bit cells of a memory cell share one word line, thereby... Agent: Grace Semiconductor Manufacturing Corporation
20120206971 - Programmable memory device and memory access method: A programmable memory device includes a plurality of one-time programmable (OTP) memory units, a search unit, a writing unit, and a reading unit. Each OTP memory unit is assigned an address. The search unit searches for the first writable OTP memory unit from the plurality of OTP memory units in... Agent: Pixart Imaging Inc.
20120206970 - Semiconductor memory device: According to one embodiment, an interface includes first to third input circuits, delay and selection circuits. The first input circuit outputs an active first internal signal in response to an active first control signal received by a memory device. The second input circuit outputs an active second internal signal in... Agent:
20120206972 - Nonvolatile semiconductor memory device: A control circuit executes an erase operation that includes an erase pulse application operation and an erase verify operation. The erase pulse application operation applies an erase pulse voltage to a memory cell to change the memory cell from a write state to an erase state. The erase verify operation... Agent: Kabushiki Kaisha Toshiba
20120206961 - Method for operating nonvolatile semiconductor memory device: According to one embodiment, a method for operating a nonvolatile semiconductor memory device, the device includes a memory unit having a memory string, and a control unit. The memory string includes a plurality of transistors and has a first group being part of the transistors, a adjusting transistor connected next... Agent: Kabushiki Kaisha Toshiba
20120206973 - Digital method to obtain the i-v curves of nvm bitcells: A calibration table (160) of reference current (Iref) values and associated digital register settings is used during user test/diagnostics mode by varying the Iref values by changing the digital register settings and searching the transitioning gate voltage (Vg) of each bitcell at each Iref value to obtain the bitcell I-V... Agent:
20120206974 - Sensing for all bit line architecture in a memory device: Methods for sensing, memory devices, and memory systems are disclosed. One such method for sensing includes charging bit lines of an all bit line architecture to a precharge voltage, selecting a word line, and performing a sense operation on the bit lines. After the sense operation on the memory cells... Agent: Micron Technology, Inc.
20120206975 - Semiconductor memory apparatus and data erasing method: A data erasing method of a semiconductor memory apparatus may include: if any one threshold voltage of a plurality of memory cells, for which an erase operation has been performed using an erase voltage pulse, is higher than an erase verification voltage, increasing a voltage level of the erase verification... Agent: Hynix Semiconductor Inc.
20120206977 - Semiconductor memory system capable of suppressing consumption current: According to one embodiment, a semiconductor memory system includes a first semiconductor memory device, a second semiconductor memory device, and a wiring line. The wiring line is connected between the first semiconductor memory device and the second semiconductor memory device. When one of the first and second semiconductor memory devices... Agent:
20120206976 - Semiconductor storage device: A memory includes a sense amplifier connected to one or more of bit lines and configured to sense data stored in the memory cells; and a word line driver configured to control a voltage of one or more of word lines. The memory cells constitute a memory block. The memory... Agent: Kabushiki Kaisha Toshiba
20120206978 - Non-volatile memory and method for power-saving multi-pass sensing: A non-volatile memory device and power-saving techniques capable of reading and writing a large number of memory cells with multiple read/write circuits in parallel has features to reduce power consumption during sensing, which is included in read, and program/verify operations. A sensing verify operation includes one or more sensing cycles... Agent:
20120206979 - 3-d structured non-volatile memory device and method of manufacturing the same: A non-volatile memory device includes channel structures that each extend in a first direction, wherein the channel structures each include channel layers and interlayer dielectric layers that are alternately stacked; source structure extending in a second direction crossing the first direction and connected to ends of the channel structures, wherein... Agent:
20120206980 - Buffering systems for accessing multiple layers of memory in integrated circuits: Embodiments of the invention relate generally to data storage and computer memory, and more particularly, to systems, integrated circuits and methods for accessing memory in multiple layers of memory implementing, for example, third dimension memory technology. In a specific embodiment, an integrated circuit is configured to implement write buffers to... Agent: Unity Semiconductor Corporation
20120206981 - Method and device for writing data: Embodiments of the present invention provide a method and a device for writing data. The method includes: receiving a data block that is to be written in an EDRAM; obtaining, according to a status of a bank in the EDRAM, usable addresses corresponding to usable banks in the EDRAM; selecting... Agent: Huawei Technologies Co., Ltd.
20120206982 - Semiconductor device and method: A semiconductor device is provided with first and second main word lines, and a control circuit. The control circuit, in response to a command signal received from outside of the semiconductor device, activates the first main word line at a first timing, and activates the second main word line at... Agent: Elpida Memory, Inc.
20120206984 - Method and apparatus for performing refresh operations in high-density memories: A method for performing refresh operations is disclosed. In response to a completion of a memory operation, a determination is made whether or not a refresh backlog count is greater than a first predetermined value. In a determination that the refresh backlog count is greater than the first predetermined value,... Agent: Ibm Corporation
20120206983 - Tracking scheme for memory: A memory has a tracking circuit for a read tracking operation. The memory includes a memory bit cell array, a tracking column, a tracking row, a sense amplifier row coupled to the memory bit cell array and the tracking row, and a sense amplifier enable logic. The memory further includes... Agent: Taiwan Semiconductor Manufacturing Company, Ltd.
20120206985 - Static random access memory (sram) and test method of the sram having precharge circuit to prepcharge bit line: A method of testing a static random access memory (SRAM), the method including writing a data into the SRAM cell to store a first potential level at a first node and a second potential level greater than the first potential level at a second node, supplying a power supply voltage... Agent: Renesas Electronics Corporation
20120206986 - Amplifier sensing: A circuit comprises a first read bit line, a second read bit line, and a sense amplifier. First and second read bit lines couple a plurality of memory cells and a reference cell of a memory array, respectively. The sense amplifier is configured to receive the first read bit line... Agent: Taiwan Semiconductor Manufacturing Company, Ltd.
20120206987 - Memory device and related operating methods: A memory device is provided that includes a memory cell, a voltage input, a plurality of bit lines, an amplifier connected to only a particular one of the bit lines, and a switch that is coupled to the amplifier and the voltage input. The switch is configured to prevent the... Agent: Advanced Micro Devices, Inc.
20120206988 - Negative voltage generator and semiconductor memory device: A negative voltage generator includes a variable-capacitance negative voltage generating unit, a switching unit and a positive voltage applying unit. The negative voltage generating unit includes a plurality of coupling capacitors for varying the capacitance in which the negative voltage is charged. The negative voltage generating unit selects at least... Agent:
20120206989 - Semiconductor memory devices with a power supply: A semiconductor device includes a virtual power supplier, a driving signal generator and a load driver. The virtual power supplier boosts a driving voltage to generate a virtual voltage. The driving signal generator generates a driving signal based on the virtual voltage, such that the driving signal has a voltage... Agent:08/09/2012 > 24 patent applications in 16 patent subcategories. inventions list
20120201068 - Stacked semiconductor device: A stacked semiconductor device is disclosed that includes a plurality of semiconductor dies. Each die has oppositely disposed first and second surfaces, with pads formed on each of the surfaces. A plurality of through-vias connect respective pads on the first surface to respective pads on the second surface. The through-vias... Agent:
20120201069 - Memory unit and method of operating the same: A memory unit includes memory elements and a drive section. In executing a first operation out of the first operation for changing resistance state of the memory element from one resistance state out of low resistance state and high resistance state to the other resistance state and a second operation... Agent: Sony Corporation
20120201070 - Nonvolatile semiconductor storage device and data writing method therefor: A nonvolatile semiconductor storage device includes first and second intersecting wires; a electrically rewritable memory cell disposed at each intersection of the first second wires, including a variable resistor for memorizing a resistance value as data in a nonvolatile manner and a rectifying device are connected in series; and a... Agent: Kabushiki Kaisha Toshiba
20120201071 - Semiconductor memory device: A semiconductor memory device includes a memory array including a plurality of element blocks; the plurality of element blocks including end-portion element blocks arranged at an end portion of the memory array, and at least one dummy block disposed adjacent to the end-portion element blocks, the at least one dummy... Agent: Rohm Co., Ltd.
20120201072 - Sram cell having an n-well bias: An integrated circuit containing SRAM cells. Each SRAM cell has a PMOS driver transistor, a PMOS passgate transistor, and at least two separate n-wells. The integrated circuit also has an n-well bias control circuit that is configured to independently bias the n-wells of an addressed SRAM cell. Moreover, a process... Agent: Texas Instruments Incorporated
20120201075 - Magnetic memory with asymmetric energy barrier: A magnetic tunnel junction memory cell includes a ferromagnetic reference layer, a ferromagnetic free layer, and a non-magnetic barrier layer separating the ferromagnetic reference layer from the ferromagnetic free layer. The magnetic tunnel junction cell has an asymmetric energy barrier for switching between a high resistance data state and a... Agent: Seagate Technology LLC
20120201074 - Magnetic random access memory devices configured for self-referenced read operation: A magnetic random access memory cell includes a sense layer, a storage layer, and a spacer layer disposed between the sense layer and the storage layer. During a write operation, the storage layer has a magnetization direction that is switchable between m directions to store data corresponding to one of... Agent:
20120201073 - Memory devices with series-interconnected magnetic random access memory cells: A memory device includes magnetic random access memory (“MRAM”) cells that are electrically connected in series, each one of the MRAM cells having a storage magnetization direction and a sense magnetization direction. During a write operation, multiple ones of the MRAM cells are written in parallel by switching the storage... Agent:
20120201076 - Spintronic devices with integrated transistors: The semiconductor industry seeks to replace traditional volatile memory devices with improved non-volatile memory devices. The increased demand for a significantly advanced, efficient, and non-volatile data retention technique has driven the development of integrated Giant-Magneto-resistive (GMR) structures. The present teachings relates to integrated latch memory and logic devices and, in... Agent: Micron Technology, Inc.
20120201077 - Nonvolatile semiconductor memory and control method thereof: According to one embodiment, a nonvolatile semiconductor memory includes memory cells storing data of multi-level, a bit scan circuit to scan the number of to-be-written memory cells and the number of memory cells that have passed the verify, a processing unit to perform an operation process based on a scan... Agent:
20120201078 - Storage at m bits/cell density in n bits/cell analog memory cell devices, m>n: A method for data storage includes accepting data for storage in a memory that includes multiple analog memory cells and supports a set of built-in programming commands. Each of the programming commands programs a respective page, selected from a group of N pages, in a subset of the memory cells.... Agent: Anobit Technologies Ltd.
20120201079 - Semiconductor memory device in which capacitance between bit lines is reduced, and method of manufacturing the same: According to one embodiment, a semiconductor memory device includes a plurality of memory cells arranged in a matrix, a plurality of word lines for selecting a plurality of memory cells, and a plurality of bit lines for selecting a plurality of memory cells. Of the plurality of bit lines, first... Agent:
20120201080 - Nonvolatile memory devices and driving methods thereof: Nonvolatile memory devices including memory cell arrays with a plurality of cell strings connected between a substrate and a plurality of bit lines and selected by selection lines, and a gating circuit configured to drive the selection lines in at least two directions.... Agent: Samsung Electronics Co., Ltd.
20120201081 - Semiconductor storage device: The invention provides a semiconductor storage device which can restrain the uneven high voltage applied to the storage unit and can provide the high voltage with high precision. The semiconductor storage device includes a storage unit array, a Y decoder circuit, a X decoder circuit, a sense amplifier circuit, a... Agent: Rohm Co., Ltd.
20120201082 - Erase ramp pulse width control for non-volatile memory: A method of erasing a memory block of a non-volatile memory, including setting a pulse width of erase pulses to an initial width, repeatedly applying erase pulses to the memory block until the memory block meets an erase metric or until a maximum number of erase pulses have been applied,... Agent: Freescale Semiconductor, Inc.
20120201083 - Semiconductor memory device including stacked gate having charge accumulation layer and control gate and method of writing data to semiconductor memory device: A semiconductor memory device includes memory cells, word lines, a driver circuit, and a control circuit. The driver circuit repeats a programming operation of selecting any one of the word lines, of applying a first voltage to selected one of the word lines, and of applying a second voltage to... Agent:
20120201084 - Operating methods of flash memory and decoding circuits thereof: A FLASH memory cell includes a control gate over a floating gate over a substrate. A wall line and an erase gate each is disposed adjacent to a respective sidewall of the control gate. A first source/drain (S/D) region is disposed in the substrate and adjacent to a sidewall of... Agent: Taiwan Semiconductor Manufacturing Company, Ltd.
20120201085 - Low power memory control circuits and methods: Circuits and methods for suppressing integrated circuit leakage currents are described. Many of these circuits and methods are particularly well-suited for use in dynamic memory circuits. Examples describe the use of power, ground, or both and power and ground source transistors used for generating virtual voltages. An aspect of the... Agent: Zmos Technology, Inc.
20120201086 - Signal margin improvement for read operations in a cross-point memory array: A configuration for biasing conductive array lines in a two-terminal cross-point memory array is disclosed. The configuration includes applying a read voltage to a selected X-conductive array line while applying an un-select voltage thru a biasing element to a remaining plurality of un-selected X-conductive array lines. A plurality of Y-conductive... Agent: Unity Semiconductor Corporation
20120201089 - Integrated circuit device comprises an interface to transmit a first code, a strobe signal after a delay and data to a dynamic random access memory (dram): An integrated circuit device comprises an interface to transmit a first code, a strobe signal after a delay and data to a dynamic random access memory (DRAM). The first code indicates that data is to be written to the DRAM. The first code is registered by the DRAM on one... Agent: Rambus Inc.
20120201087 - Laminated wiring board: A laminated wiring board includes a plurality of wiring layers that are stacked with the intermediary of an insulating layer between the layers and have a four-layer wiring unit obtained by disposing a power supply layer, a ground layer, a first signal wiring layer, and a second signal wiring layer... Agent: Sony Corporation
20120201088 - Memory circuit system and method: A memory circuit system and method are provided in the context of various embodiments. In one embodiment, an interface circuit remains in communication with a plurality of memory circuits and a system. The interface circuit is operable to interface the memory circuits and the system for performing various functionality (e.g.... Agent: Google Inc.
20120201090 - Power savings mode for memory systems: A system and method are disclosed to accomplish power savings in an electronic device, such as a memory chip, by performing selective frequency locking and subsequent instantaneous frequency switching in the DLL (delay locked loop) used for clock synchronization in the electronic device. By locking the DLL at a slow... Agent: Micron Technology, Inc.
20120201091 - Memory card test interface: A memory card and methods for testing memory cards are disclosed herein. The memory card has a test interface that allows testing large numbers of memory cards together. Each memory card may have a serial data I/O contact and a test select contact. The memory cards may only send data... Agent:08/02/2012 > 65 patent applications in 37 patent subcategories. inventions list
20120195090 - Semiconductor device including plural chips stacked to each other: Such a device is disclosed that includes first and second chips stacked to each other, and a third chip controlling the first and second chips, stacked on the first and second chips, and including first, second and third output circuits. The first output circuit supplies a first command signal to... Agent: Elpida Memory, Inc.
20120195089 - Semiconductor memory chip and multi-chip package using the same: A semiconductor memory chip includes a first pad unit configured to receive a first data and a first strobe signal, and a first selection transfer unit configured to transfer the first data and the first strobe signal to a first write path circuit in a first mode, and transfer the... Agent: Hynix Semiconductor Inc.
20120195091 - Method and system for split threshold voltage programmable bitcells: A memory device includes an antifuse. The antifuse is configured to program a bit cell of the memory device. The antifuse is configured with a PMOS device... Agent: Broadcom Corporation
20120195092 - Rom generator: According to one embodiment, a ROM generator includes a ROM-data acquiring unit that acquires ROM data; a cell-data storing unit that stores a plurality of cell data respectively having different connection places of a connection path with respect to same ROM data; a cell-data selecting unit that selects the cell... Agent: Kabushiki Kaisha Toshiba
20120195096 - Differential plate line screen test for ferroelectric latch circuits: Non-volatile latch circuits, such as in memory cells and flip-flops, that are constructed for reliability screening. The non-volatile latch circuits each include ferroelectric capacitors coupled to storage nodes, for example at the outputs of cross-coupled inverters. Separate plate lines are connected to the ferroelectric capacitors of the complementary storage nodes.... Agent: Texas Instruments Incorporated
20120195094 - Memory support provided with elements of ferroelectric material and programming method thereof: Logic data is written in a memory having a first word line and a first bit line, with the memory including a first memory cell having a first ferroelectric transistor. The first ferroelectric transistor includes a layer of ferroelectric material and has a first conduction terminal coupled to the first... Agent: Stmicroelectronics S.r.i.
20120195093 - Memory support provided with memory elements of ferroelectric material and improved non-destructive reading method thereof: A method is for non-destructive reading of an information datum stored in a memory that includes a first wordline, a first bitline and a second bitline, and a first ferroelectric transistor, which is connected between the bitlines and has a control terminal coupled to the first wordline. The method includes... Agent: Stmicroelectronics S.r.l.
20120195095 - Memory support provided with memory elements of ferroelectric material and non-destructive reading method thereof: A method for non-destructive reading of logic data stored in a memory includes applying to a first wordline a reading voltage so as not to cause a variation of the stable state of polarization of a layer of ferroelectric material, and generating a difference of potential between first and second... Agent: Stmicroelectronics S.r.i
20120195097 - Method and system for utilizing perovskite material for charge storage and as a dielectric: A memory device is disclosed. In a first aspect the memory comprises a first doped awell; two wells of opposite doping implanted in the first doped well; and two bitlines located on top of the two wells. The memory includes a Perovsite material on top of the first doped well... Agent: 4d-s Pty Ltd.
20120195098 - Method and system for utilizing perovskite material for charge storage and as a dielectric: A memory device is disclosed. In a first aspect the memory comprises a first doped awell; two wells of opposite doping implanted in the first doped well; and two bitlines located on top of the two wells. The memory includes a Perovsite material on top of the first doped well... Agent: 4d-s Pty Ltd.
20120195099 - Changing a memristor state: A method of changing a state of a memristor having a first intermediate layer, a second intermediate layer, and a third intermediate layer positioned between a first electrode and a second electrode includes applying a first pulse having a first bias voltage across the memristor, wherein the first pulse causes... Agent:
20120195101 - Resistance-changing memory device: A resistance-changing memory device has a cell array having memory cells, each of which stores as data a reversibly settable resistance value, a sense amplifier for reading data from a selected memory cell in the cell array, and a voltage generator circuit which generates, after having read data of the... Agent: Kabushiki Kaisha Toshiba
20120195100 - Semiconductor device and method of controlling semiconductor device: Provided is a semiconductor device including: a memory cell having a variable resistance device; and a control unit that controls a voltage applied to the memory cell, wherein the variable resistance device includes a lower electrode contains a first metal material, an upper electrode containing a second metal material, and... Agent: Renesas Electronics Corporation
20120195102 - Nano-electro-mechanical dram cell: A DRAM cell and method for storing information in a dynamic random access memory using an electrostatic actuator beam to make an electrical connection between a storage capacitor and a bit line.... Agent: International Business Machines Corporation
20120195103 - Semiconductor device having complementary bit line pair: Disclosed herein is a semiconductor device comprising complementary pair of bit lines, memory cells connected to the bit lines, dummy cells having the same structure as the memory cells, a differential sense amplifier, an equalizing circuit equalizing potentials of the bit lines, and a control circuit. The memory cells are... Agent: Elpida Memory Inc.
20120195104 - Semiconductor memory device: The capacitance of a capacitor that is required in a DRAM is reduced, whereby a highly integrated DRAM is provided. In a divided bit line type DRAM, a sub bit line is formed below a word line and a bit line is formed above the word line. The parasitic capacitance... Agent: Semiconductor Energy Laboratory Co., Ltd.
20120195107 - Method for selectable guaranteed write-through with early read suppression: A static random access memory with write-through capability includes a memory cell configured to store a bit of data. A write enable signal is configured to enable writing a write value from a write line input into the static random access memory cell and to enable reading a read value... Agent: International Business Machines Corporation
20120195110 - Semiconductor memory device: When threshold voltages of constituent transistors are reduced in order to operate an SRAM circuit at a low voltage, there is a problem in that a leakage current of the transistors is increased and, as a result, electric power consumption when the SRAM circuit is not operated while storing data... Agent: Renesas Electronics Corporation
20120195109 - Semiconductor storage device: According to one embodiment, a sense amplifier detects data stored in a memory cell based on potentials of bit lines of a bit line pair where bit line pairs are provided to correspond to columns of a memory cell array, respectively. Dummy cells are provided to correspond to rows of... Agent: Kabushiki Kaisha Toshiba
20120195105 - Sram bit cell: A semiconductor memory bit cell includes an inverter latch including a pair of cross-coupled inverters. A first transistor has a gate coupled to a first control line and a source coupled to the inverter latch, and a second transistor has a gate coupled to a second control line and a... Agent: Taiwan Semiconductor Manufacturing Co., Ltd.
20120195108 - Sram cell having a p-well bias: A process of performing an SRAM single sided write operation including applying a positive bias increment to an isolated p-well containing a passgate in an addressed SRAM cell. A process of performing an SRAM single sided read operation including applying a negative bias increment to an isolated p-well containing a... Agent: Texas Instruments Incorporated
20120195106 - Sram timing cell apparatus and methods: Apparatus and methods for providing SRAM timing tracking cell circuits are disclosed. In an embodiment, an apparatus comprises an SRAM array comprising static random access memory cells arranged in rows and columns; a plurality of word lines each coupled to memory cells along one of the rows; a clock generation... Agent: Taiwan Semiconductor Manufacturing Company, Ltd.
20120195111 - In-line register file bitcell: An SRAM bitcell architecture is described having a dedicated read port (N0/N1/N6, N3/N4/N7) with pull up transistors (N6, N7) that shares at least a first bit line pair (23, 24) and word line signal (25), thereby providing separate data access read paths to a 6T SRAM architecture such that the... Agent:
20120195112 - Method of writing to a spin torque magnetic random access memory: A method includes destructively reading bits of a spin torque magnetic random access memory and immediately writing back the original or inverted values. A detection of the majority state of the write back bits and a conditional inversion of write back bits are employed to reduce the number of write... Agent: Everspin Technologies, Inc.
20120195113 - Phase change random access memory apparatus: A phase change random access memory (PCRAM) apparatus includes: a memory cell array including a plurality of phase change memory cells; and a firing control unit configured to provide a firing voltage for firing the plurality of phase change memory cells to a global bit line in response to an... Agent: Hynix Semiconductor Inc.
20120195114 - Semiconductor storage device, semiconductor storage device manufacturing method and package resin forming method: A ferroelectric capacitor comprising a transistor layer superimposed on a semiconductor substrate, a ferroelectric capacitor layer provided superior to the transistor layer, a wiring layer provided superior to the ferroelectric capacitor layer, and a passivation film. Further, at least one layer of barrier film capable of inhibiting penetration of moisture... Agent: Fujitsu Semiconductor Limited
20120195115 - Semiconductor device: A first field-effect transistor provided over a substrate in which an insulating region is provided over a first semiconductor region and a second semiconductor region is provided over the insulating region; an insulating layer provided over the substrate; a second field-effect transistor that is provided one flat surface of the... Agent: Semiconductor Energy Laboratory Co., Ltd.
20120195116 - Nonvolatile memory device and method for manufacturing the same: According to one embodiment, a method is disclosed for manufacturing a nonvolatile memory device. The method can include forming a second stacked body, removing the second stacked body formed in a region where a first memory unit will be formed, forming a first stacked body, and removing the first stacked... Agent: Kabushiki Kaisha Toshiba
20120195119 - Nonvolatile semiconductor memory device: In writing, a first write operation to a first memory cell is executed; and a second write operation for providing a first threshold-voltage distribution to a second memory cell adjacent to the first one, is executed. The first threshold voltage distribution is a lowest threshold-voltage distribution among the positive threshold... Agent: Kabushiki Kaisha Toshiba
20120195120 - Nonvolatile semiconductor memory device: A control circuit controls erase operation to erase data of memory transistors, correction write operation, and correction write verify operation. In the correction write operation, a erase threshold level of a memory transistor is moved to a positive threshold level after the erase operation. In the correction write verify operation,... Agent: Kabushiki Kaisha Toshiba
20120195118 - Semiconductor memory apparatus, data programming method thereof, and memory system including the same: A semiconductor memory apparatus includes: a memory unit including a first memory group and a second memory group; and a control unit configured to control input data to be programmed into selected memory cells of the first memory group such that one-bit data is programmed into each of the memory... Agent: Hynix Semiconductor Inc.
20120195117 - Semiconductor system and data programming method: A data programming method includes the steps of determining whether a threshold voltage distribution of a memory cell, where a first bit value of writing data was programmed, has deviated from a targeted first voltage range, correcting the first bit value through an error correction code if the threshold voltage... Agent: Hynix Semiconductor Inc.
20120195121 - Nonvolatile semiconductor memory device: A nonvolatile semiconductor memory device including a memory cell array of memory cells arranged in a matrix, each of which includes a selecting transistor and a memory cell transistor; a column decoder controlling the potential of bit lines; a voltage application circuit controlling the potential of the first word lines;... Agent: Fujitsu Semiconductor Limited
20120195122 - Memory circuit: The present invention provides a memory circuit in which, while the power is not supplied, a data signal that has been held in a memory section corresponding to a volatile memory can be held in a capacitor in a memory section corresponding to a nonvolatile memory. In the nonvolatile memory... Agent: Semiconductor Energy Laboratory Co., Ltd.
20120195123 - Method and apparatus for management of over-erasure in nand-based nor-type flash memory: A method and apparatus for operating an array block of dual charge retaining transistor NOR flash memory cells by erasing the dual charge retaining transistor NOR flash memory cells to set their threshold voltage levels to prevent leakage current from corrupting data during a read operation. Erasure of the array... Agent: Aplus Flash Technology, Inc.
20120195125 - Operating method of nonvolatile memory device: Disclosed is an operating method of a nonvolatile memory device, which includes programming the first selection transistors of the plurality of cell strings and programming the plurality of memory cells of the plurality of cell strings. The programming the first selection transistors comprises supplying a first voltage to a first... Agent:
20120195124 - Programming a non-volatile memory: In a system having a plurality of non-volatile memory cells, a method includes performing hot carrier injection on a first non-volatile memory cell in a first mode of programming. In the first mode, current flows from a first current electrode to a second electrode of the first non-volatile memory cell... Agent:
20120195126 - Cell operation monitoring: Memory devices adapted to process and generate analog data signals representative of data values of two or more bits of information facilitate increases in data transfer rates relative to devices processing and generating only binary data signals indicative of individual bits. Programming of such memory devices includes programming to a... Agent: Micron Technology, Inc.
20120195127 - Non-volatile semiconductor memory: A non-volatile semiconductor memory includes a plurality of memory cells and a driver for selectively driving the memory cells. The driver includes a first drive portion and a second drive portion. The first drive portion is provided for applying a source voltage higher than a power source voltage to a... Agent:
20120195128 - Nonvolatile semiconductor memory device and method for driving the same: According to one embodiment, a nonvolatile semiconductor memory device includes a memory unit and a control unit. The memory unit includes a multilayer structure, a semiconductor pillar, a storage layer, an inner insulating film, an outer insulating film, a memory cell transistor. The control unit performs control of setting the... Agent: Kabushiki Kaisha Toshiba
20120195129 - Nonvolatile semiconductor memory device: A control circuit controls various kinds of operations on the memory cell array. The control circuit executes a pre-erase stress application operation in which, when an erase operation on one of the memory cells is executed, prior to the erase operation, a first voltage belonging in a certain voltage range... Agent: Kabushiki Kaisha Toshiba
20120195130 - Semiconductor memory device and data erase method thereof: A semiconductor memory device includes: a plurality of memory cells coupled in series between a bit line and a source line; and a bit line control voltage supply unit configured to provide a control voltage to the bit line according to an operation mode, wherein the bit line control voltage... Agent: Hynix Semiconductor Inc.
20120195131 - Memory register encoding apparatus and methods: Apparatus, systems, and methods are disclosed that operate to encode register bits to generate encoded bits such that, for pairs of addresses, an encoded bit to be coupled to a first address in a memory device may be exchanged with an encoded bit to be coupled to a second address... Agent:
20120195134 - Data alignment circuit: A data alignment circuit includes: a select transmission unit configured to selectively transmit a first pulse or ground voltage as a first control pulse and selectively transmit a second pulse or ground voltage as a second control pulse, in response to a control signal; and a data latch unit configured... Agent: Hynix Semiconductor Inc.
20120195132 - Semiconductor integrated circuit: According to one embodiment, a semiconductor integrated circuit includes an input register which latches, by a second unit, data which are read from a memory cell array by a first unit, a bit state-counter which counts a bit state of the data latched in the input register, a frame size-setup... Agent: Kabushiki Kaisha Toshiba
20120195133 - Semiconductor memory device having data compression test cicuit: A semiconductor memory device includes a data transmission unit configured to transmit first input data to only a first global line driver or to the first global line driver and a second global line driver in response to a test signal, and a transmission element configured to transmit second input... Agent: Hynix Semiconductor Inc.
20120195135 - Semiconductor memory device: According to one embodiment, a semiconductor memory device includes a plurality of memory cells each of which is arranged at the intersection position between a pair of complementary bit lines and a word line, and stores data between a first power supply voltage applied to a first node and a... Agent: Kabushiki Kaisha Toshiba
20120195138 - Internal voltage generating circuit and semiconductor memory device: A semiconductor memory device includes an internal voltage generating circuit and a memory cell. The internal voltage generating circuit is configured to compare a temperature voltage, which has a level varying with a predetermined slope according to a level change of an internal voltage, with a variable reference voltage, which... Agent: Hynix Semiconductor Inc.
20120195136 - Semiconductor device: A semiconductor device according to the present invention includes plural controlled chips CC0 to CC7 that hold mutually different layer information, and a control chip IF that supplies in common layer address signals A13 to A15 and a command signal ICMD to the controlled chips. Each bit that constitutes the... Agent: Elpida Memory, Inc.
20120195137 - Semiconductor integrated circuit and control method thereof: A semiconductor integrated circuit includes a first chip and a second chip stacked together with the first chip. A first memory area is formed on the second chip, and a second memory area for repairing a failure of the first memory area is formed on the first chip.... Agent: Hynix Semiconductor Inc.
20120195139 - Multi-power domain design: In some embodiments related to a memory array, a sense amplifier (SA) uses a first power supply, e.g., voltage VDDA, while other circuitry, e.g., signal output logic, uses a second power supply, e.g., voltage VDDB. Various embodiments place the SA and a pair of transferring devices at a local IO... Agent: Taiwan Semiconductor Manufacturing Company, Ltd.
20120195140 - Semiconductor integrated circuit: A semiconductor integrated circuit includes a first pad allocated to receive a row address, a second pad allocated to discriminate a first input/output mode and a second input/output mode, a detector configured to generate a detection signal in response to logic levels of the first and second pads, and a... Agent: Hynix Semiconductor Inc.
20120195141 - Generic low power strobe based system and method for interfacing memory controller and source synchronous memory: A system and method for interfacing a memory controller and a source synchronous memory utilizing a generic low power strobe. A set of double rate (2×) strobes can be generated by gating a continuous double rate clock in order to enable the set of double rate strobes only for duration... Agent: Lsi Corporation
20120195142 - Semiconductor memory device: A semiconductor memory device includes a main word line signal generator configured to generate a main word line signal having a first swing width, a sub-word line signal generator configured to generate a first sub-word line signal and a second sub-word line signal having a second swing width and a... Agent:
20120195143 - Semiconductor memory device: A semiconductor memory device includes: a burst start signal generation unit configured to generate a first burst start signal by delaying a write pulse by a first period, generate a second burst start signal by delaying the write pulse by a second period, and selectively transmit the first or second... Agent: Hynix Semiconductor Inc.
20120195144 - Semiconductor device and manufacturing method thereof: Such a device is disclosed that includes: redundancy circuits for replacing defective memory cells included in a memory cell array; an electrical fuse circuit that stores addresses of the defective memory cells; a data determination circuit that generates a determination signal by determining whether test data read from the memory... Agent: Elpida Memory, Inc.
20120195145 - Semiconductor memory for disconnecting a bit line from a sense amplifier in a standby period and memory system including the semiconductor memory: Each memory block has a plurality of memory cells, and word lines and bit lines connected to the memory cells. Precharge switches connect the bit lines to a precharge line. A switch control circuit controls an operation of the precharge switches and sets a cutoff function that turns off connection... Agent: Fujitsu Semiconductor Limited
20120195147 - Bit line precharge circuit and a semiconductor memory apparatus using the same: A bit line precharge circuit includes a precharge signal generation unit configured to generate first and second precharge signals that are enabled at different timing points by receiving a bit line equalizing signal; a first precharge unit configured to connect a pair of bit lines to each other in response... Agent:
20120195146 - Local sense amplifier circuit and semiconductor memory device including the same: A local sense amplifier circuit in a semiconductor memory device, the local sense amplifier circuit including a local data sensing unit configured to amplify a voltage difference between a local input/output (I/O) line pair based on a local sensing enable signal to provide the amplified voltage difference to a global... Agent:
20120195148 - Semiconductor device and information processing system including the same: A semiconductor device according to the present invention includes plural core chips CC0 to CC7 to which mutually different pieces of chip identification information LID are allocated, and an interface chip IF that controls the core chips CC0 to CC7. The interface chip IF receives address information ADD for specifying... Agent: Elpida Memory, Inc.
20120195149 - Circuits and methods for providing refresh addresses and alternate refresh addresses to be refreshed: Circuits and refresh address circuits for providing a refresh address, and methods for refreshing memory cells. An example method includes refreshing a first plurality of memory cells and interrupting the refreshing of the first plurality of memory cells. A second plurality of memory cells is refreshed, at least one of... Agent: Micron Technology, Inc.
20120195150 - Refresh circuit: A refresh circuit includes an enable pulse generator configured to generate a first enable pulse and a second enable pulse, a first address latch configured to latch the first row address in synchronization with the first enable pulse and generate a first latch address, and a second address latch configured... Agent: Hynix Semiconductor Inc.
20120195151 - Semiconductor memory device and method: In an embodiment, a method of operating a memory cell coupled to a first port and to a second port includes determining if a first port is requesting to access the memory cell and determining if a second port is requesting to access the memory cell. Based on the determining,... Agent:
20120195152 - Memory architecture having multiple partial wordline drivers and contacted and feed-through bitlines: Various embodiments are disclosed relating to a memory circuit architecture. In an example embodiment, which may accommodate a change to a new memory size or cell aspect ratio, while migrating between different process nodes or the same process generation, while retaining at least a portion of the periphery circuitry, a... Agent: Broadcom Corporation
20120195153 - Semiconductor system and semiconductor apparatus: A semiconductor apparatus includes an odd data clock buffer group configured to maintain or shift a phase of a multi-phase source clock signal, and output a first multi-phase clock signal, an even data clock buffer group configured to maintain or shift a phase of the multi-phase source clock signal, and... Agent: Hynix Semiconductor Inc.Previous industry: Electric power conversion systems
Next industry: Agitating
RSS FEED for 20140710:
Integrate FreshPatents.com into your RSS reader/aggregator or website to track weekly updates.
For more info, read this article.
Thank you for viewing Static information storage and retrieval patents on the FreshPatents.com website. These are patent applications which have been filed in the United States. There are a variety ways to browse Static information storage and retrieval patent applications on our website including browsing by date, agent, inventor, and industry. If you are interested in receiving occasional emails regarding Static information storage and retrieval patents we recommend signing up for free keyword monitoring by email.
Results in 5.19093 seconds