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Static information storage and retrieval July category listing 07/12

Below are recently published patent applications awaiting approval from the USPTO. Recent week's RSS XML file available below.
Listing for abstract view: USPTO application #, Title, Abstract excerpt,Patent Agent. Listing format for list view: USPTO National Class full category number, title of the patent application.
  
07/26/2012 > 29 patent applications in 20 patent subcategories. category listing

20120188811 - Associative memory: An associative memory capable of reducing erroneous searches is provided. A storage memory in the associative memory stores reference data. A comparator circuit receives externally applied search data and obtains the distance (for example, the Hamming distance) between the reference data and the search data. An oscillating circuit outputs a... Agent: Hiroshima University

20120188812 - Hybrid mram array structure and operation: This invention relates to MRAM technology and new variations on MRAM array architecture to incorporate certain advantages from both cross-point and 1T-1MTJ architectures. The fast read-time and higher signal-to-noise ratio of the 1T-1MTJ architecture and the higher packing density of the cross-point architecture are both exploited by combining certain characteristics... Agent:

20120188813 - Verification algorithm for metal-oxide resistive memory: Memory devices and methods for operating such devices are described which can effectively program the metal-oxide memory elements in an array, while also avoiding applying unnecessarily high voltage pulses. Programming operations described herein include applying a lower voltage pulse across a metal-oxide memory element to establish a desired resistance state,... Agent: Macronix International Co., Ltd.

20120188814 - Memory device and semiconductor device: To provide a memory device which operates at high speed or a memory device in which the frequency of refresh operations is reduced. In a cell array, a potential is supplied from a driver circuit to a wiring connected to a memory cell. The cell array is provided over the... Agent: Semiconductor Energy Laboratory Co., Ltd.

20120188815 - Temporary storage circuit, storage device, and signal processing circuit: A temporary storage circuit including a reduced number of transistors is provided. The temporary storage circuit includes storage elements, each of which includes a first transistor and a second transistor. A channel of the first transistor is formed in an oxide semiconductor layer. A signal potential corresponding to data is... Agent: Semiconductor Energy Laboratory Co., Ltd.

20120188818 - Low-crystallization temperature mtj for spin-transfer torque magnetic random access memory (sttmram): A spin-torque transfer memory random access memory (STTMRAM) element is disclosed and has a fixed layer, a barrier layer formed upon the fixed layer, and a free layer comprised of a low-crystallization temperature alloy of CoFeB—Z where Z is below 25 atomic percent of one or more of titanium, (Ti),... Agent: Avalanche Technology, Inc.

20120188817 - Read sensing circuit and method with equalization timing: A Magnetic Random Access Memory (MRAM) includes read sensing circuitry having an equalizer device configured between a bit cell output node and a reference node of the bit cell. The equalizer is turned on to couple the output node to the reference node during an initial portion of a read... Agent: Qualcomm Incorporated

20120188816 - Row-decoder circuit and method with dual power systems: A Spin-Transfer-Torque Magnetic Random Access Memory includes a dual-voltage row decoder with charge sharing for read operations. The dual-voltage row decoder with charge sharing for read operations reduces read-disturbance failure rates and provides a robust macro design with improved yields. Voltage from one of the power supplies can be applied... Agent: Qualcomm Incorporated

20120188819 - Methods and systems for mems cmos programmable memories and related devices: Systems and methods for CMOS-based MEMS programmable memories are described. In one aspect, the systems and methods provide for a programmable memory having multiple memory cells. Each memory cell includes an electrode disposed within the memory cell, and a conductor material having two ends disposed proximate to the electrode. The... Agent: Baolab Microsystems Sl

20120188821 - Method for achieving four-bit storage using flash memory having splitting trench gate: The present invention discloses a method for achieving four-bit storage by using a flash memory having a splitting trench gate. The flash memory with the splitting trench gate is disclosed in a Chinese patent No. 200710105964.2. At one side that each of two trenches is contacted with a channel, a... Agent:

20120188822 - Control voltage generation circuit and non-volatile memory device including the same: A control voltage generation circuit for generating a control voltage for controlling a high-voltage transistor includes an input node configured to receive a first enable signal; an output node configured to generate the control voltage, a transferor configured to transfer a voltage of the input node to the output node... Agent:

20120188823 - Semiconductor device: A semiconductor device includes a charge pump circuit that generates a first voltage during a first period and a second voltage during a second period following the first period by a boosting operation, a load current application circuit that includes a first memory cell, and that applies the first voltage... Agent: Renesas Electronics Corporation

20120188824 - Programming non-volatile storage with fast bit detection and verify skip: A set of non-volatile storage elements are subjected to a programming process in order to store data. During the programming process, one or more verification operations are performed to determine whether the non-volatile storage elements have reached their target. Non-volatile storage elements being programmed to a first set of one... Agent:

20120188820 - System and method for addressing threshold voltage shifts of memory cells in an electronic product: Methods and systems for addressing threshold voltage shifts of memory cells. A method includes reading a pattern of data from a first plurality of memory cells, comparing the read of the pattern of data with a known pattern of data using a reference, and if the read of the pattern... Agent:

20120188826 - Memory architecture having two independently controlled voltage pumps: In embodiments described herein, a memory architecture has an array of non-volatile memory cells and a pair of independently controlled voltage pumps. The pair of voltage pumps is coupled for supplying both positive and negative voltage biases to the memory array during program and erase operations, such that a sum... Agent: Cypress Semiconductor Corporation

20120188825 - Memory devices having source lines directly coupled to body regions and methods: Memory devices, memory cell strings and methods of operating memory devices are shown. Configurations described include directly coupling an elongated body region to a source line. Configurations and methods shown should provide a reliable bias to a body region for memory operations such as erasing.... Agent:

20120188827 - Burst order control circuit: A burst order control circuit includes a signal transmitting unit transmitting a second address as first and second signals in response to a mode signal and a first address, a signal delay unit delaying a read command, the first signal, and the second signal to generate a delayed read command,... Agent:

20120188829 - Circuits, devices, systems, and methods of operation for capturing data signals: Embodiments of the invention describe driving data onto a bus. The embodiments include a data driver circuit having a data capture circuit coupled to the bus. The data capture circuit receives data relative to a write strobe signal and captures a first digit of the data responsive to a first... Agent: Micron Technology, Inc.

20120188828 - Data capture system and method, and memory controllers and devices: Embodiments of a data capture system and method may be used in a variety of devices, such as in memory controllers and memory devices. The data capture system and method may generate a first set of periodic signals and a second set of periodic signals that differs from the first... Agent: Micron Technology, Inc.

20120188830 - Semiconductor memory device correcting fuse data and method of operating the same: A semiconductor memory device and method of operating same are described. The semiconductor memory device includes a first anti-fuse array having a plurality of first anti-fuse elements that store first fuse data, a second anti-fuse array having a plurality of second anti-fuse elements that store error correction code (ECC) data... Agent: Samsung Electornics Co., Ltd.

20120188831 - Power-off apparatus, systems, and methods: Some embodiments include apparatus, systems, and methods having a voltage generator to generate a voltage, a memory cell including a storage node associated with a storage node voltage, and a power controller to provide a signal to the voltage generator such that the voltage generated by the voltage generator rises... Agent:

20120188832 - Memory channel having deskew separate from redrive: A memory module may have a redrive circuit having a plurality of redrive paths, a memory device, and a deskew circuit. The deskew circuit may be separate from the plurality of redrive paths. The deskew circuit may be coupled between the plurality of redrive paths and the memory device to... Agent:

20120188834 - Semiconductor memory device and memory system having the same: A semiconductor memory device is disclosed. The semiconductor device includes a memory cell array, a clock signal generator configured to receive an external clock signal from the outside of the memory device and output an internal clock signal, and a data output unit configured to receive an internal data signal... Agent:

20120188833 - Timing adjustment circuit for a memory interface and method of adjusting timing for memory interface: According to one embodiment, a timing adjustment circuit for a memory interface is presented. The circuit is provided with a gate circuit, an original gate signal generation circuit, a high impedance prevention unit, an impedance control unit and a gate leveling circuit. The gate circuit performs gating of a data... Agent: Kabushiki Kaisha Toshiba

20120188835 - Integrated circuit with staggered signal output: A memory controller having a time-staggered request signal output. A first timing signal is generated while a second timing signal is generated having a first phase difference relative to the first timing signal. An address value is transmitted in response to the first timing signal and a control value is... Agent:

20120188837 - Method of reading memory cell: A method for reading a memory cell (20) of a semiconductor memory (10) includes initiating a precharge or predischarge operation on a bit line (24) prior to arrival of a triggering edge of a clock signal (32) that initiates a read operation. A word line (22) is activated responsive to... Agent: Freescale Semiconductor, Inc

20120188836 - Semiconductor memory apparatus: A semiconductor memory apparatus includes a bit line sense amplifier unit and a driving voltage supply unit. The bit line sense amplifier unit senses and amplifies a signal provided from a memory cell using a pull-up driving voltage provided through a pull-up power line and a pull-down driving voltage provided... Agent: Hynix Semiconductor Inc.

20120188839 - Bank selection circuit and memory device having the same: A bank selection circuit includes a command latch unit configured to latch an input command at a time earlier than a rising edge of a clock by a setup time, a command decoder configured to decode a latched command and generate a row operation signal, a bank address latch unit... Agent:

20120188838 - Memory with word-line segment access: A memory comprises a row of bit cells, including a first plurality of bit cells and a second plurality of bit cells. A first word line segment driver is connected to the first plurality of bits cells. A second word line segment driver is connected to the second plurality of... Agent: Taiwan Semiconductor Manufacturing Co., Ltd.

  
07/19/2012 > 47 patent applications in 27 patent subcategories. category listing

20120182776 - Dram device with built-in self-test circuitry: A dynamic random access memory (DRAM) device includes a first and second integrated circuit (IC) die. The first integrated circuit die has test circuitry to generate redundancy information. The second integrated circuit die is coupled to the first integrated circuit die in a packaged configuration including primary storage cells and... Agent:

20120182777 - Memory module cutting off dm pad leakage current: A memory module includes: an ODT circuit on a memory device and including pull-up and pull-down resistors connected between pull-up and pull-down transistors. A data masking (DM) pad is provided in a tap region of the module board. A current leakage monitoring unit is also provided and receives a ground... Agent: Samsung Electronics Co., Ltd.

20120182780 - Memory system with multi-level status signaling and method for operating the same: A memory system includes a status circuit having a common status node electrically connected to a respective status pad of each of a plurality of memory chips. The memory system also includes a plurality of resistors disposed within the status circuit to define a voltage divider network for generating different... Agent: Sandisk Technologies Inc.

20120182778 - Semiconductor device including plural chips stacked to each other: Such a device is disclosed that includes a first semiconductor chip including a plurality of first terminals, a plurality of second terminals, and a first circuit coupled between the first and second terminals and configured to control combinations of the first terminals to be electrically connected to the second terminals,... Agent: Elpida Memory, Inc.

20120182779 - Semiconductor memory device: According to one embodiment, a nonvolatile memory device includes a substrate, an interconnect layer, a memory layer, a circuit layer, first and second contact interconnects. The interconnect layer is provided on the substrate and includes first and second interconnects. The memory layer is provided between the substrate and the interconnect... Agent: Kabushiki Kaisha Toshiba

20120182781 - Magnetic shift register memory device: In one embodiment, the invention is a magnetic shift register memory device. One embodiment of a memory cell includes a magnetic column including a plurality of magnetic domains, a reader coupled to the magnetic column, for reading data from the magnetic domains, a temporary memory for storing data read from... Agent: International Business Machines Corporation

20120182782 - Methods for testing unprogrammed otp memory: Methods for testing unprogrammed single transistor and two transistor anti-fuse memory cells include testing for connections of the cells to a bitline by comparing a voltage characteristic of a bitline connected to the cell under test to a reference bitline having a predetermined voltage characteristic. Some methods can use test... Agent: Sidense Corp.

20120182786 - Bidirectional resistive memory devices using selective read voltage polarity: A memory device includes a memory cell array including a plurality of memory cells, each including a bidirectional variable resistance element and an input/output circuit configured to determine a polarity for a read voltage to be applied to a selected memory cell among the plurality of memory cells and to... Agent: Samsung Electronics Co., Ltd.

20120182787 - Cross-point memory devices, electronic systems including cross-point memory devices and methods of accessing a plurality of memory cells in a cross-point memory array: Memory devices comprise a plurality of memory cells, each memory cell including a memory element and a selection device. A plurality of first (e.g., row) address lines can be adjacent (e.g., under) a first side of at least some cells of the plurality. A plurality of second (e.g., column) address... Agent: Micron Technology, Inc.

20120182785 - Memory unit and method of operating the same: A memory unit includes memory cells each having a memory element and a transistor, word lines and first and second bit lines, and a drive section. In performing setting operation for a first memory element located on one word line and in performing resetting operation for a second memory element... Agent: Sony Corporation

20120182783 - Programming an array of resistance random access memory cells using unipolar pulses: Subject matter disclosed herein relates to a memory device, and more particularly to programming a non-volatile memory device.... Agent: Numonyx B.v.

20120182784 - Semiconductor memory device: A semiconductor memory device according to an embodiment comprises a memory cell array configured from a plurality of row lines and column lines that intersect one another, and from a plurality of memory cells disposed at each of intersections of the row lines and column lines and each including a... Agent: Kabushiki Kaisha Toshiba

20120182789 - Memory device, semiconductor device, and detecting method: To provide a memory device which can perform verification operation for detecting a memory cell whose data holding time is shorter than a predetermined length, accurately in a short time. Each memory cell includes at least a first capacitor, a second capacitor, and a transistor which functions as a switching... Agent: Semiconductor Energy Laboratory Co., Ltd.

20120182791 - Semiconductor device and semiconductor memory device: A memory circuit is included. The memory circuit includes n field-effect transistors (n is a natural number of 2 or more) and n capacitors each including a pair of electrodes. A digital data signal is input to one of a source and a drain of the first field-effect transistor. One... Agent: Semiconductor Energy Laboratory Co., Ltd.

20120182790 - Semiconductor memory device: The memory capacity of a DRAM is enhanced. A semiconductor memory device includes a driver circuit including part of a single crystal semiconductor substrate, a multilayer wiring layer provided over the driver circuit, and a memory cell array layer provided over the multilayer wiring layer. That is, the memory cell... Agent: Semiconductor Energy Laboratory Co., Ltd.

20120182788 - Storage element, storage device, signal processing circuit, and method for driving storage element: A storage element capable of retaining data even after supply of power supply voltage is stopped is provided. In the storage element retaining data in synchronization with a clock signal, with the use of a capacitor and a transistor having a channel in an oxide semiconductor layer, the data can... Agent: Semiconductor Energy Laboratory Co., Ltd.

20120182792 - Biasing circuit and technique for sram data retention: A SRAM system includes: a SRAM cell array coupled between high and low supply nodes, a difference therebetween defining a data retention voltage (VDR) for a low power data retention mode; a main power switch coupling one of high and low supply nodes to a main power supply and disconnecting... Agent: Taiwan Semiconductor Manufacturing Co., Ltd.

20120182793 - Asymmetric silicon-on-insulator sram cell: A memory cell having N transistors including at least one pair of access transistors, one pair of pull-down transistors, and one pair of pull-up transistors to form a memory cell, wherein N is an integer at least equal to six, wherein each of the access transistors and each of the... Agent: International Business Machines Corporation

20120182794 - Multi-terminal phase change devices: Phase change devices, particularly multi-terminal phase change devices, include first and second active terminals bridged together by a phase-change material whose conductivity can be modified in accordance with a control signal applied to a control electrode. Structure allows application in which an electrical connection can be created between two active... Agent: Agate Logic Inc.

20120182795 - Emulation of static random access memory (sram) by magnetic random access memory (mram): A magnetic memory system includes a magnetic random access memory (MRAM) including a plurality of magnetic memory banks and operative to store data during a write operation initiated by a write command. The magnetic memory system further includes a first-in-first-out (FIFO) interface device coupled to the MRAM and including a... Agent: Avalanche Technology, Inc.

20120182796 - Storage element and memory device: A storage element includes a storage layer which has magnetization vertical to the film surface and of which the direction of magnetization changes, a magnetization fixed layer which has magnetization vertical to the film surface serving as a reference of information, and an insulating layer, and the direction of magnetization... Agent: Sony Corporation

20120182799 - Data path for multi-level cell memory, methods for storing and methods for utilizing a memory array: Memories, data paths, methods for storing, and methods for utilizing are disclosed, including a data path for a memory using multi-level memory cells to provide storage of multiple bits per memory cell. One such data path includes a bit mapping circuit and a data converter circuit. Such a bit mapping... Agent: Micron Technology, Inc.

20120182798 - Non-volatile semiconductor memory: A non-volatile semiconductor device has a memory cell array having electrically erasable programmable non-volatile memory cells, reprogramming and retrieval circuits that temporarily store data to be programmed in the memory cell array and sense data retrieved from the memory cell array. Each reprogramming and retrieval circuit has first and second... Agent: Kabushiki Kaisha Toshiba

20120182800 - Semiconductor memory device capable of preventing a shift of threshold voltage: A memory cell array is connected to a word line and a bit line, and configured so that a plurality of memory cells storing one level of n levels (n is a natural number more than 4) in one memory cell are arrayed in a matrix. A control circuit controls... Agent:

20120182797 - Sense operation in a memory device: Methods for sensing and memory devices are disclosed. One such method for sensing determines a threshold voltage of an n-bit memory cell that is adjacent to an m-bit memory cell to be sensed. A control gate of the m-bit memory cell to be sensed is biased with a sense voltage... Agent: Micron Technology, Inc.

20120182801 - Memory architecture of 3d nor array: A 3D memory device includes a plurality of ridge-shaped stacks of memory cells. Word lines are arranged over the stacks of memory cells. Bit lines structures are coupled to multiple locations along the stacks of memory cells. Source line structures are coupled to multiple locations along each of the semiconductor... Agent: Macronix International Co., Ltd.

20120182802 - Memory architecture of 3d array with improved uniformity of bit line capacitances: A 3D integrated circuit memory array has a plurality of plane positions. Multiple bit line structures have a multiple sequences of multiple plane positions. Each sequence characterizes an order in which a bit line structure couples the plane positions to bit lines. Each bit line is coupled to at least... Agent: Macronix International Co., Ltd.

20120182803 - Non-volatile semiconductor memory device capable of improving failure-relief efficiency: According to one embodiment, a non-volatile semiconductor memory device includes a memory cell array and a row decoder. The memory cell array has NAND strings as a physical block, and word lines respectively connected to memory cells included in the NAND strings. The row decoder includes latch circuits and a... Agent:

20120182804 - Architecture for a 3d memory array: Techniques are described herein for compensating for threshold voltage variations among memory cells in an array by applying different bias conditions to selected bit lines. Techniques are also described herein for connecting global bit lines to a variety of levels of memory cells in a 3D array, to provide for... Agent: Macronix International Co., Ltd.

20120182806 - Memory architecture of 3d array with alternating memory string orientation and string select structures: A 3D memory device includes a plurality of ridge-shaped stacks, in the form of multiple strips of conductive material separated by insulating material, arranged as bit lines which can be coupled through decoding circuits to sense amplifiers. Diodes are connected to the bit lines at either the string select of... Agent: Macronix International Co., Ltd.

20120182805 - Strings of memory cells having string select gates, memory devices incorporating such strings, and methods of accessing and forming the same: Strings of memory cells having a string select gate configured to selectively couple ends of a string to a data line and a source line concurrently, memory devices incorporating such strings and methods for accessing and forming such strings are provided. For example, non-volatile memory devices are disclosed that utilize... Agent: Micron Technology, Inc.

20120182809 - Data state-dependent channel boosting to reduce channel-to-floating gate coupling in memory: In a programming operation, selected storage elements on a selected word line are programmed while unselected storage elements on the selected word line are inhibited from programming by channel boosting. To provide a sufficient but not excessive level of boosting, the amount of boosting can be set based on a... Agent:

20120182808 - Memory device, manufacturing method and operating method of the same: A memory device, a manufacturing method and an operating method of the same are provided. The memory device includes a substrate, stacked structures, a channel element, a dielectric element, a source element, and a bit line. The stacked structures are disposed on the substrate. Each of the stacked structures includes... Agent: Macronix International Co., Ltd.

20120182807 - Three-dimensional stacked and-type flash memory structure and methods of manufacturing and operating the same hydride: A 3D stacked AND-type flash memory structure comprises several horizontal planes of memory cells arranged in a three-dimensional array, and each horizontal plane comprising several word lines and several of charge trapping multilayers arranged alternately, and the adjacent word lines spaced apart from each other with each charge trapping multilayer... Agent: Macronix International Co., Ltd.

20120182810 - Methods, devices, and systems for adjusting sensing voltages in devices: The present disclosure includes methods, devices, and systems for adjusting sensing voltages in devices. One or more embodiments include memory cells, and a controller configured to perform a sense operation on the memory cells using a sensing voltage to determine a quantity of the memory cells having a threshold voltage... Agent: Micron Technology, Inc.

20120182811 - Method of erasing a flash eeprom memory: A method for erasing a flash EEPROM memory device is disclosed. The memory device has a first semiconductor region of one conductivity type formed within a second semiconductor region of an opposite conductivity type, source and drain regions formed from a semiconductor layer of the opposite conductivity type in the... Agent:

20120182812 - Semiconductor memory device and method of operating the same: A semiconductor memory device that may perform a second operation during a first operation comprises a command decoder for generating a decoded command signal, a suspend pulse and a resume pulse, and a storage unit for storing the decoded address signal, the decoded command signal and a data signal in... Agent: Hynix Semiconductor Inc.

20120182813 - Power supply circuit and semiconductor memory device including the power supply circuit: According to one embodiment, a power supply circuit, which generates a power supply voltage which is applied to a memory cell array including a plurality of memory cells disposed at intersections between a plurality of word lines and a plurality of bit lines, comprises a first boost circuit configured to... Agent:

20120182814 - Programming circuit using antifuse: A programming circuit using an antifuse includes a fuse signal generation unit including an antifuse which connects a node with a low voltage in response to a test address when the node is driven to a level of a high voltage, and configured to output a signal of the node... Agent: Hynix Semiconductor Inc.

20120182815 - Memory devices having controllers that divide command signals into two signals and systems including such memory devices: A memory device using error correcting code and a system including the same are provided. The memory device includes a memory cell array including a plurality of bit lines and a plurality of memory cells; an access block for accessing the memory cell array; and a controller block for receiving... Agent: Samsung Electronics Co., Ltd.

20120182817 - Redundant memory array for replacing memory sections of main memory: Memories and methods for replacing memory sections of a main memory array by mapping memory addresses for an entire main memory section to at least one memory section of a redundant memory array. One such memory includes a fuse block having programmable elements configured to be programmed to identify main... Agent: Micron Technology, Inc.

20120182816 - Semiconductor device and manufacturing method thereof: Such a device is disclosed that includes: a row redundancy circuit and a column redundancy circuit for replacing defective sub word lines and defective bit lines included in a memory cell array, respectively; first and second electrical fuse circuits that store the addresses of the defective sub word lines and... Agent:

20120182818 - Low power and high speed sense amplifier: A sense amplifier circuit includes a precharge circuit configured to precharge a bit line coupled to a sensing node in response to a precharge control signal and a sense output circuit. The sense output circuit includes a sense output inverter coupled to the sensing node. The sense output inverter is... Agent: Taiwan Semiconductor Manufacturing Co., Ltd.

20120182819 - Recycling charges: A circuit includes a first node; a second node; a first PMOS transistor having a source coupled to the first node, a drain coupled to a first control transistor, and a gate driven by a first voltage; and a first NMOS transistor having a source coupled to the second node,... Agent: Taiwan Semiconductor Manufacturing Company, Ltd.

20120182820 - Local power domains for memory sections of an array of memory: Memories, memory arrays, and methods for selectively providing electrical power to memory sections of a memory array are disclosed. A memory array can be operated by decoupling row decoder circuitry from receiving electrical power while the memory array is not being accessed. Portions of the memory array to be accessed... Agent: Micron Technology, Inc.

20120182821 - Memory system components that support error detection and correction: A memory system that includes a memory device and a memory bank. During operation, the memory device receives a request to concurrently access a data word at a first row in a first storage region of the memory bank and error information associated with the data at a second row... Agent: Rambus Inc.

20120182822 - Semiconductor device including plural chips stacked to each other: Such a device is disclosed that includes a first chip outputting a bank address signal and an active signal, and a plurality of second chips stacked on the first chip. Each of the second chips includes a plurality of memory banks each selected based on the bank address signal. Selected... Agent: Elpida Memory, Inc.

  
07/12/2012 > 28 patent applications in 22 patent subcategories. category listing

20120176829 - Semiconductor memory device with ferroelectric device and refresh method thereof: A semiconductor memory device with a ferroelectric device comprises a channel region, a drain region and a source region formed in a substrate, a ferroelectric layer formed over the channel region, and a word line formed over the ferroelectric layer. A different channel resistance is induced to the channel region... Agent:

20120176832 - Access signal adjustment circuits and methods for memory cells in a cross-point array: Embodiments of the invention relate generally to semiconductors and memory technology, and more particularly, to systems, integrated circuits, and methods to generate access signals to facilitate memory operations in scaled arrays of memory elements, such as memory implemented in third dimensional memory technology formed BEOL directly on top of a... Agent: Unity Semiconductor Corporation

20120176833 - Electronic device with a programmable resistive element and a method for blocking a device: One or more embodiments relate to an electronic device comprising a circuitry and a programmable resistive element. The programmable resistive element comprises a first and a second state, wherein the programmable resistive element is configured to allow switching from the second state into the first state in response to a... Agent: Infineon Technologies Ag

20120176831 - Resistive random access memory with low current operation: A memory cell in a 3-D read and write memory device has two bipolar resistance-switching layers with different respective switching currents. A low current resistance-switching layer can be switched in set and reset processes while a high current resistance-switching layer remains in a reset state and acts as a protection... Agent:

20120176830 - Variable resistance memory devices using read mirror currents: A nonvolatile memory device includes a variable resistance memory element and a read circuit coupled to the variable resistance memory element at a first signal node and configured to provide a read current to the variable resistance memory element via the first signal node, to a provide a mirror current... Agent:

20120176834 - Variable resistance nonvolatile memory device: Each of basic array planes has a first via group that interconnects only even-layer bit lines in the basic array plane, and a second via group that interconnects only odd-layer bit lines in the basic array plane, the first via group in a first basic array plane and the second... Agent:

20120176835 - Temperature sensor, method of manufacturing the temperature sensor, semiconductor device, method of manufacturing the semiconductor device, and method of controlling the semiconductor device: A disclosed temperature sensor includes a charge trap structure including a silicon oxide film formed on a substrate; an aluminum oxide film that is formed on the silicon oxide film, wherein oxygen is injected into the aluminum oxide film from an upper surface thereof; and an electrode formed on the... Agent: Tokyo Electron Limited

20120176837 - Memory cell sensing using negative voltage: Embodiments of the present disclosure provide methods, devices, modules, and systems for memory cell sensing using negative voltage. One method includes applying a negative read voltage to a selected access line of an array of memory cells, applying a pass voltage to a number of unselected access lines of the... Agent: Micron Technology, Inc.

20120176838 - Reducing effects of program disturb in a memory device: A method for programming that biases a selected word line with a programming voltage. An unselected word line on the source side and an unselected word line on the drain side of the selected word line are biased at a pass voltage that is less than the normal pass voltage.... Agent: Micron Tecnology, Inc.

20120176839 - Nonvolatile semiconductor memory having a word line bent towards a select gate line side: A nonvolatile semiconductor memory includes a cell unit having a select gate transistor and a memory cell connected in series, a select gate line connected to the select gate transistor, and a word line connected to the memory cell. One end of the word line is bent to the select... Agent:

20120176840 - Combined memories in integrated circuits: Combined memories in integrated circuits are described, including determining a first requirement for logic blocks, determining a second requirement for memory blocks including a vertical configuration for the memory bocks, and compiling a design for the integrated circuit using the first requirement and the second requirement. The memory blocks may... Agent: Unity Semiconductor Corporation

20120176841 - Flexible 2t-based fuzzy and certain matching arrays: A novel NVM-based 2T or 2nT NAND-cell for a NAND-array for PLD, PAL and matching functions is disclosed. The preferable NVM cell can be ROM or Flash. The 2T flash cell preferably uses FN for both program and erase operation, while 2T ROM cell preferably to use phosphorus for ROM... Agent: Aplus Flash Technology, Inc.

20120176842 - Memory system: The present invention provides a memory system which contributes to improvement in efficiency of a data process accompanying a memory access. A memory system has a rewritable nonvolatile memory, a buffer memory, and a controller. The controller controls, in response to an access request from an external apparatus, first data... Agent: Solid State Storage Solutions LLC

20120176843 - Memories and methods of programming memories: Apparatus and methods for adjusting programming for upper pages of memories are disclosed. In at least one embodiment, a threshold voltage distribution upper limit is determined after a single programming pulse for lower page programming, and upper page programming start voltages are adjusted based on the determined upper limit of... Agent:

20120176836 - Non-volatile semiconductor memory device: According to one embodiment, a non-volatile semiconductor memory device comprises memory strings. Each memory string comprises a semiconductor layer, control gates, a first selection gate, and a second selection gate. A semiconductor layer comprises a pair of pillar portions which extend in a vertical direction to a substrate, and a... Agent:

20120176844 - Read conditions for a non-volatile memory (nvm): A method and memory are provided for determining a read reference level for a plurality of non-volatile memory cells. The method includes: performing a program operation of the plurality of non-volatile memory cells; determining a program level of a least programmed memory cell of the plurality of memory cells; performing... Agent:

20120176845 - Techniques for controlling a direct injection semiconductor memory device: Techniques for controlling a direct injection semiconductor memory device are disclosed. In one particular exemplary embodiment, the techniques may be realized as a method for controlling a direct injection semiconductor memory device comprising applying a first voltage potential to a first region via a bit line, applying a second voltage... Agent: Micron Technology, Inc.

20120176846 - Threshold voltage digitizer for array of programmable threshold transistors: A method and system for determining a respective threshold voltage of each of a plurality of transistors in a memory array. The method includes: applying a ramp voltage to gates of the plurality of transistors, wherein the ramp voltage is configured to increase based on an incrementing digital code; as... Agent:

20120176847 - Methods and apparatus for voltage sensing and reporting: Semiconductor devices comprising at least one voltage sensor for sensing an operating voltage associated with an operational circuit of the semiconductor device. The at least one voltage sensor is configured to generate a signal indicative of a state of the operating voltage. Methods of monitoring a voltage in a semiconductor... Agent: Micron Technology, Inc.

20120176848 - Semiconductor memory device and method for generating bit line equalizing signal: A bit line equalizing signal generator of a semiconductor memory device uses a supply voltage and a pumping voltage in stages during a period where a bit line equalizing signal is enabled, thereby enhancing an equalizing speed and an active speed while minimizing power consumption. The semiconductor memory device includes... Agent:

20120176849 - Semiconductor apparatus and memory system including the same: A semiconductor memory apparatus includes one or more semiconductor chips configured to have predetermined capacity and structure; and a signal level control unit configured to control levels of external signals, which are input to the one or more semiconductor chips, in order to realize various capacities and structures using the... Agent: Hynix Semiconductor Inc.

20120176850 - Column address strobe write latency (cwl) calibration in a memory system: Column address strobe write latency (CWL) calibration including a method for calibrating a memory system. The method includes entering a test mode at a memory device and measuring a CWL at the memory device. A difference between the measured CWL and a programmed CWL is calculated. The calculated difference is... Agent: International Business Machines Corporation

20120176851 - Methods and memory devices for repairing memory cells: Methods and memory devices for repairing memory cells are discloses, such as a memory device that includes a main array having a plurality of sections of memory cells. One such main array includes a plurality of sets of input/output lines, each of which may be coupled to a respective plurality... Agent: Micron Technology, Inc

20120176852 - Semiconductor memory device and method of testing the same: A device and a method controlling the device are provided. A first command is supplied to the device in synchronization with a clock signal of a first frequency. The first command is to have the device perform a first operation. The frequency of the clock signal is changed from the... Agent: Elpida Memory, Inc.

20120176853 - Refresh control circuit, memory apparatus and refresh control method using the same: A memory apparatus is configured to generate refresh addresses with different values in response to one refresh command and an address, and perform a plurality of refresh operations with time differences in response to the refresh addresses. Herein, the refresh operations are performed within a refresh row cycle time.... Agent: Hynix Semiconductor Inc.

20120176855 - Card and host device: A host device is configured to read and write information from and into a card and to supply a supply voltage that belongs to a first voltage range or a second voltage range which is lower than the first voltage range, and issues a voltage identification command to the card.... Agent:

20120176854 - State-monitoring memory element: Embodiments of the invention relate to a state-monitoring memory element. The state-monitoring memory element may be implemented by degrading an input voltage supply to the state-monitoring memory element across a diode and/or a transistor. One or more current sources may be used to stress the state-monitoring memory element. A logic... Agent: Cypress Semiconductor Corporation

20120176856 - Memory circuits, systems, and method of interleavng accesses thereof: An interleaved memory circuit includes a memory bank including at least one first memory cell for storing a charge representative of a first datum, the first memory cell being coupled with a first word line and a first bit line. The interleaved memory circuit further includes a local control circuit... Agent: Taiwan Semiconductor Manufacturing Company, Ltd.

  
07/05/2012 > 57 patent applications in 30 patent subcategories. category listing

20120170344 - Content addressable memory: An entry including multiple bits of unit cells each storing data bit is coupled to a match line. The match line is supplied with a charging current having a restricted current value smaller than a match line current flowing in a one-bit miss state in one entry, but larger than... Agent: Renesas Electronics Corporation

20120170346 - Memory system with sectional data lines: The system includes multiple sets of local data lines in one or more routing metal layers below the three-dimensional memory array and multiple sets of global data lines in one or more top metal layers above the three-dimensional memory array. Each set of one or more blocks include one set... Agent:

20120170347 - Memory system with sectional data lines: The system includes multiple sets of local data lines in one or more routing metal layers below the three-dimensional memory array and multiple sets of global data lines in one or more top metal layers above the three-dimensional memory array. Each set of one or more blocks include one set... Agent:

20120170345 - Stacked semiconductor device and method of manufacturing the same: The stacked semiconductor device including a first chip, a second chip positioned on the first chip, the second chip being connected to a plurality of first penetration electrodes and including a first memory and a memory controller that are each controlled by the first chip, and a second memory positioned... Agent:

20120170349 - Ferroelectric memory with shunt device: A ferroelectric memory device includes a shunt switch configured to short both sides of the ferroelectric capacitor of the ferroelectric memory device. The shunt switch is configured therefore to remove excess charge from around the ferroelectric capacitor prior to or after reading data from the ferroelectric capacitor. By one approach,... Agent: Texas Instruments Incorporated

20120170348 - Ferroelectric memory write-back: A self-timed sense amplifier read buffer pulls down a pre-charged high global bit line, which then feeds data into a tri state write back buffer that is connected directly to the bit line. The bit line provides charge to a ferroelectric capacitor to write a logical “one” or “zero” while... Agent: Texas Instruments Incorporated

20120170350 - Method and apparatus pertaining to a ferro-magnetic random access memory: An FRAM device can comprise a sense amplifier, at least a first bitcell, a first control line, and a second control line. The first bitcell can have a bit line that connects to the sense amplifier via a first isolator and a complimentary bit line that connects to the sense... Agent: Texas Instruments Incorporated

20120170351 - Method and apparatus pertaining to a ferro-magnetic random access memory: An FRAM device can comprise a sense amplifier and at least a first bitcell. The first bitcell can have a bit line and a complimentary bit line that connects to the sense amplifier. A first precharge circuit responds to a first control signal during a test mode of operation to... Agent: Texas Instruments Incorporated

20120170353 - Nonvolatile memory device and method for programming the same: A method for programming a nonvolatile memory device according to the present invention includes a step of detecting an excessively low resistance cell from among a plurality of memory cells (11) (S101); a step of changing the resistance value of a load resistor (121) to a second resistance value smaller... Agent:

20120170352 - Thermo programmable resistor based rom: An integrated circuit is formed having an array of memory cells located in the dielectric stack above a semiconductor substrate. Each memory cell has an adjustable resistor and a heating element. A dielectric material separates the heating element from the adjustable resistor. The heating element alters the resistance of the... Agent: Stmicroelectronics Pte Ltd.

20120170354 - Apparatus and a method: An apparatus including a first electrode; a second electrode including graphene; and a dielectric between the first electrode and the second electrode; input circuitry configured to change a charge state of the dielectric by causing electric charges to be trapped in the dielectric; and output circuitry configured to detect a... Agent: Nokia Corporation

20120170356 - Semiconductor memory device with hierarchical bitlines: A dynamic random access memory (DRAM) device has a hierarchical bitline structure with local bitlines and global bitlines formed on different metal layers. The local bitlines are separated into a plurality of local bitline sections, and bitline isolation switches are configured to connect or disconnect the local bitline sections to... Agent: Rambus Inc.

20120170355 - Storage element, storage device, and signal processing circuit: A signal processing circuit whose power consumption can be suppressed is provided. In a period during which a power supply voltage is not supplied to a storage element, data stored in a first storage circuit corresponding to a nonvolatile memory can be held by a first capacitor provided in a... Agent: Semiconductor Energy Laboratory Co., Ltd.

20120170357 - Method and system for providing multiple logic cells in a single stack: A method and system for providing a magnetic junction usable in a magnetic device are described. The magnetic junction includes a pinned layer, a plurality of nonmagnetic spacer layers, and a plurality of free layers. The free layers are interleaved with the nonmagnetic spacer layers. A first nonmagnetic spacer layer... Agent: Grandis, Inc.

20120170358 - Mram cell structure: Disclosed herein is an improved memory device, and related methods of manufacturing, wherein the area occupied by a conventional landing pad is significantly reduced to around 50% to 10% of the area occupied by conventional landing pads. This is accomplished by removing the landing pad from the cell structure, and... Agent: Taiwan Semiconductor Manufacturing Company, Ltd.

20120170359 - Phase change memory with fast write characteristics: A memory device including programmable resistance memory cells, including electrically pre-stressed target memory cells. The pre-stressed target memory cells have one of a lower voltage transition threshold, a shorter duration set interval and a longer reset state retention characteristic. Biasing circuitry is included on the device configured to control the... Agent: Macronix International Co., Ltd.

20120170360 - Semiconductor memory device: A semiconductor memory device is disclosed. The semiconductor memory device converts a sequentially-changing step voltage into a current so as to provide a write current, and minimizes the influence of a threshold voltage variation caused by fabrication deviation, such that it can be stably operated. The semiconductor memory device includes... Agent: Hynix Semiconductor Inc.

20120170361 - Low-cost non-volatile flash-ram memory: A flash-RAM memory includes non-volatile random access memory (RAM) formed on a monolithic die and non-volatile page-mode memory formed on top of the non-volatile RAM, the non-volatile page-mode memory and the non-volatile RAM reside on the monolithic die. The non-volatile RAM is formed of stacks of magnetic memory cells arranged... Agent: Avalanche Technology, Inc.

20120170362 - Method and system for providing dual magnetic tunneling junctions usable in spin transfer torque magnetic memories: A method and system for providing a magnetic junction usable in a magnetic memory are described. The magnetic junction includes first and second pinned layers, first and second nonmagnetic spacer layers, and a free layer. The first pinned layer has a first pinned layer magnetic moment and is nonmagnetic layer-free.... Agent: Samsung Electronics Co., Ltd.

20120170363 - Method for increasing program speed and control read windows for multi-level cell non-volatile memory: A method of programming a memory device comprising a plurality of bits that each have a plurality of program states in which each program state has a corresponding program verify (PV) level may include applying a first sequence of program shots to program fastest bits of the memory device utilizing... Agent: Macronix International Co., Ltd.

20120170364 - Method of programming a nonvolatile memory device: In method of programming a nonvolatile memory device including a plurality of multi-level cells that store multi-bit data according to example embodiments, a least significant bit (LSB) program operation is performed to program LSBs of the multi-bit data in the plurality of multi-level cells. A most significant bit (MSB) program... Agent:

20120170365 - Non-volatile memory devices and systems including the same, and methods of programming non-volatile memory devices: A method is for programming a memory block of a non-volatile memory device. The non-volatile memory device is operatively connected to a memory controller, and the memory block defined by a plurality of word lines located between a string select line and a common source line corresponding to the string... Agent: Samsung Electronics Co., Ltd.

20120170367 - Semiconductor device and method of generating voltages using the same: A semiconductor device includes a register unit for storing additional bits associated with a command signal and outputting a selected additional bit corresponding to a received address; a combination circuit for combining received control bits and the selected additional bit, and outputting enable signals based on the combined bits, where... Agent: Hynix Semiconductor Inc.

20120170366 - Semiconductor memory device and method of operating the same: A method of operating a semiconductor memory device includes performing a first program loop including a first program operation and a first verification operation in order to store a lower bit data of n-bit data in memory cells coupled to a page, performing a subprogram loop for memory cells of... Agent: Hynix Semiconductor Inc.

20120170368 - Nonvolatile memory device and method for fabricating the same: Provided are a nonvolatile memory device and a method for fabricating the same, which can secure the structural stability of a three-dimensional nonvolatile memory device. The nonvolatile memory device includes one or more columnar channel plugs, a plurality of word lines and a plurality of dielectric layers stacked alternately to... Agent:

20120170369 - Nonvolatile memory devices: Nonvolatile memory devices including memory cell arrays with first bit line regions and common source tapping regions which are alternately disposed on a substrate along a direction, a page buffer including second bit line regions aligned with the first bit line regions and page buffer tapping regions aligned with the... Agent: Samsung Electronics Co., Ltd.

20120170370 - Nonvolatile memory device and nonvolatile memory system employing same: A nonvolatile memory device comprises a memory cell array, a row selection circuit and a voltage generator. The memory cell array comprises a first dummy memory cell, a second dummy memory cell, and a NAND string comprising a plurality of memory cells coupled in series between a string selection transistor... Agent: Samsung Electronics Co., Ltd.

20120170372 - Memory device biasing method and apparatus: Memory devices and methods are disclosed, such as those facilitating data line shielding by way of capacitive coupling with data lines coupled to a memory string source line. For example, alternating data lines are sensed while adjacent data lines are coupled to a common source line of the data lines... Agent: Micron Technology, Inc.

20120170371 - Programming method of non-volatile memory device: A programming method of a non-volatile memory device that includes a string of memory cells with a plurality of floating gates and a plurality of control gates disposed alternately, wherein each of the memory cells includes one floating gate and two control gates disposed adjacent to the floating gate and... Agent:

20120170374 - Nonvolatile memory device and related programming method: A nonvolatile memory device programs a memory cell by performing a plurality of program loops each comprising a program operation and a program verifying operation. Where the program verifying operation in one program loop determines that the memory cell has been successfully programmed to a target state, a soft-programming operation... Agent: Samsung Electronics Co., Ltd.

20120170373 - Semiconductor memory device and program methods thereof: Programming a semiconductor memory device includes: performing a program loop using a blind program operation until the selected cell threshold voltages reach a first verification level; upon detecting a cell having the threshold voltage reaching the first verification level, verifying whether a cell having the threshold voltage reached a second... Agent: Hynix Semiconductor Inc.

20120170375 - Vertical nonvolatile memory devices and methods of operating same: Integrated circuit memory devices include a plurality of vertically-stacked strings of nonvolatile memory cells having respective vertically-arranged channel regions therein electrically coupled to an underlying substrate. A control circuit is provided, which is configured to drive the vertical channel regions with an erase voltage that is ramped from a first... Agent:

20120170376 - Semiconductor memory device and operating method thereof: A semiconductor memory device includes a plurality of memory cells, including an N well formed within a P type region and a P well formed within the N well, a peripheral circuit configured to perform a program, program verify, read, erase, or erase verify operation on memory cells selected from... Agent: Hynix Semiconductor Inc.

20120170377 - Local word line driver and flash memory array device thereof: In a local word line driver of an NOR flash memory and its flash memory array device, the local word line driver is provided for driving a local word line in a sector of a memory array, and the local word line driver has two transistors including a first transistor... Agent: Eon Silicon Solution Inc.

20120170378 - Read methods of semiconductor memory device: A read method of a semiconductor memory device includes performing a read operation on target cells by using a first read voltage, terminating the read operation on the target cells if, as a result of the read operation on the target cells, error correction is feasible, performing a read operation... Agent:

20120170381 - Nonvolatile semiconductor memory device: According to one embodiment, a nonvolatile semiconductor memory device includes a memory cell transistor, a word line, a row decoder, a sense amplifier which determines the data in the memory cell transistor via the bit line, a first bit line clamp transistor connected in series between the bit line and... Agent:

20120170380 - Semiconductor memory device: According to one embodiment, a semiconductor memory device includes a memory cell array, a first detecting circuit, a second detecting circuit, a switching circuit and a recovery control circuit. The first detecting circuit outputs a first detection signal which shows whether an externally supplied external power supply is equal to... Agent:

20120170379 - Semiconductor memory device and method of operating the same: A semiconductor memory device according to an aspect of the present disclosure includes a first page buffer coupled to a first even bit line and a first odd bit line, a second page buffer coupled to a second even bit line and a second odd bit line, and a controller... Agent:

20120170384 - Integrated circuit, memory system, and operation method thereof: An integrated circuit includes an input pad configured to receive a low-speed signal and a high-speed signal, a high-speed buffer coupled to the input pad, a low-speed buffer coupled to the input pad, a strobe input unit configured to receive a strobe signal for indicating an input of the high-speed... Agent:

20120170383 - Integrated circuit, system including the same, memory, and memory system: A system includes integrated circuit chip including a first buffer configured to receive signals and a second buffer configured to receive signals, wherein the first buffer receives signals of a higher frequency than the second buffer, a controller chip configured to control the integrated circuit chip, an I/O channel formed... Agent:

20120170385 - Output driver and electronic system comprising same: An output driver comprises a pull-up circuit that pulls up an output node to a supply voltage in N successive intervals in response to N pull-up control signals having different phases and a pull-down circuit that pulls down the output node to a ground voltage in M successive intervals in... Agent: Samsung Electronics Co., Ltd.

20120170382 - Semiconductor memory device, test circuit, and test operation method thereof: A semiconductor memory device includes a plurality of banks, each including a plurality of first memory cells and a plurality of second memory cells, a first input/output unit configured to transfer first data between the first memory cells and a plurality of first data pads, a second input/output unit configured... Agent:

20120170386 - Hybrid read scheme for multi-level data: Some aspects of the present disclosure relate to a read circuit that uses a hybrid read scheme as set forth herein. In this hybrid read scheme, a state machine, at a first time in the read operation, sets a reference signal SRef to a first reference value to induce determination... Agent: Infineon Technologies Ag

20120170387 - Device for generating a test pattern of a memory chip and method thereof: A method of generating a test pattern of a memory chip includes generating and outputting a pattern enabling signal according to a first pattern signal and a second pattern signal, generating and outputting a first pre-input-output signal and a second pre-input-output signal according to a memory bank signal, a section... Agent:

20120170388 - Sram including write assist circuit and method of operating same: A static random access memory (SRAM) is described and includes; a bit cell connected with a word line, connected between a bit line and a complementary bit line, and receiving an internal voltage from a write assist circuit. The write assist circuit includes a power control circuit that charges/discharges an... Agent: Samsung Electronics Co., Ltd.

20120170389 - Memory controller for strobe-based memory systems: A memory controller for strobe-based memory systems is disclosed. The memory controller comprises a circuit to generate a control signal having a predetermined timing relationship with respect to a first clock signal, a circuit to receive the control signal, and a receiver to sample the read data in response to... Agent:

20120170392 - Internal voltage generation circuit and semiconductor integrated circuit: A semiconductor integrated circuit includes first and second bank groups, a first internal voltage control unit configured to generate a first enable pulse which is enabled when a first read operation or a first write operation is performed for banks included in the first bank group, and a first internal... Agent: Hynix Semiconductor Inc.

20120170391 - Memory device with boost compensation: A memory circuit includes a memory cell configured to be re-writable. A write enable circuit is configured to enable writing a signal via a pair of bit lines to the memory cell depending on a write signal. A charge supply circuit is configured to supply a charge to at least... Agent: Stmicroelectronics Pvt. Ltd.

20120170393 - Programmable delay introducing circuit in self-timed memory: Delays are introduced in self-timed memories by introducing a capacitance on the path of a signal to be delayed. The capacitances are realized by using idle-lying metal layers in the circuitry. The signal to be delayed is connected to the idle-lying capacitances via programmable switches. The amount of delay introduced... Agent: Stmicroelectronics Pvt.ltd.

20120170390 - Read stability of a semiconductor memory: A semiconductor memory storage device is disclosed. The memory comprises a plurality of storage cells for storing data each storage cell comprising an access control device for providing the storage cell with access to or isolation from a data access port in response to an access control signal, access control... Agent: Arm Limited

20120170394 - Column address circuit of semiconductor memory device and method of generating column addresses: The column address circuit of a semiconductor memory device according to an aspect of the present disclosure includes a column address generation circuit configured to generate an internal dummy clock in response to a data output enable signal, generate an internal clock in response to a read enable signal, generate... Agent:

20120170395 - Data flow control in multiple independent port: A system includes a memory controller and a plurality of memory devices connected in-series that communicate with the memory controller. Each of the memory devices has multiple independent serial ports for receiving and transmitting data. The memory controller a device address (DA) or ID number for designating a device that... Agent: Mosaid Technologies Incorporated

20120170396 - Semiconductor memory device: A semiconductor memory device includes a temperature sensor configured to generate a low-temperature signal which is enabled at below first set temperature and a high-temperature signal which is enabled at above second set temperature; a start signal generator configured to receive a refresh command and generate a start signal according... Agent: Hynix Semiconductor Inc.

20120170397 - Sensor node enabled to manage power individually: A sensor node is provided. The sensor node regulates the power supplied to memories of a memory unit individually and the power supplied to a transmitter and a receiver of an RF transceiver individually. Thus, the sensor node can minimize its power consumption.... Agent: Korea Electronics Technology Institute

20120170398 - Column address counter circuit of semiconductor memory device: The column address counter circuit of a semiconductor memory device includes at least one lower bit counter unit configured to generate a first bit of a column address by counting an internal clock, where the first bit is not a most significant bit of the column address, and a most... Agent:

20120170399 - Multi-column addressing mode memory system including an integrated circuit memory device: A memory system includes a master device, such as a graphics controller or processor, and an integrated circuit memory device operable in a dual column addressing mode. The integrated circuit memory device includes an interface and column decoder to access a row of storage cells or a page in a... Agent: Rambus Inc.

20120170400 - Memory devices and accessing methods thereof: A memory device is provided. The memory device comprises a plurality of memory chips. The plurality of memory chips receive an input address code and alternately operate in an active mode. Each memory chip receives a selection signal and operates according to an internal address counter code. For each memory... Agent:

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