Static information storage and retrieval patents - Monitor Patents
FreshPatents.com Logo    FreshPatents.com icons
Monitor Keywords Patent Organizer File a Provisional Patent Browse Inventors Browse Industry Browse Agents



USPTO Class 365  |  Browse by Industry: Previous - Next | All     monitor keywords
06/2012 | Recent  |  14:  |  |  | Sep | Aug | Jul | Jun | May | Apr | Mar | Feb | Jan | 13: Dec | Nov | Oct | Sep | Aug | Jul | Jun | May | Apr | Mar | Feb | Jan | 12: Dec | Nov | Oct | Sep | Aug | July | June | May | April | Mar | Feb | Jan | 11: Dec | Nov | Oct | Sep | Aug | Jul | Jun | May | Apr | Mar | Feb | Jan | 10: Dec | Nov | Oct | Sep | Aug | Jul | Jun | May | Apr | Mar | Feb | Jan |  | 09: Dec | Nov | Oct | Sep | Aug | Jl | Jn | May | Apr | Mar | Fb | Jn |  | 2008 | 2007 |

Static information storage and retrieval June invention type 06/12

Below are recently published patent applications awaiting approval from the USPTO. Recent week's RSS XML file available below.
Listing for abstract view: USPTO application #, Title, Abstract excerpt,Patent Agent. Listing format for list view: USPTO National Class full category number, title of the patent application.
  
06/28/2012 > 57 patent applications in 31 patent subcategories. invention type

20120163059 - Conditionally precharged dynamic content addressable memory: A conditionally precharged content addressable memory (CAM) includes forcing a mismatch on a matchline of the CAM if a data entry in the CAM is invalid. The matchline of the CAM is precharged only if the data entry is valid.... Agent: Advanced Micro Devices, Inc.

20120163060 - Semiconductor memory device: A semiconductor memory device comprises a semiconductor substrate; a plurality of memory cell arrays stacked on the semiconductor substrate, each memory cell array including a plurality of first lines paralleled with each other, a plurality of second lines paralleled with each other and formed crossing the first lines, and a... Agent: Kabushiki Kaisha Toshiba

20120163061 - Memory array having local source lines: A memory is provided that simplifies a fabrication process and structure by reducing the number of source lines and bitlines accessible to circuitry outside of the memory array. The memory has first and second row groups comprising a plurality of memory elements each coupled to one each of a plurality... Agent: Everspin Technologies, Inc.

20120163062 - Memory device and memory access method: Provided is a memory device in which the circuit structure is simplified while the functions of a memory including an OTP memory and a memory including a pseudo-MTP memory are maintained. A memory device includes a plurality of memory sets each including a mark bit storage area for storing a... Agent: Seiko Instruments Inc.

20120163063 - Complementary read-only memory (rom) cell and method for manufacturing the same: A complementary read-only memory (ROM) cell includes a transistor; and a bit line and a complementary bit line adjacent to the transistor; wherein a drain terminal of the transistor is connected to one of the bit line and the complementary bit line based on data programmed in the ROM cell.... Agent: Stmicroelectronics Pvt Ltd.

20120163064 - Memory device: A read only memory cell circuit is provided. The memory cell circuit includes at least one memory cell. A pair of bit lines associated with each memory cell is provided which form a complementary output. The at least one memory cell is configured to be coupled to first or second... Agent: Stmicroelectronics Pvt. Ltd.

20120163066 - Semiconductor storage device: A semiconductor storage device includes: a memory cell array including memory cells, each of the memory cells having a variable resistance element; and a control circuit configured to apply a control voltage, which is necessary for the variable resistance element to transit a resistance state, to a selected memory cell.... Agent: Kabushiki Kaisha Toshiba

20120163065 - Spatial correlation of reference cells in resistive memory array: The present disclosure relates to methods of selectively placing a reference column or reference row in a memory array. The method includes measuring a resistance state resistance value for a plurality of variable resistive memory cells within a memory array and mapping a location of each measured variable resistive memory... Agent: Seagate Technology LLC

20120163067 - Volatile memory elements with soft error upset immunity: Memory elements are provided that exhibit immunity to soft error upset events when subjected to high-energy atomic particle strikes. The memory elements may each have ten transistors including two address transistors and four transistor pairs that are interconnected to form a bistable element. Clear lines such as true and complement... Agent:

20120163068 - 10t sram cell with near dual port functionality: An integrated circuit including an array of SRAM cells containing a write port with a write word line and two read buffers with read word lines. The write port includes passgate transistors connected to each data node of the SRAM cell. A process of operating the integrated circuit in which... Agent: Texas Instruments Incorporated

20120163070 - Magnetoresistive element and magnetic memory: According to one embodiment, a magnetoresistive element includes a first magnetic layer with a perpendicular and variable magnetization, a second magnetic layer with a perpendicular and invariable magnetization, and a first nonmagnetic layer between the first and second magnetic layer. The first magnetic layer has a laminated structure of first... Agent:

20120163069 - Memristor device with resistance adjustable by moving a magnetic wall by spin transfer and use of said memristor in a neural network: A device with adjustable resistance includes two magnetic elements separated by an insulating or semi-conductor element. The resistance of the device depends on the position of a magnetic wall in one of the magnetic elements, the magnetic wall separating two areas of said magnetic element each having a separate homogeneous... Agent: Thales

20120163071 - Signal processing circuit: It is an object to provide a signal processing circuit for which a complex manufacturing process is not necessary and whose power consumption can be suppressed. In particular, it is an object to provide a signal processing circuit whose power consumption can be suppressed by stopping the power supply for... Agent: Semiconductor Energy Laboratory Co., Ltd.

20120163072 - Non-volatile semiconductor memory cell with dual functions: A non-volatile semiconductor memory cell with dual functions includes a substrate, a first gate, a second gate, a third gate, a charge storage layer, a first diffusion region, a second diffusion region, and a third diffusion region. The second gate and the third gate are used for receiving a first... Agent:

20120163077 - Multi-level cell nor flash memory device: A multi-level cell NOR flash memory device includes a plurality of gate lines, a plurality of source regions, a plurality of drain regions, a plurality of source lines, a plurality of bitlines, and a plurality of power lines. The bitlines each have a specific sheet resistance. A specific number of... Agent: Eon Silicon Solution Inc.

20120163079 - Programming orders for reducing distortion based on neighboring rows: A method for data storage includes predefining an order of programming a plurality of analog memory cells that are arranged in rows. The order specifies that for a given row having neighboring rows on first and second sides, the memory cells in the given row are programmed only while the... Agent: Anobit Technologies Ltd

20120163080 - Reducing distortion using joint storage: A method for data storage includes predefining an order of programming a plurality of analog memory cells that are arranged in rows. The order specifies that for a given row having neighboring rows on first and second sides, the memory cells in the given row are programmed only while the... Agent: Anobit Technologies Ltd

20120163078 - Semiconductor memory device capable of suppressing peak current: A memory cell array includes a plurality of memory cells, in which n (n is a natural number equal to 3 or larger) cells are simultaneously written. A control circuit controls the memory cell array. A conversion circuit converts data constituted of k (k is equal to n or smaller,... Agent:

20120163076 - Single check memory devices and methods: Memory devices and methods of operating memory devices are shown. Configurations described include circuits to perform a single check between programming pulses to determine a threshold voltage with respect to desired benchmark voltages. In one example, the benchmark voltages are used to change a programming speed of selected memory cells.... Agent:

20120163082 - Memory with sub-blocks: The apparatuses and methods described herein may comprise a memory array formed on a semiconductor substrate and including a plurality of cells associated with a plurality of word lines. The memory array may comprise a plurality of sub-blocks including a first sub-block and a second sub-block. Each sub-block may comprise... Agent:

20120163081 - Nonvolatile memory devices: Nonvolatile memory devices including a memory cell array with a plurality of memory blocks and a plurality of bit lines arranged at the memory cell array. Each of the plurality of memory blocks may include a plurality of strings arranged in rows and columns and formed to be vertical to... Agent: Samsung Electronics Co., Ltd.

20120163083 - Alternate bit line bias during programming to reduce channel to floating gate coupling in memory: In a non-volatile storage system, capacitive coupling effects are reduced by reducing the probability that adjacent storage elements reach the lockout condition at close to the same program pulse. A slow down measure such as an elevated bit line voltage is applied to the storage elements of a word line... Agent:

20120163086 - Concurrent operation of plural flash memories: A device comprises an address storage device. A first circuit includes a first flash memory, configured to sequentially receive first and second addresses and store the first address in the address storage device. The first circuit has a first set of control inputs for causing the first circuit to perform... Agent: Taiwan Semiconductor Manufacturing Co., Ltd.

20120163087 - Decoder for nand memory: An integrated circuit device has multiple blocks of NAND memory cells, and a high voltage switch. The high voltage switch is coupled to a decoder output and the blocks of NAND memory cells. The high voltage switch has an output voltage range with positive and negative voltages.... Agent: Macronix International Co., Ltd.

20120163084 - Early detection of degradation in nand flash memory: Techniques for early detection of degradation in NAND Flash memories by measuring the dispersion of the threshold voltages (VT's), of a set (e.g. page) of NAND Flash memory cells during read operations are described. In an embodiment of the invention the time-to-completion (TTC) values for the read operation for the... Agent:

20120163090 - Information recording/reproducing device: According to one embodiment, an information recording/reproducing device includes a recording layer, and a recording circuit configured to record information by generating a phase change in the recording layer while applying a voltage to the recording layer. The recording layer comprises a compound including at least one type of cationic... Agent:

20120163089 - Method for writing data in semiconductor storage device and semiconductor storage device: A method for writing data in a semiconductor storage device and a semiconductor storage device are provided, that can reduce variations in readout current from a sub storage region which serves as a reference cell for the memory cells of the semiconductor storage device, thereby preventing an improper determination from... Agent: Lapis Semiconductor Co., Ltd.

20120163085 - Non-volatile memory and methods with soft-bit reads while reading hard bits with compensation for coupling: A non-volatile memory has its cells' thresholds programmed within any one of a first set of voltage bands partitioned by a first set of reference thresholds across a threshold window. Hard bits are obtained when read relative to the first set of reference thresholds. The cells are read at a... Agent:

20120163088 - Semiconductor memory device and control method therefor: According to one embodiment, a semiconductor memory device includes a memory cell array including memory cells, each of which is arranged at a position of between a word line and a bit line, a row decoder, and a bit line control circuit. And when data is to be read out... Agent:

20120163091 - Semiconductor memory device which stores plural data in a cell: A memory cell array is configured to have a plurality of memory cells arranged in a matrix, each of the memory cells being connected to a word line and a bit line and being capable of storing n values (n is a natural number equal to or larger than 3).... Agent:

20120163092 - Nonvolatile memory device and method of programming the same: The program method of a nonvolatile memory device includes detecting temperature, setting a step voltage, corresponding to an increment of a program voltage in a program operation of an incremental step pulse program (ISPP) method, wherein the step voltage changes based on the detected temperature, and performing the program operation... Agent: Hynix Semiconductor Inc.

20120163093 - Nonvolatile memory device and program method thereof: A programming method of a nonvolatile memory device includes inputting even data and odd data to be programmed into even memory cells coupled to even bit lines and odd memory cells coupled to odd bit lines, respectively, setting a sense signal as a first sense signal or a second sense... Agent:

20120163094 - Programming methods and memories: Methods of programming memory cells, and memories incorporating such methods, are disclosed. In at least one embodiment, programming is accomplished by applying a set of incrementing program pulses to program a selected cell to a first target threshold voltage, and applying a set of incrementing inhibit pulses to an unselected... Agent: Micron Technology, Inc

20120163074 - Early degradation detection in flash memory using test cells: A Flash memory system and a method for data management using the embodiments of the invention use special test cells with Early Degradation Detection (EDD) circuitry instead of using the actual user-data storage cells are described. The Flash memory test cells can be made to serve as a “canary in... Agent:

20120163073 - Early detection of degradation in nor flash memory: The embodiments of the invention in this disclosure describe techniques for early warning of degradation in NOR Flash memories by estimating the dispersion of the threshold voltages (VT's), of a set of NOR Flash memory cells during read operations. In an embodiment invention the time-to-completion (TTC) values for the read... Agent:

20120163075 - Non-volatile storage device: There is provided a non-volatile storage device including: a bit line that is connected to a non-volatile storage element and is applied with a voltage of magnitude corresponding to the logic value stored in the storage element; a charging section that charges the bit line to a voltage of equivalent... Agent: Lapis Semiconductor Co., Ltd.

20120163096 - Nonvolatile semiconductor memory device and method for controlling the same: During data read process, a control circuit gives a read voltage to a selected word line connected to a selected memory cell, and gives read pass voltages, for turning on memory cells, to unselected word lines connected to unselected memory cells. The control circuit respectively gives a first read pass... Agent: Kabushiki Kaisha Toshiba

20120163095 - Semiconductor memory device: A semiconductor memory device includes a plurality of bit lines connected to memory cells; a sense amplifier connected to the plurality of bit lines; a memory unit configured to hold failure data of the bit lines; and a controller configured to perform control such that if it is judged that... Agent: Kabushiki Kaisha Toshiba

20120163097 - Memory device, memory control method, and program: A memory device includes: a non-volatile memory erasing data in a block unit and writing and reading data to and from a block; and a control unit controlling an access operation to the non-volatile memory, monitoring levels of a data change state of the non-volatile memory, and controlling a refresh... Agent: Sony Corporation

20120163100 - Auto-precharge signal generator: An auto-precharge signal generation circuit comprises a signal generator, a set signal generator, and an auto-precharge signal generator. The signal generator is configured to generating a control signal and a precharge control signal in response to receiving a first column address strobe signal and an auto-precharge flag signal. The set... Agent: Hynix Semiconductor Inc.

20120163099 - Mode-register reading controller and semiconductor memory device: A semiconductor memory device may include a mode-register reading controller and a mode register. The mode-register reading controller generates a control signal for loading data into an input/output line in response to an enable signal, during a mode-register reading operation. The control signal is generated in response to a mode-register... Agent: Hynix Semiconductor Inc.

20120163098 - Semiconductor memory device including mode register set and method for operating the same: A semiconductor memory device and method for operating the same includes a controller configured to generate a data buffer control signal in a mode register set (MRS) mode, a data buffer configured to buffer and output a plurality of MRS codes inputted through a data pad in response to the... Agent:

20120163101 - Memory interface circuit, memory interface method, and electronic device: A memory interface circuit includes a gating circuit that starts detection of a logic level of a data strobe signal in accordance with a data read command. A clamp circuit clamps the data strobe signal to a first logic level after the data read command is issued. A detection circuit... Agent: Fujitsu Semiconductor Limited

20120163102 - Multi-port memory array: A multi-port memory array is disclosed. The memory array includes a plurality of memory subblocks and an output network. Each memory subblock includes a plurality of single-read-port memory cells. The output network is configured to redirect information read for a first read port to a second read port on a... Agent: Advanced Micro Devices, Inc.

20120163103 - Memory cell using bti effects in high-k metal gate mos: Techniques and circuitry are disclosed for implementing non-volatile storage that exploit bias temperature instability (BTI) effects of high-k/metal-gate n-type or p-type metal oxide semiconductor (NMOS or PMOS) transistors. A programmed bitcell of, for example, a memory or programmable logic circuit exhibits a threshold voltage shift resulting from an applied programming... Agent:

20120163104 - Delay adjustment device, semiconductor device and delay adjustment method: A semiconductor device including an adjustment mode and a normal operation mode, including a first terminal to be coupled to the memory and configured to output a read command to the memory in the adjustment mode and not to output a write command in the adjustment mode, and a second... Agent: Renesas Electronics Corporation

20120163105 - Semiconductor storage device: A semiconductor storage device has a great number of logic circuits and fuse blocks with its space-saving design. In the semiconductor storage device, a plurality of fuse blocks is arranged in a line or row in the vicinity of a gate array. Each fuse block includes a plurality of fuse... Agent: Lapis Semiconductor Co., Ltd.

20120163107 - Memory device capable of operation in a burn in stress mode, method for performing burn in stress on a memory device, and method for detecting leakage current of a memory device: Activate one active word line of two active word lines formed between two isolation word lines to a logic-high voltage, and float another active word line of the two active word lines. Then activate a plurality of first memory cells corresponding to the active word line having the logic-high voltage... Agent:

20120163108 - Non-volatile memory device and electronic apparatus: A non-volatile memory device is provided, which includes a first block for storing a first data group including a test data, a second block for storing a second data group including a complementary data to the first data group, a differential sense amplifier for generating an output value based on... Agent: Seiko Epson Corporation

20120163106 - Refresh control circuit and method for semiconductor memory device: A semiconductor memory device includes a refresh counter for counting a refresh signal and outputting a refresh address in response to an active mode signal enabled in an active mode, an external address input buffer for buffering an external address to output an internal address in response to a mode... Agent:

20120163109 - Memory circuit and a tracking circuit thereof: Memory circuit and a tracking circuit thereof. The tracking circuit includes a dummy bit line (DBL). The tracking circuit further includes a first circuit to discharge the dummy bit line in response to a first signal and a wordline activation signal. The wordline activation signal causes activation of a memory... Agent: Texas Instruments Incorporated

20120163110 - Memory device with robust write assist: A memory circuit includes a memory cell configured to be re-writable. A write enable circuit is configured to enable writing a signal via a pair of bit lines to the memory cell depending on a write signal. A charge supply circuit is configured to supply a charge to at least... Agent: Stmicroelectronics Pvt. Ltd.

20120163111 - Refresh control circuit and method for semiconductor memory device: A refresh control circuit for a semiconductor memory device includes a refresh controller configured to control the number of times a refresh signal is enabled during one refresh period in response to a refresh mode entering signal which indicates the start of a refresh mode, and a mode determination signal... Agent:

20120163112 - Semiconductor storage system capable of suppressing peak current: According to one embodiment, in a semiconductor storage system, the power supply wiring is connected to a first semiconductor storage device, and second semiconductor storage device as a common connection, and supplies power to the first and second semiconductor storage devices. A voltage detection circuit is provided in each of... Agent:

20120163113 - Memory controller and memory controlling method: A memory controller includes: a first generating unit that generates a read-address to read a data element sequence having a plurality of data elements from a bank of a memory; a second generating unit that generates a position signal indicating a position of a data element to be selected from... Agent: Fujitsu Limited

20120163114 - Nand logic word line selection: A NAND architecture for selecting a word line driver in a DRAM is disclosed. Separately decoded addresses in the low, mid and high ranges are used to select a final word line driver. The output of the word line driver is at a potential negative with respect to ground for... Agent:

20120163115 - Nor logic word line selection: A NOR architecture for selecting a word line driver in a DRAM is disclosed. Complements of separately decoded addresses in the low, mid and high ranges are used to select a final word line driver. The output of the word line driver is at a potential negative with respect to... Agent:

  
06/21/2012 > 71 patent applications in 38 patent subcategories. invention type

20120155142 - Phase interpolators and push-pull buffers: Interpolator systems are described utilizing one or more push-pull buffers to generate output clock signals that may be provided as inputs to a phase interpolator. The more linear slope on the output of the push-pull buffer may improve the linearity of a phase interpolator using the clock signals output from... Agent: Micron Technology, Inc.

20120155143 - Semiconductor device: A semiconductor device includes a plurality of gates of high voltage transistors configured to couple a plurality of global word lines to a plurality of local word lines and the plurality of local word lines arranged over each of the gates. The plurality of local word lines is arranged within... Agent: Hynix Semiconductor Inc.

20120155144 - Fast response circuits and methods for fram power loss protection: A circuit to protect data on an FRAM during a read operation includes an FRAM voltage regulator having an output to supply an FRAM operating voltage to the FRAM. A voltage monitor monitors a supply voltage for the FRAM to generate a voltage fault signal if the supply voltage falls... Agent: Texas Instruments Incorporated

20120155145 - High speed fram: A memory cell includes four transistors and two ferroelectric capacitors, wherein one of the two ferroelectric capacitors is positively polarized and another one of the two ferroelectric capacitors is negatively polarized for storing a non-inverting data and an inverting data, and a pair of access transistors is connected to the... Agent:

20120155147 - Nonvolatile semiconductor memory device: A nonvolatile semiconductor memory device includes a memory cell array including memory cells each provided at individual intersection between a first wiring and a second wiring, the memory cell comprising a variable resistive element, and predetermined numbers of the memory cells shearing the same first wiring to configure a page;... Agent: Kabushiki Kaisha Toshiba

20120155148 - Resistance change memory device: A resistance change memory device including: a cell array having a resistance change type of memory cells disposed at the cross-points of word lines and bit lines, the resistance value of the memory cell being reversibly settable; a word line driver circuit configured to apply a selecting drive voltage to... Agent: Kabushiki Kaisha Toshiba

20120155146 - Resistance-change memory: According to one embodiment, a resistance-change memory includes memory cells between a bit line and a source line, each of the memory cells including a memory element and a cell transistor having a gate connected to a word line, an n-channel transistor having a gate to which a first control... Agent:

20120155149 - Semiconductor storage device: A semiconductor storage device includes: a cell array including a plurality of first wirings, a plurality of second wirings intersecting the first wirings, and memory cells positioned at intersecting portions between the first wirings and the second wirings, each of the memory cells having a series circuit of a non-ohmic... Agent: Kabushiki Kaisha Toshiba

20120155150 - Semiconductor storage device: A semiconductor storage device with a novel structure, which can retain stored data even when power is not supplied (i.e., is non-volatile) and has no limitation on the number of write cycles. The semiconductor storage device includes a memory cell array in which a plurality of memory cells are arranged... Agent: Semiconductor Energy Laboratory Co., Ltd.

20120155151 - Memory device having memory cells with enhanced low voltage write capability: A memory device includes a memory array comprising a plurality of memory cells. At least a given one of the memory cells comprises a pair of cross-coupled inverters and associated write assist circuitry. The write assist circuitry comprises first switching circuitry coupled between a supply node of a device of... Agent:

20120155152 - Static random access memory: In a random access memory, one of a first conductivity type well constituting a first bit in one column group and another first conductivity type well constituting a second bit selected simultaneously to the first bit in an adjacent column group, is isolated from a common well of the first... Agent: Fujitsu Semiconductor Limited

20120155155 - Generating a temperature-compensated write current for a magnetic memory cell: This disclosure describes write current temperature compensation techniques for use in programming a data storage device that includes one or more memory cells. The techniques may include programming a programmable magnetization state of a magnetoresistive device included within a resistance network based on a signal indicative of the operating temperature... Agent: Honeywell International Inc.

20120155157 - Magnetic random access memory apparatus, methods for programming and verifying reference cells therefor: A magnetic random access memory apparatus includes a memory cell array including a plurality of magnetic memory cells; a reference cell array including a pair of reference magnetic memory cells; a write driver configured to program data in the memory cell array and the reference cell array; and a first... Agent: Hynix Semiconductor Inc.

20120155160 - Memory controller and method for interleaving dram and mram accesses: A memory controller and method for interleaving volatile and non-volatile memory different latencies and page sizes are described wherein a single DDR3 memory controller communicates with a number of memory modules comprising of at least non-volatile memory, e.g., spin torque magnetic random access memory, integrated in a different Rank or... Agent: Everspin Technologies, Inc.

20120155156 - Method and system for providing magnetic tunneling junction elements having improved performance through capping layer induced perpendicular anisotropy and memories using such magnetic elements: A method and system for providing a magnetic element and a magnetic memory utilizing the magnetic element are described. The magnetic element is used in a magnetic device that includes a contact electrically coupled to the magnetic element. The method and system include providing pinned, nonmagnetic spacer, and free layers.... Agent: Grandis, Inc.

20120155159 - Multibit magnetic random access memory cell with improved read margin: A magnetic random access memory (MRAM) cell including a magnetic tunnel junction including a tunnel barrier layer between a first magnetic layer having a first magnetization direction, and a second magnetic layer having a second adjustable magnetization to vary a junction resistance of the magnetic tunnel junction from a first... Agent: Crocus Technology Sa

20120155153 - Scalable magnetic memory cell with reduced write current: A magnetic memory cell comprising a magnetoresistive element including a free layer with a changeable orientation of a magnetization oriented substantially perpendicular to a layer plane in its equilibrium state, a pinned layer with a fixed orientation of a magnetization oriented substantially perpendicular to a layer plane, and a tunnel... Agent:

20120155158 - Storage device and writing control method: A storage device is provided with a plurality of pairs of memory blocks, which have a storage layer which stores information and is configured to have a plurality of storage elements which store the information in the storage layer by the orientation of the magnetization of the storage layer being... Agent: Sony Corporation

20120155154 - Three-dimensional magnetic random access memory with high speed writing: A magnetic random access memory with perpendicular magnetization comprising a selection transistor with a gate width, that is formed on a substrate and is electrically connected to a word line; a plurality of memory layers sequentially disposed above the substrate, wherein each of the plurality of the memory layers includes... Agent:

20120155163 - Reducing programming time of a memory cell: The present invention provides methods and apparatus for adjusting voltages of bit and word lines to program a two terminal memory cell. The invention may include setting a first line connected to a memory cell to a first voltage from a first line standby voltage, charging a second line connected... Agent:

20120155162 - Semiconductor storage apparatus or semiconductor memory module: A semiconductor storage apparatus provides a large capacity phase-change memory possessing high speed operation, low electrical current, and high-reliability. During the period that a read-out start signal is activated in the memory region control circuit and the block of pairs of sense-latch and write driver is performing the verify read... Agent: Hitachi, Ltd.

20120155161 - Three-terminal ovonic threshold switch as a current driver in a phase change memory: A three-terminal Ovonic Threshold Switch (OTS) is used to provide current to a Phase Change Memory Switch (PCMS) cross point array. The current is started by sending a small current into the second terminal of the three-terminal OTS allowing a larger current to flow from the first terminal to the... Agent:

20120155164 - Multibit cell of magnetic random access memory with perpendicular magnetization: A multi-bit cell of magnetic random access memory comprises a magnetic tunnel junction element including a first and second free layer comprising a changeable magnetization oriented substantially perpendicular to a layer plane in its equilibrium state and a switching current, a first and second tunnel barrier layer, and a pinned... Agent:

20120155165 - Memory: An embodiment of the invention relates to a memory comprising a strained double-heterostructure having an inner semiconductor layer which is sandwiched between two outer semiconductor layers, wherein the lattice constant of the inner semiconductor layer differs from the lattice constants of the outer semiconductor layers, the resulting lattice strain in... Agent: Technische Universitat Berlin

20120155166 - Alternate page by page programming scheme: An alternate page by page scheme for the multi-state programming of data into a non-volatile memory is presented. Pages of data are written a page at a time onto word lines of the memory. After all of the pages of data are written to a first level of resolution onto... Agent:

20120155168 - Negative voltage generator, decoder, nonvolatile memory device and memory system using negative voltage: A negative voltage generator includes a direct current voltage generator configured to generate a direct current voltage, a reference voltage generator configured to generate a reference voltage, an oscillator configured to generate an oscillation clock, a charge pump configured to generate a negative voltage in response to a pump clock,... Agent: Samsung Electronics Co., Ltd.

20120155167 - Non-volatile storage device, information processing system and write control method of non-volatile storage device: A non-volatile storage device has a non-volatile memory, a capacity determination part configured to determine whether data amount stored into the non-volatile memory exceeds a first threshold value, an area dividing determination part configured to provide a first storage area for writing one bit data to one memory cell and... Agent: Kabushiki Kaisha Toshiba

20120155169 - Nonvolatile semiconductor storage device: A nonvolatile semiconductor storage device storing plural data bits in one memory cell by assigning multivalued data having a higher-order bit selected from one of a pair of data in a first unit and a lower-order bit selected from the other of the pair of data. In a first write... Agent: Kabushiki Kaisha Toshiba

20120155170 - Non-volatile memory device and method of manufacturing the same: A multi-layered non-volatile memory device and a method of manufacturing the same. The non-volatile memory device may include a plurality of first semiconductor layers having a stack structure. A plurality of control gate electrodes may extend across the first semiconductor layers. A first body contact layer may extend across the... Agent:

20120155171 - Memory system: According to one embodiment, a memory system includes a nonvolatile first memory configured to store a boot program, a volatile second memory, a detection circuit configured to detect a level of a power supply voltage, and to generates an interrupt when the power supply voltage becomes less than a first... Agent:

20120155172 - Semiconductor memory device: According to one embodiment, a semiconductor memory device includes a first memory and a second memory, a data path between the first memory and the second memory, a register configured to store first data transferred through the data path in a first direction, and a comparison circuit configured to compare... Agent:

20120155173 - Universal timing waveforms sets to improve random access read and write speed of memories: Methods of increasing the speed of random read and write operations of a memory device are provided for improving the performance of volatile and non-volatile memory devices. In contrast to the conventional approach that latches the current memory address right before the currently accessed memory data are outputted, the methods... Agent:

20120155174 - Use of alternative value in cell detection: A system and method, including computer software, allows reading data from a flash memory cell. Voltages from a group of memory cells are detected. The group of memory cells have associated metadata for error detection, and each memory cell stores a voltage representing a data value selected from multiple possible... Agent: Apple Inc.

20120155175 - Flash memory device and operation method thereof: A method for operating a flash memory device includes storing a first command and a first address corresponding to a first plane, storing a second command and a second address corresponding to a second plane, and performing a first command operation for the first plane based on the first command... Agent:

20120155176 - Semiconductor memory device and method of manufacturing the same: A semiconductor memory device and a method of manufacturing the same. The semiconductor memory device includes a first conductive type well and a second conductive type well disposed on and/or over a semiconductor substrate; a first gate and a second gate disposed on and/or over the first conductive type well... Agent:

20120155180 - Nonvolatile semiconductor memory device and method of operating a nonvolatile memory device: A nonvolatile memory device includes a memory cell array including a plurality of bitlines, a plurality of wordlines, and a plurality of memory cells. The memory device further includes a plurality of page buffers coupled to the respective bitlines of the memory cell array, each page buffer including a latch... Agent: Samsung Electronics Co., Ltd.

20120155178 - Semiconductor memory device: According to one embodiment, a semiconductor memory device includes a memory, and a data transfer section configured to perform data transfer from and to the memory, and having a first mode to transfer data with a first bit width and a second mode to transfer data with a second bit... Agent:

20120155179 - Semiconductor memory device: According to one embodiment, a semiconductor memory device includes a memory cell array having memory cells, word lines connected to the memory cell array, a generation circuit configured to generate voltages required for operations of the memory cell array, selection circuits connected to the word lines, respectively, each of the... Agent:

20120155177 - Structures and methods for reading out non-volatile memory using referencing cells: The structures and methods of reading out semiconductor Non-Volatile Memory (NVM) using referencing cells are disclosed. The new invented scheme can reduce large current consumption from the direct current biasing in the conventional scheme and achieve a high resolution on the cell threshold voltage with a good sensing speed.... Agent:

20120155181 - Method and apparatus for reducing read disturb in memory: Various aspects of a NAND memory include have multiple versions of a high threshold voltage distribution—a version with a reduced maximum, and another version. The version with a reduced maximum has a reduced word line pass voltage.... Agent: Macronix International Co., Ltd.

20120155184 - Flash memory device having dummy cell: A nonvolatile semiconductor memory device includes a string selection transistor coupled to a bit line. The device also includes a plurality of memory cells coupled in series to the string selection transistor, wherein at least one of the memory cells is configured to be in a programmed state during an... Agent: Samsung Electronics Co., Ltd.

20120155183 - Method of soft programming semiconductor memory device: An operating method of a semiconductor memory device includes erasing all memory cells of a selected cell block, performing a soft program operation on the erased memory cells by supplying a soft program pulse to word lines of the selected cell block, performing a first verify operation using a first... Agent:

20120155182 - Non-volatile memory device and cache program method of the same: A cache programming method for a non-volatile memory device includes programming data for a current programming operation into a memory cell array, determining whether the current programming operation has been performed to a threshold point of program completion, and receiving a data for a next programming operation when the current... Agent:

20120155185 - Memory device and corresponding reading method: An electrically erasable and programmable non-volatile memory device includes memory cells arranged in rows and columns, and each column of memory cells is associated with a respective local bit line. The local bit lines are divided into packets of local bit lines, each packet of local bit lines associated with... Agent: Stmicroelectronics S.r.i.

20120155186 - Semiconductor memory device and method of operating the same: A semiconductor memory device operate during a program verification operation to apply a read voltage to a word line and a pre-charge voltage to a bit line in order to provide output data. A number of fail cells is determined in view of the output data, wherein the number of... Agent: Samsung Electronics Co., Ltd.

20120155187 - Adaptive programming for flash memories: A method to adjust the programming voltage in flash memory when the programming time exceeds specification. A method to adjust the programming voltage of flash memory after a predetermined number of erase/write cycles.... Agent: Texas Instruments Incorporated

20120155188 - Reduced power consumption memory circuitry: In a circuit that reduces power consumption in an array system of memory cells accessible in parallel, a local evaluation circuit is connected to a memory cell and a global bit line of the array system of memory cells. A selection circuitry splits the global bit line into an upper... Agent: International Business Machines Corporation

20120155189 - System and method for level shifter: In one embodiment, a bit-line interface is disclosed. The bit-line interface has a multiplexer having a plurality of bit-line outputs, and a write path coupled to a multiplexer signal input. The bit-line interface also has a read path coupled to the multiplexer signal input, wherein the read path and the... Agent: Infineon Technologies Ag

20120155193 - Burst termination control circuit and semiconductor memory device using the same cross-references to related application: A semiconductor memory device includes a burst termination control unit and a data output control unit. The burst termination control unit generates a termination control signal, a read command, a write command and a mode resister read command. The data output control unit stops a data output operation in response... Agent: Hynix Semiconductor Inc.

20120155190 - Page buffer circuit: A page buffer circuit includes: a main latch unit configured to have a main latch value which is dependent on a sub latch output signal, and output the main latch value to a first node; a sub latch unit configured to latch a voltage of a second node as a... Agent: Hynix Semiconductor Inc.

20120155191 - Semiconductor memory device: According to one embodiment, a semiconductor memory device includes a first memory configured to receive a first clock and including a first buffer configured to perform a data input operation and a data output operation, a second memory including a second buffer configured to perform a data input operation and... Agent:

20120155192 - Semiconductor memory devices and methods of testing the same: A semiconductor memory device and a method of testing the same are provided. The semiconductor memory device includes a memory cell array including a plurality of memory cells each of which stores at least one bit of data; an output terminal configured to transmit output data; and a data output... Agent: Samsung Electronics Co., Ltd.

20120155194 - Wordline voltage control within a memory: A memory circuit 2 includes bit cells 4 selected for reading with a word line voltage upon a word line 20. Word line voltage control circuitry 26 generates a two-step word line voltage signal. The word line voltage first increases to an intermediate level at which word line transistors 12... Agent: Arm Limited

20120155195 - Overlapping interconnect signal lines: Described herein are various principles for designing, manufacturing, and operating integrated circuits having functional components and one or more metal interconnect layers, where the dimensions of signal lines of the metal interconnect layers are larger than dimensions of the functional components. In some embodiments, a signal line may have a... Agent: Stmicroelectronics Inc.

20120155196 - Semiconductor memory and manufacturing method: A semiconductor memory includes a memory cell array that includes data cells of x bits and redundant cells of y bits for each word; a position-data storage unit that stores, for each word, defective-cell position data of defective cells of the data cells and the redundant cells; and a read... Agent: Fujitsu Limited

20120155197 - Semiconductor memory device and operating method thereof: A semiconductor memory device includes a page buffer configured to store data read from a memory cell, a counter circuit configured to count the number of first data or second data in the read data for every read operation while the read operations are repeated a set number of times,... Agent: Hynix Semiconductor Inc.

20120155198 - Semiconductor storage device: According to one embodiment, a read bit line is driven based on data read out from a memory cell. A read port drives the read bit line based on data stored in a storage node. A read word line performs row selection via the read port at a time of... Agent: Kabushiki Kaisha Toshiba

20120155200 - Memory device, memory system including the same, and control method thereof: A memory system includes a memory device, a control device configured to control the memory device, a first channel configured to transfer a row command from the control device to the memory device, and a second channel configured to transfer a column command from the control device to the memory... Agent:

20120155199 - Semiconductor memory apparatus: A semiconductor memory apparatus may include a bonding pad; a control signal pad; and an operation mode signal generation unit configured to generate a plurality of operation mode signals in response to a bonding signal inputted through the bonding pad and a control signal inputted through the control signal pad.... Agent: Hynix Semiconductor Inc.

20120155201 - System and method for hidden refresh rate modification: A system and method for modifying a hidden-refresh rate for dynamic memory cells includes monitoring a control signal from a processor and performing a hidden-refresh of dynamic data at a first refresh rate when the control signal is asserted. The dynamic data is refreshed at a second refresh rate when... Agent: Micron Technology, Inc.

20120155202 - Defective memory cell address storage circuit and redundancy control circuit including the same: A fail address storage circuit includes a fail address storage unit configured to store a fail address and a discrimination information storage unit configured to store information indicating whether a value stored in the fail address storage unit is a row address or column address.... Agent:

20120155203 - Semiconductor memory device, method of testing the same and system of testing the same: A method of testing a semiconductor memory device comprises receiving a clock, addresses, commands, and data from a test device through channels, generating an internal bank address in response to the addresses and the commands, performing a multi-bit parallel test for each of a plurality of banks based on the... Agent:

20120155204 - Semiconductor memory apparatus having a pre-discharging function, semiconductor integrated circuit having the same, and method for driving the same: A semiconductor memory apparatus includes a bit line coupled to a plurality of memory cells, a discharge controller configured to generate a bit line discharge signal to pre-discharge the bit line before the memory cells are activated, and a bit line discharge block coupled to the bit line and configured... Agent: Hynix Semiconductor Inc.

20120155206 - Semiconductor device periodically updating delay locked loop circuit: Such a device is disclosed that includes a control circuit outputting a first clock signal having a first clock cycle in response to a first command signal and outputting a second clock signal having a second clock cycle in response to a second command signal, a first circuit controlled based... Agent: Elpida Memory, Inc.

20120155205 - Semiconductor integrated circuit: A semiconductor memory apparatus includes a buffer control unit configured to deactivate a buffer control signal in response to an auto-refresh start pulse, and activate the buffer control signal in response to an auto-refresh end pulse, a command buffer configured to buffer an external command and output an internal command... Agent: Hynix Semiconductor Inc.

20120155208 - Negative high voltage generator and non-volatile memory device including negative high voltage generator: A negative high voltage generator includes a charge providing unit and a voltage conversion unit. The charge providing unit is configured to periodically output a predetermined amount of positive charges received from a supply voltage. The voltage conversion unit is configured to store the positive charges and to discharge the... Agent: Samsung Electronics Co., Ltd.

20120155207 - Semiconductor device generating internal voltage: Such a device is disclosed that includes an internal voltage generating circuit generating an internal voltage by lowering an external potential and supplying the generated internal voltage to a power supply line, a switch being connected between a grounding wire to which a ground voltage is supplied and the power... Agent: Elpida Memory, Inc.

20120155209 - Semiconductor memory device: A semiconductor memory device is configured to have a first memory cell array having a plurality of blocks (cell arrays corresponded to one I/O bit), each block having a plurality of columns and being corresponding respectively to one of data terminals, wherein the blocks being arranged side by side in... Agent: Fujitsu Semiconductor Limited

20120155210 - Physical organization of memory to reduce power consumption: Controllable arrays in a memory may be activated and deactivated independently. In one embodiment, a processor may include a memory. The memory may be a de-interleaved memory with independently selectable arrays. Based on an address bit of an address used to access data from the memory, a wordline and downstream... Agent:

20120155211 - Semiconductor integrated circuit: A memory macro includes: a plurality of memory cells arranged in a matrix; a plurality of word lines corresponding to rows of the plurality of memory cells; and a plurality of word line drivers configured to drive the plurality of word lines. The voltage of the word lines in their... Agent: Panasonic Corporation

20120155212 - Semiconductor device generating a clock signal when required: Such a device is disclosed that includes a clock generation circuit generating a first clock signal and having an output node, and a drive circuit coupled to the output node of the clock generation circuit. The clock generation circuit outputs the first clock signal from the output node to the... Agent: Elpida Memory, Inc.

  
06/14/2012 > 51 patent applications in 28 patent subcategories. invention type

20120147642 - System and method for reducing power consumption in a content-addressable memory: According to one disclosed embodiment, a content-addressable memory (CAM) system configured for reduced power consumption includes a sensing circuit utilized to apply a sense voltage to a matchline of the CAM system, a valid bit cell coupled to the matchline, and a power cut-off circuit configured to isolate the sense... Agent: Broadcom Corporation

20120147643 - System for reducing power consumption and increasing speed of content-addressable memory: According to one disclosed embodiment, a content addressable memory (CAM) system configured for reduced power consumption and increased speed includes a plurality of bit cells implementing a stacked architecture. Each bit cell comprises a pair of stacked storage elements in a first column and a compare circuit, coupled to the... Agent: Broadcom Corporation

20120147644 - Continuous mesh three dimensional non-volatile storage with vertical select devices: A three-dimensional array adapted for memory elements that reversibly change a level of electrical conductance in response to a voltage difference being applied across them. Memory elements are formed across a plurality of planes positioned different distances above a semiconductor substrate. Bit lines to which the memory elements of all... Agent:

20120147649 - Non-volatile memory having 3d array of read/write elements with low current structures and methods thereof: A three-dimensional array read/write (R/W) memory elements is formed across multiple layers of planes positioned at different distances above a semiconductor substrate. It is preferable to operate the R/W elements with low current and high resistive states. The resistance of these resistive states depends also on the dimension of the... Agent:

20120147650 - Non-volatile memory having 3d array of read/write elements with vertical bit lines and select devices and methods thereof: A three-dimensional memory is formed as an array of memory elements that are formed across multiple layers of planes positioned at different distances above a semiconductor substrate. The memory elements reversibly change a level of electrical conductance in response to a voltage difference being applied across them. The three-dimensional array... Agent:

20120147646 - Three dimensional non-volatile storage with connected word lines: A three-dimensional array adapted for memory elements that reversibly change a level of electrical conductance in response to a voltage difference being applied across them. Memory elements are formed across a plurality of planes positioned different distances above a semiconductor substrate. Bit lines to which the memory elements of all... Agent:

20120147648 - Three dimensional non-volatile storage with dual gate selection of vertical bit lines: A three-dimensional array adapted for memory elements that reversibly change a level of electrical conductance in response to a voltage difference being applied across them. Memory elements are formed across a plurality of planes positioned different distances above a semiconductor substrate. Bit lines to which the memory elements of all... Agent:

20120147645 - Three dimensional non-volatile storage with dual gated vertical select devices: A three-dimensional array adapted for memory elements that reversibly change a level of electrical conductance in response to a voltage difference being applied across them. Memory elements are formed across a plurality of planes positioned different distances above a semiconductor substrate. Bit lines to which the memory elements of all... Agent:

20120147647 - Three dimensional non-volatile storage with three device driver for row select: A three-dimensional array adapted for memory elements that reversibly change a level of electrical conductance in response to a voltage difference being applied across them. Memory elements are formed across a plurality of planes positioned different distances above a semiconductor substrate. Bit lines to which the memory elements of all... Agent:

20120147651 - Three dimensional non-volatile storage with dual layers of select devices: A three-dimensional array adapted for memory elements that reversibly change a level of electrical conductance in response to a voltage difference being applied across them. Memory elements are formed across a plurality of planes positioned different distances above a semiconductor substrate. Bit lines to which the memory elements of all... Agent:

20120147652 - Three dimensional non-volatile storage with asymmetrical vertical select devices: A three-dimensional array adapted for memory elements that reversibly change a level of electrical conductance in response to a voltage difference being applied across them. Memory elements are formed across a plurality of planes positioned different distances above a semiconductor substrate. Bit lines to which the memory elements of all... Agent:

20120147653 - Circuit and system of a high density anti-fuse: A high density anti-fuse cell can be built at the cross points of two perpendicular interconnect lines, such as active region lines, active and polysilicon lines, active and metal lines, or polysilicon and metal lines. The cell size can be very small. At least one of the anti-fuse cells have... Agent:

20120147654 - Ferroelectric random access memory with single plate line pulse during read: A ferroelectric random access memory (FRAM) with reduced cycle time. During a read cycle, plate line voltages are boosted to a voltage to both transfer charge from the selected row of FRAM cells to corresponding bit lines, and to fully polarize a data state in the selected FRAM cells. In... Agent: Texas Instruments Incorporated

20120147659 - Bidirectional non-volatile memory array architecture: Method and apparatus for transferring data in a memory. A semiconductor memory includes a plurality of memory cells each having a resistive sense element (RSE) in series with a switching device. A conductive word line extends in a first direction adjacent the memory cells and is connected to a gate... Agent: Seagate Technology LLC

20120147656 - Memory element and memory device: A memory element and a memory device having the stable switching characteristics with the characteristics of data retention remaining favorable are provided. The memory element includes a first electrode, a memory layer, and a second electrode in this order. The memory layer includes an ion source layer provided on the... Agent: Sony Corporation

20120147655 - Non-volatile memory device and method for programming the same: A non-volatile memory device and a method for programming the same are disclosed. The method for programming the non-volatile memory device includes generating a simultaneous write current based on a program address in such a manner that bit line write cells corresponding to memory cells coupled to the same bit... Agent: Hynix Semiconductor Inc.

20120147660 - Preservation circuit and methods to maintain values representing data in one or more layers of memory: Circuitry and methods for restoring data in memory are disclosed. The memory may include at least one layer of a non-volatile two-terminal cross-point array that includes a plurality of two-terminal memory elements that store data as a plurality of conductivity profiles and retain stored data in the absence of power.... Agent: Unity Semiconductor Corporation

20120147657 - Programming reversible resistance switching elements: A storage system and method for operating the storage system that uses reversible resistance-switching elements is described. Techniques are disclosed herein for varying programming conditions to account for different resistances that memory cells have. These techniques can program memory cells in fewer attempts, which can save time and/or power. Techniques... Agent:

20120147658 - System of measuring a resistance of a resistive memory device: A system for measuring a resistance of a memory cell in a resistive memory device can include a pulse generator configured to apply a data write pulse and a resistance read pulse to the resistive memory device with a delay time. A connecting member can be connected between the pulse... Agent: Samsung Electronics Co., Ltd.

20120147661 - Data security for dynamic random access memory at power-up: A circuit and method erase at power-up all data stored in a DRAM chip for increased data security. All the DRAM memory cells are erased by turning on the transistors for the DRAM storage cells simultaneously by driving the wordlines of all the cells to an activated state. With all... Agent: International Business Machines Corporation

20120147662 - Semiconductor integrated circuit and manufacturing method thereof: High manufacturing yield is realized and variation in threshold voltage of each MOS transistor in a CMOS·SRAM is compensated. Body bias voltages are applied to wells for MOS transistors of each SRAM memory cell in any active mode of an information holding operation, a write operation and a read operation... Agent: Renesas Electronics Corporation

20120147664 - Non-volatile memory device and method for controlling the same: A non-volatile memory and method for controlling the same prevents a faulty operation from being generated in a read operation, resulting in increase in operation reliability. The non-volatile memory device includes a cell array configured to include a plurality of unit cells in which a read or write operation of... Agent: Hynix Semiconductor Inc.

20120147663 - Nonvolatile memory with enhanced efficiency to address asymetric nvm cells: This application describes embodiments of MRAM cells that utilize a PMOS transistor as an access transistor. The MRAM cells are configured to mitigate the effects of applying asymmetric current loads to transition a Magnetic-Tunnel Junction of the MRAM cell between magnetoresistive states.... Agent: Infineon Technologies Ag

20120147665 - Predictive thermal preconditioning and timing control for non-volatile memory cells: Method and apparatus for using thermal preconditioning to write data to a non-volatile memory cell. In accordance with some embodiments, a semiconductor memory has an array of non-volatile memory cells, and a control circuit which stores a first write command from a host to write data to said array. A... Agent: Seagate Technology LLC

20120147668 - Diode and memory device having a diode: A diode and a memory device having a diode are provided. The diode includes a semiconductor layer and phase change material layer. The semiconductor layer and the phase change material layer have different energy bandgaps and different carrier concentrations such that an isotype heterojunction is formed at a boundary interface... Agent: Agency For Science, Technology And Research

20120147666 - Phase change material cell with stress inducer liner: An example embodiment disclosed is a phase change memory cell. The memory cell includes a phase change material and a transducer positioned proximate the phase change material. The phase change material is switchable between at least an amorphous state and a crystalline state. The transducer is configured to activate when... Agent: International Business Machines Corporation

20120147667 - Variable resistance memory programming: Some embodiments include a device having memory elements and methods of storing information into the memory elements. Such methods can include increasing a temperature of a portion of a memory element for a time interval during an operation to change a resistance state of the memory element. After the time... Agent:

20120147672 - Fractional bits in memory cells: Methods, devices, modules, and systems for programming memory cells can include storing charges corresponding to a data state that represents an integer number of bits in a set of memory cells. Programming memory cells can include storing a charge in a cell of the set, where the charge corresponds to... Agent: Micron Technology, Inc.

20120147669 - Non-volatile memory device and a method for operating the device: A method for operating a non-volatile memory device includes programming a memory cell and not programming a flag cell during first to nth (n is a natural number equal to or greater than 1) program loops, and programming the memory cell and the flag cell during (n+1)th to mth (m... Agent:

20120147671 - Over-sampling read operation for a flash memory device: A flash memory device and a reading method are provided where memory cells are divided into at least two groups. Memory cells are selected according to a threshold voltage distribution. Data stored in the selected memory cells are detected and the data is latched corresponding to one of the at... Agent: Samsung Electronics Co., Ltd.

20120147670 - Semiconductor storage device adapted to prevent erroneous writing to non-selected memory cells: A memory cell array has a number of memory cells which are connected to word lines and bit lines and are arranged in a matrix form, each of the memory cells storing one of n levels (n is a natural number of 2 or more). A control circuit controls the... Agent:

20120147674 - Nonvolatile memory devices that utilize dummy word line segments to inhibit dishing during fabrication: A NAND flash memory device includes a plurality of continuous conductors disposed on a common level of a multilayer substrate, the plurality of continuous conductors including respective conductive lines extending in parallel along a first direction, respective contact pads disposed at ends of the respective conductive lines and respective conductive... Agent:

20120147673 - Semiconductor memory device using only single-channel transistor to apply voltage to selected word line: A semiconductor memory device has a memory cell array, a first transistor of a first conductivity type, a second transistor of a second conductivity type and a third transistor of the first conductivity type. A source or drain of the first transistor is connected to each of word lines. A... Agent: Kabushiki Kaisha Toshiba

20120147676 - Non-volatile storage system with shared bit lines connected to single selection device: A non-volatile storage system is disclosed that includes pairs of NAND strings (or other groupings of memory cells) in the same block being connected to and sharing a common bit line. To operate the system, two selection lines are used so that the NAND strings (or other groupings of memory... Agent:

20120147675 - Nonvolatile stacked nand memory: A NAND string of memory cells has stacks of split word lines (gates), with resulting increased bit density. Variants add a top assist gate to the NAND string, a bottom assist gate to the NAND string, or both a top assist gate and a bottom assist gate to the NAND... Agent: Macronix International Co., Ltd.

20120147677 - Biasing system and method: Embodiments are provided that include a memory system that includes a memory system, having an access device coupled between a global line and a local line and a voltage source coupled to the global line and configured to output a bias voltage on the global line when the memory system... Agent: Micron Technology, Inc.

20120147681 - Methods, devices, and systems relating to a memory cell having a floating body: Methods, devices, and systems are disclosed for a memory cell having a floating body. A memory cell may include a transistor over an insulation layer, the transistor including a source, and a drain. The memory cell may also include a floating body including a first region positioned between the source... Agent: Micron Technology, Inc.

20120147680 - Semiconductor memory device: A power supply control circuit which can cut off a power supply independently is provided for each column in a memory cell array. The power supply control circuit is controlled by a circuit which is provided for each column and determines whether or not it is necessary to hold information,... Agent: Panasonic Corporation

20120147678 - Buffering systems for accessing multiple layers of memory in integrated circuits: Embodiments of the invention relate generally to data storage and computer memory, and more particularly, to systems, integrated circuits and methods for accessing memory in multiple layers of memory implementing, for example, third dimension memory technology. In a specific embodiment, an integrated circuit is configured to implement write buffers to... Agent: Unity Semiconductor Corporation

20120147679 - Method for conducting reference voltage training: A method for conducting reference voltage training includes setting levels of a reference voltage in response to code signals and receiving and storing data for the respective levels of the reference voltage, and simultaneously outputting the stored data.... Agent: Hynix Semiconductor Inc.

20120147682 - Memory elements having configurable access duty cycles and related operating methods: Apparatus and methods are provided for accessing memory elements. An exemplary memory element includes an array of memory cells and a control module. Each memory cell of the array is coupled to an access line, wherein the control module is configured to assert a first signal for a write duty... Agent: Advanced Micro Devices, Inc.

20120147684 - Memory refresh apparatus and method: A memory refresh apparatus and method are operable such that in response to the receipt of a refresh control signal, a plurality of refresh control signals is sent to the memory circuits at different times.... Agent: Google Inc.

20120147683 - Semiconductor memory device: A memory cell is provided at an intersection of a word line and a bit line, and a dummy cell is provided at an intersection of a dummy word line and a dummy bit line. A delay circuit delays a signal read into the dummy bit line to generate a... Agent: Kabushiki Kaisha Toshiba

20120147685 - Semiconductor storage device: A semiconductor storage device including an open bit line core architecture includes a plurality of array areas, wherein each of the array areas includes two redundant array blocks, a plurality of real array blocks, and a power supply capacity control unit. The two redundant array blocks contain only redundant word... Agent: Fujitsu Semiconductor Limited

20120147686 - Semiconductor device having hierarchical bit line structure and control method thereof: Disclosed herein is a semiconductor device comprising a global bit line and a local bit line, and a switch coupled therebetween. Upon performing a precharge operation, a precharge voltage is supplied to the global bit line with turning the switch ON, so that the local bit line receives the precharge... Agent: Elpida Memory, Inc.

20120147687 - Semiconductor memory device: A row decoder is disposed on a side of a memory cell array in a column direction and supplies one of word lines with a first drive signal for selecting one of memory cells. A dummy word line is formed extending in the column direction. A dummy bit line is... Agent: Kabushiki Kaisha Toshiba

20120147688 - Integrated circuits, systems, and methods for reducing leakage currents in a retention mode: An integrated circuit includes at least one memory array for storing data. A first switch is coupled with the memory array. A first power line is coupled with the first switch. The first power line is operable to supply a first power voltage. A second switch is coupled with the... Agent: Taiwan Semiconductor Manufacturing Company, Ltd.

20120147689 - Three dimensional non-volatile storage with multi block row selection: A three-dimensional array adapted for memory elements that reversibly change a level of electrical conductance in response to a voltage difference being applied across them. Memory elements are formed across a plurality of planes positioned different distances above a semiconductor substrate. Bit lines to which the memory elements of all... Agent:

20120147690 - Memory accessing device: A memory accessing device includes a generator which generates K (K: an integer equal to or more than two) of address coefficients corresponding to a first mode whereas generates L (L: an integer more than K) of address coefficients corresponding to a second mode. A first converter converts each value... Agent: Sanyo Electric Co., Ltd.

20120147691 - Semiconductor storage device and memory system: A semiconductor storage device includes an external terminal to which a first signal is supplied, a core circuit, and an access operation control circuit that generates a signal indicating an access operation mode to the core circuit for subsequent cycles based on a pulse width of the first signal.... Agent: Fujitsu Semiconductor Limited

20120147692 - Semiconductor device outputting read data in synchronization with clock signal: A semiconductor device is provided with a clock output control circuit which supplies a long-period clock signal having a period longer than an internal clock signal within an active period and supplies the internal clock signal within a read period subsequent to the active period, a clock transfer circuit which... Agent: Elpida Memory, Inc.

  
06/07/2012 > 47 patent applications in 24 patent subcategories. invention type

20120140540 - Charge sharing in a tcam array: A memory cell includes a storage capacitor, a read line, and a storage transistor, where the storage transistor is connected to the read line and is subject to activation by a charge in the storage capacitor. An in-memory processor includes a memory array which stores data, and an activation unit... Agent:

20120140541 - Memory built-in self test scheme for content addressable memory array: A method and apparatus for testing a content addressable memory (CAM) array includes writing known data to the CAM array and providing comparison data to the CAM array. A determination is made whether the CAM array is operating correctly responsive to a comparison of the known data and the comparison... Agent: Advanced Micro Devices, Inc.

20120140542 - Arrays of nonvolatile memory cells: Disclosed is an array of nonvolatile memory cells includes five memory cells per unit cell. Also disclosed is an array of vertically stacked tiers of nonvolatile memory cells that includes five memory cells occupying a continuous horizontal area of 4F2 within an individual of the tiers. Also disclosed is an... Agent:

20120140543 - One time programming memory and method of storage and manufacture of the same: The present invention relates to a one time programming memory and method of storage and manufacture of the same. It belongs to microelectronic memory technology and manufacture field. The one time programming memory comprises a diode (10) having a unidirectional conducting rectification characteristic and a variable-resistance memory (20) having a... Agent: Institute Of Microelectronics, Chinese Academy Of Sciences

20120140546 - Multi-bit resistance-switching memory cell: A non-volatile storage apparatus comprises a set of Y lines, a set of X lines and a plurality of memory cells in communication with the set of X lines and the set of Y lines. Each memory cell of the plurality of memory cells includes a resistance element in a... Agent:

20120140547 - Multi-bit resistance-switching memory cell: A non-volatile storage apparatus comprises a set of Y lines, a set of X lines and a plurality of memory cells in communication with the set of X lines and the set of Y lines. Each memory cell of the plurality of memory cells includes a resistance element in a... Agent:

20120140549 - Nonvolatile semiconductor memory device: A nonvolatile semiconductor memory device comprises a memory cell array including first and second mutually crossing lines and electrically erasable programmable memory cells arranged at intersections of the first and second lines, each memory cell containing a variable resistor operative to nonvolatilely store the resistance thereof as data and a... Agent: Kabushiki Kaisha Toshiba

20120140545 - Semiconductor device and method of sensing data of the semiconductor device: In one example embodiment, the semiconductor device includes a memory cell array having at least one memory cell disposed in a region at which at least one bit line and at least one word line cross. A sensing unit senses data stored in the at least one memory cell. The... Agent: Samsung Electronics Co., Ltd.

20120140544 - Semiconductor memory apparatus and method of driving the same: A semiconductor memory apparatus includes a resistive memory cell configured to be applied with a command voltage pulse with a different voltage level, depending upon an input command, and a feedback unit coupled between one end and the other end of the resistive memory cell, and configured to detect whether... Agent: Hynix Semiconductor Inc.

20120140548 - Semiconductor memory device: According to one embodiment, semiconductor memory device includes: semiconductor substrate; parallel first lines stacked on substrate; parallel second lines intersecting first lines; memory cell array including memory cells at intersections of first and second lines and each including variable resistance element and selecting element series-connected together; first control circuit provided... Agent: Kabushiki Kaisha Toshiba

20120140550 - Integrated circuit, method for driving the same, and semiconductor device: An integrated circuit which can be switched to a resting state and can be returned from the resting state rapidly is provided. An integrated circuit whose power consumption can be reduced without the decrease in operation speed is provided. A method for driving the integrated circuit is provided. The integrated... Agent: Semiconductor Energy Laboratory Co., Ltd.

20120140551 - Static random access memory (sram) write assist circuit with leakage suppression and level control: A static random access memory (SRAM) write assist circuit with leakage suppression and level control is described. In one embodiment, the SRAM write assist circuit increases the amount of boost provided in a write cycle, while in another embodiment, the SRAM write assist circuit limits the amount of boost provided... Agent: International Business Machines Corporation

20120140552 - Write assist static random access memory cell: Static random access memory (SRAM) cells are disclosed. In one example embodiment the SRAM cell includes a latch having a first node and a second node for storing bit information at the first node and a complement of the bit at the second node. The SRAM cell further includes a... Agent:

20120140554 - Compact low-power asynchronous resistor-based memory read operation and circuit: A compact, low-power, asynchronous, resistor-based memory read circuit includes a memory cell having a plurality of consecutive memory states, each of said states corresponding to a respective output voltage. A sense amplifier reads the state of the memory cell. The sense amplifier includes a voltage divider configured to receive the... Agent: International Business Machines Corporation

20120140555 - Multilevel phase change memory operation: Methods, devices, and systems associated with multilevel phase change memory cells are described herein. One or more embodiments of the present disclosure include operating a phase change memory device by placing a phase change memory cell in a reset state and applying a selected programming pulse to the phase change... Agent: Micron Technology, Inc.

20120140553 - Reversible low-energy data storage in phase change memory: A phase change memory (PCM) device utilizes low energy pulses to write data to PCM storage elements (cells). Methods, devices and systems are described that use low energy reset pulses to reset cells that have been previously set using a method that keeps a portion of the PCM cells in... Agent:

20120140556 - Method of operating flash memory: A method of operating a flash memory is described. When a first storage site has 2n program levels, the numbers of program levels of the storage sites neighboring to the first storage site are set to be 2n-1. When a second storage site has 2n-1 program levels, the numbers of... Agent: Macronix International Co., Ltd.

20120140557 - Programming method for non-volatile memory device: Provided is a method of programming a non-volatile memory device. The method includes applying a first programming pulse to a corresponding wordline of the non-volatile memory device, applying a second programming pulse to the wordline, wherein a voltage of the second programming pulse is different from that of the first... Agent: Samsung Electronics Co., Ltd.

20120140558 - Non-volatile semiconductor memory device: A control circuit applies a write pulse voltage to a selected word line to perform a write operation to 1-page memory cells along the selected word line. The circuit then performs a verify read operation to confirm whether the data write to the 1-page memory cells is completed. According to... Agent: Kabushiki Kaisha Toshiba

20120140559 - Selective memory cell program and erase: Techniques are disclosed herein for programming memory arrays to achieve high program/erase cycle endurance. In some aspects, only selected word lines (WL) are programmed with other WLs remaining unprogrammed. As an example, only the even word lines are programmed with the odd WLs left unprogrammed. After all of the even... Agent:

20120140561 - Memory device capable of improving write processing speed and memory control method: According to one embodiment, a memory device includes a memory unit, a first storage unit, a second storage unit, a third storage unit, a data move unit, and a controller. The first storage unit stores a logical address and an intermediate address. The second storage unit stores the intermediate address... Agent: Kabushiki Kaisha Toshiba

20120140560 - Method and memory controller for reading data stored in flash memory by referring to binary digit distribution characteristics of bit sequences read from flash memory: An exemplary method for reading data stored in a flash memory includes: controlling the flash memory to perform a plurality of read operations upon each of a plurality of memory cells included in the flash memory; obtaining a plurality of bit sequences read from the memory cells, respectively, wherein the... Agent:

20120140564 - Non-volatile one-time-programmable and multiple-time programmable memory configuration circuit: A programmable non-volatile configuration circuit uses a pair of non-volatile memory devices arranged in a pull-up and pull-down arrangement. The non-volatile memory devices have floating gates that overlaps a variable portion of a source/drain region. This allows a programming voltage for the device to be imparted to the floating gate... Agent: Invensas Corporation

20120140562 - Nonvolatile memory device and method of making the same: A nonvolatile memory device includes a substrate, a structure including a stack of alternately disposed layers of conductive and insulation materials disposed on the substrate, a plurality of pillars extending through the structure in a direction perpendicular to the substrate and into contact with the substrate, and information storage films... Agent: Samsung Electronics Co., Ltd.

20120140563 - Pump circuit and semiconductor memory device including the same: A pump circuit includes a plurality of clock control circuits configured to transfer a clock to respective output terminals in response to respective pump-off signals or block the clock from being transferred to the respective output terminals, a plurality of charge pumps configured to generate respective high voltages by performing... Agent:

20120140565 - Scalable electrically eraseable and programmable memory: A non-volatile memory including one or more EEPROM cell pairs. Each EEPROM cell pair includes three transistors and stores two data bits, effectively providing a 1.5 transistor EEPROM cell. An EEPROM cell pair includes a first non-volatile memory transistor connected to a first bit line, a second non-volatile memory transistor... Agent: Semiconductor Components Industries, L.L.C.

20120140569 - Memory cell operation: Embodiments of the present disclosure provide methods, devices, modules, and systems for programming memory cells. One method includes determining a quantity of erase pulses used to place a group of memory cells of the array in an erased state, and adjusting at least one operating parameter associated with programming the... Agent: Micron Technology, Inc.

20120140567 - Nand step up voltage switching method: Methods and memories having switching points for changing Vstep increments according to a level of a multilevel cell being programmed include programming at a smaller Vstep increment in narrow threshold voltage situations and programming at a larger Vstep increment where faster programming is desired.... Agent: Micron Technology, Inc.

20120140568 - Programming memory with reduced pass voltage disturb and floating gate-to-control gate leakage: Program disturb is reduced in a non-volatile storage system by programming storage elements on a selected word line WLn in separate groups, according to the state of their WLn−1 neighbor storage element, and applying an optimal pass voltage to WLn−1 for each group. Initially, the states of the storage elements... Agent:

20120140566 - Programming method of non-volatile memory device: A programming method includes setting the voltages of bit lines, performing a program operation, performing a program verify operation by supplying a program verify voltage and determining whether all of the memory cells of the selected page have been programmed with a target threshold voltage or higher, counting the number... Agent:

20120140570 - Eeprom with increased reading speed: In an EEPROM consisting of a NAND cell in which a plurality of memory cells are connected in series, the control gate voltage Vread of the memory cell in a block selected by the data read operation is made different from the each of the voltages Vsg1, Vsg2 of the... Agent: Kabushiki Kaisha Toshiba

20120140571 - Electronically scannable multiplexing device: An electronically scannable multiplexing device is capable of addressing multiple bits within a volatile or non-volatile memory cell. The multiplexing device generates an electronically scannable conducting channel with two oppositely formed depletion regions. The depletion width of each depletion region is controlled by a voltage applied to a respective control... Agent: International Business Machines Corporation

20120140572 - Semiconductor memory device and method of operating the same: A semiconductor memory device includes a switching element coupled between a power supply line and an output terminal of a power supply circuit for supplying a power supply voltage, wherein the switching element is configured to be turned on in response to a standby signal, a page buffer including a... Agent:

20120140573 - Semiconductor memory device and method of operating the same: A semiconductor memory device includes a page buffer configured to store data received from selected memory cells in response to a read command, a first register configured to store first data received from the page buffer in response to a first control signal, a second register configured to store second... Agent:

20120140574 - Non-volatile memory device and sensing method thereof: A non-volatile memory device is disclosed, which performs a sensing operation using a current. The non-volatile memory device includes a cell array including one or more unit cells, configured to read or write data, a current-voltage converter configured to convert a sensing current corresponding to data stored in the unit... Agent: Hynix Semiconductor Inc.

20120140576 - Memory device, test operation method thereof, and system including the same: A test operation method of a memory device is provided. The test operation method includes a reference current generator generating a reference current and providing a reference voltage generated based on the reference current to one of input terminals of a sense amplifier; providing a read voltage generated based on... Agent:

20120140577 - Multi-chip package and method of operating the same: A semiconductor memory device includes a memory cell array including first memory cells for storing data and second memory cells for storing chip identification (ID) information, a data comparison circuit configured to compare input data and the stored data of the first memory cells and to output comparison data, and... Agent:

20120140579 - Multi-chip package and operating method thereof: A multi-chip package includes a voltage generating circuit configured to generate a power source voltage and a plurality of memory chips coupled to the voltage generating circuit to each receive the power source voltage, wherein the memory chips are each configured to postpone an operation if the power source voltage... Agent:

20120140575 - Process tolerant large-swing sense amplfier with latching capability: A process-tolerant large-swing sense amplifier with latching capability includes top-array and bottom-array access. The sense amplifier provides improved tolerance to process variation, reduces design complexity, reduces power consumption, and reduces the physical footprint of the circuit. In addition, the sense amplifier provides write-through functionality through the read data bus.... Agent: Oracle International Corporation

20120140578 - Semiconductor device having plural internal voltage generating circuits and method of controlling the same: Such a device is disclosed that includes a terminal, a first voltage generator generating, when activated, a voltage at the terminal and stopping, when deactivated, generating the voltage, and a second voltage generator generating, when activated, the voltage at the terminal and stopping, when deactivated, generating the voltage. The first... Agent: Elpida Memory, Inc.

20120140580 - Integrated circuit having voltage generation circuitry for memory cell array, and method of operating and/or controlling same: A method of generating a voltage on an integrated circuit device comprising a memory cell array including (i) a plurality of memory cells, arranged in a matrix of rows and columns, and (ii) a plurality of bit lines, wherein each bit line includes a plurality of memory cells. The integrated... Agent: Micron Technology, Inc.

20120140581 - Multiple cycle memory write completion: A memory system that reduces the memory cycle time of a memory cell by performing an incomplete write operation. The voltage on a storage node of the memory cell does not reach a full supply voltage during the incomplete write operation. The incomplete write operation is subsequently completed by one... Agent: Mosys, Inc.

20120140582 - Write circuitry for hierarchical memory architectures: A memory architecture includes a plurality of local input and output circuitries, with each local input and output circuitry associated with at least one memory bank. The memory architecture also includes a global input and output circuitry, which includes a plurality of global sub-write circuitries, is coupled to the plurality... Agent: Stmicroelectronics Pvt. Ltd.

20120140583 - Multi-chip memory devices and methods of controlling the same: A multi-chip memory device and a method of controlling the same are provided. The multi-chip memory device includes a first memory chip; and a second memory chip sharing an input/output signal line with the first memory chip, wherein each of the first memory chip and the second memory chip determines... Agent: Samsung Electronics Co., Ltd.

20120140584 - Semiconductor system, semiconductor memory apparatus, and method for input/output of data using the same: A semiconductor system, a semiconductor memory apparatus, and a method for input/output of data using the same are disclosed. The semiconductor system includes a controller and a memory apparatus where the controller is configured to transmit a clock signal, a data output command, an address signal, and a second strobe... Agent: Hynix Semiconductor Inc.

20120140585 - Retention voltage generation: An integrated circuit and method are provided, the integrated circuit comprising retention voltage generation circuitry which receives a supply voltage from a supply voltage node and provides a retention voltage at a retention voltage node. Functional circuitry is connected between the retention voltage node and a reference voltage node,... Agent: Arm Limited

20120140586 - Nonvolatile memory device having stacked transistor configuration: A nonvolatile memory device comprises a memory cell array comprising a plurality of memory blocks, an address decoder that selects one of the memory blocks in response to an input address and generates a first control signal and a second control signal, a plurality of metal lines connected with the... Agent: Samsung Electronics Co., Ltd.

Previous industry: Electric power conversion systems
Next industry: Agitating


######

RSS FEED for 20141204: xml
Integrate FreshPatents.com into your RSS reader/aggregator or website to track weekly updates.
For more info, read this article.

######

Thank you for viewing Static information storage and retrieval patents on the FreshPatents.com website. These are patent applications which have been filed in the United States. There are a variety ways to browse Static information storage and retrieval patent applications on our website including browsing by date, agent, inventor, and industry. If you are interested in receiving occasional emails regarding Static information storage and retrieval patents we recommend signing up for free keyword monitoring by email.



Results in 1.2754 seconds

PATENT INFO