|Static information storage and retrieval patents - Monitor Patents|
USPTO Class 365 | Browse by Industry: Previous - Next | All
05/2012 | Recent | 14: | | | Sep | Aug | Jul | Jun | May | Apr | Mar | Feb | Jan | 13: Dec | Nov | Oct | Sep | Aug | Jul | Jun | May | Apr | Mar | Feb | Jan | 12: Dec | Nov | Oct | Sep | Aug | July | June | May | April | Mar | Feb | Jan | 11: Dec | Nov | Oct | Sep | Aug | Jul | Jun | May | Apr | Mar | Feb | Jan | 10: Dec | Nov | Oct | Sep | Aug | Jul | Jun | May | Apr | Mar | Feb | Jan | | 09: Dec | Nov | Oct | Sep | Aug | Jl | Jn | May | Apr | Mar | Fb | Jn | | 2008 | 2007 |
Static information storage and retrieval May archived by USPTO category 05/12Below are recently published patent applications awaiting approval from the USPTO. Recent week's RSS XML file available below.
Listing for abstract view: USPTO application #, Title, Abstract excerpt,Patent Agent. Listing format for list view: USPTO National Class full category number, title of the patent application. 05/31/2012 > 38 patent applications in 27 patent subcategories. archived by USPTO category
20120134193 - Semiconductor device having plural memory chip: A semiconductor device includes a stacked plurality of memory chips. The memory chips each include a plurality of memory banks, a plurality of read/write buses that are assigned to the respective memory banks, and a plurality of penetration electrodes that are assigned to the respective read/write buses and arranged through... Agent: Elpida Memory, Inc.
20120134192 - Semiconductor memory device and method for fabricating the same: A semiconductor memory device includes: a plurality of mats; a plurality of sense amplifier regions disposed on a side of the plurality of mats; and a plurality of main bit lines overlapping with a plurality of secondary bit lines, respectively, in regions for the plurality of mats, wherein the plurality... Agent:
20120134194 - Bridge device architecture for connecting discrete memory devices to a system: A bridge device architecture for connecting discrete memory devices. The bridge device is used in conjunction with a composite memory device including at least one discrete memory device. The bridge device includes a local control interface for connecting to the at least one discrete memory device, a local input/output interface... Agent: Mosaid Technologies Incorporated
20120134195 - Memory device and manufacturing method thereof: The present invention relates to a memory device having 4F2 size cells and a method for fabricating the same. The memory device comprises plural word lines arranged parallel to each other in one direction, plural bit lines arranged parallel to each other, and plural memory cells having a transistor that... Agent:
20120134196 - Analog memories utilizing ferroelectric capacitors: A ferroelectric memory having a plurality of ferroelectric memory cells, each ferroelectric memory cell including a ferroelectric capacitor is disclosed. The ferroelectric memory includes read and write lines and a plurality of ferroelectric memory cell select buses, one select bus corresponding to each of the ferroelectric memory cells. Each of... Agent:
20120134197 - Memory cell and memory device using the same: Provided is a memory cell including: a ferroelectric transistor; a plurality of switching elements electrically connected to the ferroelectric transistor; and a plurality of control lines for transmitting individual control signals to each of the plurality of switching element for separately controlling the plurality of switching elements. The plurality of... Agent: Eletronics And Telecommunications Research Institute
20120134198 - Memory system: A memory system includes a memory cell array including a plurality of memory cells electrically connected to pairs of bit lines once a word line is activated; latch portions connected to respective pairs of bit lines; a sense amplifier connected to the latch portions; and a control circuit configured to... Agent: Kabushiki Kaisha Toshiba
20120134200 - Magnetic memory cell with multi-level cell (mlc) data storage capability: Method and apparatus for writing data to a magnetic memory element, such as a spin-torque transfer random access memory (STRAM) memory cell. In accordance with various embodiments, a multi-level cell (MLC) magnetic memory cell stack has first and second magnetic memory elements connected to a first control line and a... Agent: Seagate Technology LLC
20120134201 - Magnetic memory element and driving method for same: A magnetic memory element and a method of driving such an element are disclosed. The magnetic memory element has a magnetic tunnel junction portion with a spin-valve structure having a perpendicular magnetization free layer formed of a perpendicular magnetization film, a perpendicular magnetization pinned layer formed of a perpendicular magnetization... Agent: Fuji Electronic Co., Ltd
20120134199 - Magnetic switching cells and methods of making and operating same: Logic circuits based, at least in part, on use of spin-torque transfer (STT) to switch the magnetization—and hence the logic state—of a magnetic material are disclosed. Aspects of the invention include novel STT-based switching devices, new configurations of known STT-based devices into useful logic circuits, common logic circuits and system... Agent:
20120134204 - Concentric phase change memory element: The present invention in one embodiment provides a memory device including a first electrode; a second electrode; and a memory cell positioned between the first electrode and the second electrode, the memory cell including a core of a first phase change material and a cladding of a second phase change... Agent: International Business Machines Corporation
20120134203 - Semiconductor device and data processing system: In a phase change memory, when M bit (8 bits=1 byte) data is written, erase operation and program operation are performed in units of n bit (M>n) data. Further, when M bit data is written, program operation is performed in units of the n bit (M>n) data. Further, when M... Agent: Hitachi, Ltd.
20120134202 - Verify or read pulse for phase change memory and switch: Embodiments disclosed herein may relate to applying verify or read pulses for phase change memory and switch (PCMS) devices.... Agent: Micron Technology, Inc.
20120134205 - Operating method for memory unit: An operating method for a memory unit is provided, wherein the memory unit includes a well region, a select gate, a first gate, a second gate, an oxide nitride spacer, a first diffusion region, and a second diffusion region. The operating method for the memory unit comprises the following steps.... Agent: Ememory Technology Inc.
20120134206 - Multilevel memory device:
20120134207 - Non-volatile memory device and read method thereof: In one embodiment, the method for reading memory cells in an array of non-volatile memory cells includes reading data from a memory cell using a set of hard decision voltages and at least a first set of soft decision voltages based on a single read command.... Agent: Samsung Electronics Co., Ltd.
20120134208 - Nonvolatile memory device, memory system, and read method thereof: A non-volatile memory device performs a read operation for compensating for coupling due to an adjacent memory cell. With the read operation of the non-volatile memory device, the coupling effect included in a read result of the selected memory cell is compensated on the basis of a program state of... Agent: Samsung Electronics Co., Ltd.
20120134209 - Single-transistor eeprom array and operation methods: A method includes performing an operation on an electrically erasable programmable read-only memory (EEPROM) array. The operation is selected from a program operation and an erase operation. The EEPROM array includes EEPROM cells arranged in rows and columns, and a plurality of word-lines extending in a column direction. Each of... Agent: Taiwan Semiconductor Manufacturing Company, Ltd.
20120134211 - Memory system: A memory system includes: a plurality of banks each including a memory cell array and a sense amplifier; a buffer circuit electrically connected to the plurality of banks; a switch circuit configured to switch on and off an electrical connection between the buffer circuit and each of the plurality of... Agent: Kabushiki Kaisha Toshiba
20120134210 - Nonvolatile semiconductor memory device: When selectively erasing one sub-block, a control circuit applies, in a first sub-block, a first voltage to bit lines and a source line, and applies a second voltage smaller than the first voltage to the word lines. Then, the control circuit applies a third voltage lower than the first voltage... Agent: Kabushiki Kaisha Toshiba
20120134212 - Nonvolatile semiconductor memory device: A nonvolatile semiconductor memory device according to an embodiment of the present invention includes: a memory cell array having a plurality of memory cells arranged therein, each of the memory cells having a charge storage layer and a control electrode; and a control unit configured to execute a write cycle... Agent: Kabushiki Kaisha Toshiba
20120134213 - Method compensation operating voltage, flash memory device, and data storage device: Disclosed is a method generating a compensated operating voltage, such as a read voltage, in a non-volatile memory device, and a related non-volatile memory device. The operating voltage is compensated in response to one or more memory cell conditions such as temperature variation, programmed data state or physical location of... Agent: Samsung Electronics Co., Ltd.
20120134214 - Semiconductor memory device and method of programming the same: A program method of a semiconductor memory device includes performing a least significant bit (LSB) program operation for target LSB program cells of a selected page, increasing the threshold voltages of target most significant bit (MSB) program cells of the selected page before performing an MSB operation for the target... Agent:
20120134215 - Memory devices having select gates with p type bodies, memory strings having separate source lines and methods: Memory devices and methods of operating memory devices are shown. Configurations described include a memory cell string having an elongated n type body region and having select gates with p type bodies. Configurations and methods shown can provide a reliable bias to a body region for memory operations such as... Agent:
20120134216 - Integrated circuit having memory array including ecc and column redundancy, and method of operating same: An integrated circuit device comprising a memory cell array having a plurality of memory cells arranged in a matrix of rows and columns; multiplexer circuitry, coupled to the memory cell array, comprising a plurality of data multiplexers, each data multiplexer having a plurality of inputs, comprising (i) a first input... Agent: Micron Technology, Inc.
20120134217 - Semiconductor device having plural banks: A semiconductor device is provided with a control circuit generating a plurality of first control signals indicating timings at which column switches conduct at the time of reading and a plurality of second control signals indicating timings at which the column switches conduct at the time of writing. The control... Agent: Elpida Memory, Inc.
20120134218 - Charge pump control scheme using frequency modulation for memory word line: A memory includes a word line having a word line voltage, a charge pump coupled to the word line, and a dynamic feedback control circuit coupled to the charge pump. The dynamic feedback control circuit is capable of changing a clock frequency of a clock signal supplied the charge pump... Agent: Taiwan Semiconductor Manufacturing Company, Ltd.
20120134219 - Mode changing circuitry: A circuit includes a memory cell having a ground reference node, a switch coupled to the ground reference node, and a mode changing circuit having an output coupled to the switch. The mode changing circuit is configured to change a logic state of the output between a first output logic... Agent: Taiwan Semiconductor Manufacturing Company, Ltd.
20120134221 - Word-line level shift circuit: A dual word-line level shifter circuit and associated SRAM. A circuit is disclosed that includes a first transistor gated by a data input at the lower voltage, and a second transistor gated by a restore input at the higher voltage, wherein the first and second transistors are coupled along a... Agent: International Business Machines Corporation
20120134220 - Write assist circuitry: A circuit includes a word line driver for driving a world line and a tracking word line driver for driving a tracking word line. The pulse width of a world line signal on the world line is driven to be larger than that of a tracking world line signal on... Agent: Taiwan Semiconductor Manufacturing Company, Ltd.
20120134223 - Clock generating circuit, semiconductor device including the same, and data processing system: A semiconductor device includes a delay circuit supplied with a first clock signal and a first phase determination signal and producing a second clock signal, the delay circuit controlling the second clock signal such that a delay in phase of the second clock signal to the first clock signal is... Agent: Elpida Memory, Inc.
20120134222 - Semiconductor device and method of controlling the same: A semiconductor device includes a data input/output circuit connected to the memory cell array via a sense circuit, and an access control circuit that controls access to the memory cell array. The access control circuit includes: a first signal unit outputting a first signal for activating or inactivating a word... Agent: Elpida Memory, Inc.
20120134224 - Verifying multi-cycle self refresh operation of semiconductor memory device and testing the same: A semiconductor memory device includes a memory cell array, a tag information register, a refresh control circuit and a DQ pin. The memory cell array includes multiple memory cells divided into first cells and second cells according to corresponding data retention times. The tag information register stores refresh cycle information... Agent: Samsung Electronics Co., Ltd.
20120134225 - Sense amplifier latch with integrated test data multiplexer: A sense amplifier latch may be provided to controllably latch the output of a sense amplifier. The latch may open in response to assertion of a latch enable signal to receive data, and close in response to deassertion of the latch enable signal to capture and store the received data.... Agent:
20120134226 - Sense amplifier and sense amplifier latch having common control: A sense amplifier of a memory array may be provided to amplify data presented from storage cells of the memory array. Additionally, a sense amplifier latch may be provided to store data received from the sense amplifier. The sense amplifier may be enabled for operation by a sense amplifier enable... Agent:
20120134227 - Semiconductor device having sense amplifier: For example, four driver transistors are arranged in wells so as to adjoin both sides of each of two element isolation regions. Two pairs of cross-coupled sense transistors are arranged in the wells at positions farther from the element isolation regions than the driver transistors are. Such an arrangement provides... Agent: Elpida Memory, Inc.
20120134228 - Charge pump control scheme for memory word line: A memory includes a word line, a charge pump coupled to the word line, and a charge pump control circuit coupled to the charge pump. The charge pump control circuit is configured to turn on the charge pump if the word line voltage is lower than a first threshold voltage... Agent: Taiwan Semiconductor Manufacturing Company, Ltd.
20120134229 - Concurrent multiple-dimension word-addressable memory architecture: An N-dimension addressable memory is disclosed. The memory includes an N-dimension array of bit ceils and logic configured to address each bit cell using N-Dimension Addressing (NDA), where N is at least two and the array of bit cells is addressable by N orthogonal address spaces. Each bit cell of... Agent:05/24/2012 > 48 patent applications in 34 patent subcategories. archived by USPTO category
20120127771 - Multi-wafer 3d cam cell: A multi-wafer CAM cell in which the negative effects of increased travel distance have been substantially reduced is provided. The multi-wafer CAM cell is achieved in the present invention by utilizing three-dimensional integration in which multiple active circuit layers are vertically stack and vertically aligned interconnects are employed to connect... Agent: International Business Machines Corporation
20120127772 - Low power sram based content addressable memory: An apparatus comprising a memory array and a plurality of processing circuits. The memory array may be configured to store a plurality of data bits in a plurality of rows and a plurality of columns. A plurality of data words may be stored in a respective plurality of the columns.... Agent:
20120127773 - Semiconductor device having data bus: A semiconductor device is disclosed which comprises a first wiring layer, a second wiring layer formed over the first wiring layer, data input/output terminals, and a data bus formed in the first and second wiring layers. The data bus includes N data lines transmitting data between a predetermined circuit and... Agent: Elpida Memory, Inc.
20120127774 - Semiconductor device and electronic device: All interface pins for transmitting and receiving a signal having a predetermined function of a semiconductor integrated circuit element are formed on an outer periphery of the semiconductor integrated circuit element along one side of the semiconductor integrated circuit element. The one side of the semiconductor integrated circuit element is... Agent: Panasonic Corporation
20120127775 - Secure storage of a codeword within an integrated circuit: The invention discloses an integrated circuit (10) for securely storing a codeword. The value of the codeword is dependent on the mobility (μA, μB, μC) of at least one transistor (TRA, TRB, TRC) of the integrated circuit. The invention further discloses a reader means (15), a method for determining the... Agent: Nxp B.v.
20120127776 - Ferroelectric memory device: A ferroelectric memory device has word, bit, plate lines; memory cells having access gate and ferroelectric capacitor; latch amplifier for latching stored data; and write amplifier for driving bit lines according to write data. The bit lines are precharged to a reference potential before an active period. In active period,... Agent: Fujitsu Semiconductor Limited
20120127777 - Method to improve ferroelectric memory performance and reliability: One embodiment of the present invention relates to a method by which the imprint of a ferroelectric random access memory (FRAM) array is reduced. The method begins when an event that will cause imprint to the memory array is anticipated by an external agent to the device comprising the chip.... Agent: Texas Instruments Incorporated
20120127778 - Memory device: A memory device includes: a transistor array having transistors; and memory elements provided, one for each of the transistors. The transistor array includes a substrate having diffusion layers on a surface thereof, parallel word lines on the substrate, parallel first bit lines provided in a direction perpendicular to the word... Agent: Sony Corporation
20120127780 - Memory resistor adjustment using feedback control: Apparatus and methods related to memory resistors are provided. A feedback controller applies adjustment signals to a memristor. A non-volatile electrical resistance of the memristor is sensed by the feedback controller during the adjustment. The memristor is adjusted to particular values lying between first and second limiting values with minimal... Agent:
20120127779 - Re-writable resistance-switching memory with balanced series stack: A re-writable resistance-switching memory cell includes first and second capacitors in series. The first and second capacitors may have balanced electrical characteristics to allow nearly concurrent, same-direction switching. The first capacitor has a first bipolar resistance switching layer between first and second conductive layers, and the second capacitor has a... Agent:
20120127781 - Semiconductor memory device: To increase a storage capacity of a memory module per unit area, and to provide a memory module with low power consumption, a transistor formed using an oxide semiconductor film, a silicon carbide film, a gallium nitride film, or the like, which is highly purified and has a wide band... Agent: Semiconductor Energy Laboratory Co., Ltd.
20120127783 - Sram cell for single sided write: A first integrated circuit containing a single sided write SRAM cell array, each SRAM cell having a bit passgate and an auxiliary bit-bar driver transistor. A process of operating the first integrated circuit including a single sided read operation in which source nodes of the auxiliary drivers in both addressed... Agent: Texas Instruments Incorporated
20120127782 - Static ram: A static RAM includes a plurality of word lines, a plurality of global bit line pairs, a plurality of static-type memory cells, a plurality of sense amplifiers, a plurality of local bit line pairs provided in correspondence with each global bit line pair, and a plurality of global switches, wherein... Agent: Fujitsu Semiconductor Limited
20120127784 - Semiconductor storage device: According to one embodiment, a dummy cell simulates an operation of a memory cell. A main dummy bit line transmits a signal read out from the dummy cell. An inverter makes a sense amplifier circuit to operate based on a potential of the main dummy bit line. n (n is... Agent: Kabushiki Kaisha Toshiba
20120127786 - Flux programmed multi-bit magnetic memory: An apparatus and associated method for a non-volatile memory cell, such as a multi-bit magnetic random access memory cell. In accordance with various embodiments, a first magnetic tunnel junction (MTJ) is adjacent to a second MTJ having a magnetic filter. The first MTJ is programmed to a first logical state... Agent: Seagate Technology LLC
20120127788 - Mram cells and circuit for programming the same: A circuit includes magneto-resistive random access memory (MRAM) cell and a control circuit. The control circuit is electrically coupled to the MRAM cell, and includes a current source configured to provide a first writing pulse to write a value into the MRAM cell, and a read circuit configured to measure... Agent: Taiwan Semiconductor Manufacturing Company, Ltd.
20120127787 - Spin-transfer torque memory non-destructive self-reference read method: A method of self-reference reading a spin-transfer torque memory unit includes applying a first read current through a magnetic tunnel junction data cell and forming a first bit line read voltage. The magnetic tunnel junction data cell has a first resistance state. Then the method includes applying a second read... Agent: Seagate Technology LLC
20120127785 - Using a nearby cell to provide field assisted switching in a magnetic memory array: Method and apparatus for writing data to a magnetic memory cell, such as a spin-torque transfer random access memory (STRAM) memory cell. In accordance with various embodiments, a write current is applied through a selected magnetic memory cell to initiate magnetic precession of the selected cell to a desired magnetic... Agent: Seagate Technology LLC
20120127790 - Adjustable write bins for multi-level analog memories: Selecting bins in a memory by receiving a target cost for performing writes at an analog memory that is capable of storing a range of values. Possible bins that may be created in the range of values and a cost associated with each possible bin are determined. Each possible bin... Agent: International Business Machines Corporation
20120127789 - Storage node, phase change memory device and methods of operating and fabricating the same: A storage node may include a lower electrode, a phase change layer on the lower electrode and an upper electrode on the phase change layer, and the lower electrode and the upper electrode may be composed of thermoelectric materials having a melting point higher than that of the phase change... Agent:
20120127791 - Nonvolatile memory device, memory system comprising same, and method of programming same: A nonvolatile memory device is programmed using an incremental step pulse programming method comprising a plurality of program loops. Some program loops use a one step verification operation, and other program loops use a two step verification operation.... Agent: Samsung Electronics Co., Ltd.
20120127792 - Semiconductor memory having electrically erasable and programmable semiconductor memory cells: In a nonvolatile memory apparatus, a system bus receives address, command, and/or control signals. Memory cells store bits of data by shifting a threshold voltage to one of plural ranges. In writing a first page, the threshold voltage of a first memory cell remains in a first range or shifts... Agent:
20120127793 - Memory arrays: A memory array includes a control gate, where every memory cell coupled to a first side of the control gate is within a first row of memory cells and every memory cell coupled to a second side of the control gate is within a second row of memory cells, and... Agent: Micron Technology, Inc.
20120127794 - Program verify operation in a memory device: Methods for program verifying, program verify circuits, and memory devices are disclosed. One such method for program verifying includes generating a ramped voltage for a plurality of count values. The ramped voltage is applied to a control gate of a memory cell being program verified. At least a portion of... Agent: Micron Technology, Inc.
20120127795 - Non-volatile memory and manufacturing method thereof and operating method of memory cell: A non-volatile memory and a manufacturing method thereof and a method for operating a memory cell are provided. The non-volatile memory includes a substrate, first and second doped regions, a charged-trapping structure, first and second gates and an inter-gate insulation layer. The first and second doped regions are disposed in... Agent: Macronix International Co., Ltd
20120127796 - Retention in nvm with top or bottom injection: Retention of charges in a nonvolatile memory (NVM) cell having a nitride-based injector (such as SiN, SIRN, SiON) for facilitating injection of holes into a charge-storage layer (for NROM, nitride) of a charge-storage stack (for NROM, ONO) may be improved by providing an insulating layer (for NROM, oxide) between the... Agent: Spansion Israel Ltd
20120127797 - System and method for testing for defects in a semiconductor memory array: A system and method for testing semiconductor memory devices includes a variable voltage input to a memory cell control gate. The voltage to the control gate can be varied from a voltage level used for normal memory cell operation, such as a read operation, to a voltage level that can... Agent: Macronix International Co., Ltd.
20120127798 - Method and apparatus for sharing internal power supplies in integrated circuit devices: A method, system and apparatus for sharing internal power supplies in integrated circuit devices is described. A multiple device integrated circuit 200 including multiple integrated circuits 202-205 each having internal power supplies is contained in an enclosure 201. Integrated circuits 202-205 are described showing how to make external connection to... Agent: Mosaid Technologies Incorporated
20120127799 - Write-precompensation and variable write backoff: A technique for writing data is disclosed. The technique includes estimating an amount of additional voltage on a victim cell of a solid-state storage device caused by writing to one or more other cells in the solid-state storage device, determining a modified write value for the victim cell based at... Agent: Link_a_media Devices Corporation
20120127801 - Method of operating nonvolatile memory device: A method of operating a nonvolatile memory device includes performing a LSB program operation on memory cells coupled to a selected word line and a word line adjacent to the selected word line; performing a first MSB program operation so that the threshold voltages of the memory cells coupled to... Agent:
20120127800 - Pair bit line programming to improve boost voltage clamping: A non-volatile storage system reduces program disturb in a set of non-volatile storage elements by programming using selected bit line patterns which increase the clamped boosting potential of an inhibited channel to avoid program disturb. Alternate pairs of adjacent bit lines are grouped into first and second sets. Non-volatile storage... Agent:
20120127802 - Non-volatile memory device, method of operating the same, and electronic device having the same: In one embodiment, the method includes receiving an operation command, detecting a noise level of a common source line, and adjusting a number of times to perform an operation on a memory cell in response to the operation command based on the detected noise level.... Agent: Samsung Electronics Co., Ltd.
20120127803 - Nonvolatile semiconductor storage device: A nonvolatile semiconductor storage device including a NAND cell unit having a first and a second select gate transistor, a plurality of memory cell transistors series connected between the first and second select gate transistors that are coupled to corresponding word lines, and a peripheral circuit erase verifying the NAND... Agent: Kabushiki Kaisha Toshiba
20120127805 - Memory elements having shared selection signals: Apparatus are provided for memory elements and related computing modules. An exemplary memory element includes a first array of one or more memory cells, a second array of one or more memory cells, write selection circuitry associated with the first array, and read selection circuitry associated with the second array.... Agent: Advanced Micro Devices, Inc.
20120127806 - Memory word line boost using thin dielectric capacitor: A memory includes a word line and a word line boost circuit. The word line boost circuit includes a capacitor having a capacitor dielectric thickness, and a transmission gate coupled to the word line and the capacitor. The transmission gate has a gate-dielectric thickness that is greater than the capacitor... Agent: Taiwan Semiconductor Manufacturing Company, Ltd.
20120127807 - Memory instruction including parameter to affect operating condition of memory: Subject matter disclosed herein relates to techniques to operate memory.... Agent: Micron Technology, Inc.
20120127804 - Memory write error correction circuit: Memory circuit includes; an array, row decoder, column decoder, addressing circuit to receive an address of the data bit, control logic receiving commands and transmitting control signals to memory system blocks, and sensing and write driver circuits coupled to a selected column. A hidden read compare circuit couples between the... Agent: Grandis, Inc.
20120127808 - Integrated circuit memory operation apparatus and methods: Some embodiments include apparatus and methods having a memory cell included in a device, a control line configured to receive a control signal to access the memory cell, and a first line configured to transfer information to and from the memory cell. The control signal has a first level during... Agent:
20120127809 - Precharge signal generation circuit of semiconductor memory apparatus: A precharge signal generation circuit of a semiconductor memory apparatus may comprise a read/write precharge command generation section configured to delay a precharge command by a first delay time set in response to a control signal to generate one of a read precharge command and a write precharge command; and... Agent: Hynix Semiconductor Inc.
20120127810 - Semiconductor memory device and access method thereof: Example embodiments provide a semiconductor memory device that may include: a cell array arranged in pluralities of rows and columns; and a sense amplifier conducting writing and reading operations to the cell array in response to writing and reading commands in correspondence with an access time, which may be variable... Agent:
20120127812 - Semiconductor device, adjustment method thereof and data processing system: A device includes a first semiconductor chip that includes a first memory cell array including a plurality of first memory cells, a first control logic circuit accessing the first memory cell array and producing a plurality of first data signals in response to data stored in selected ones of the... Agent: Elpida Memory, Inc.
20120127811 - Timing generation circuit, semiconductor storage device and timing generation method: According to an embodiment, a semiconductor storage device includes a memory cell array, a plurality of sense amplifiers and a timing generation circuit. The memory cell array includes a plurality of word lines, a plurality of bit lines crossing the plurality of word lines, and a plurality of memory cells... Agent: Kabushiki Kaisha Toshiba
20120127813 - Device and method for storing error information of memory: A device for storing error information of a memory device includes a plurality of parent memories and a plurality of child memories. Each of the parent memories stores a row address and a column address of one defective cell. Each of the child memories stores a column address of a... Agent: Hynix Semiconductor Inc.
20120127814 - Semiconductor device performing stress test: A semiconductor device includes a memory cell array that is divided into a plurality of memory cell mats by a plurality of sense amplifier arrays. Each of the plurality of memory cell mats includes a plurality of word lines and a test circuit for performing a test control to activate,... Agent: Elpida Memory, Inc.
20120127815 - Sense amplifier and method of sensing data using the same: Some embodiments regard a circuit comprising a pre-charge circuit and a latch circuit. The pre-charge circuit charges a voltage node to a pre-determined voltage level based on which the latch circuit generates a feedback signal to stop the pre-charge circuit from charging.... Agent: Taiwan Semiconductor Manufacturing Company, Ltd.
20120127816 - Semiconductor device having hierarchical bit line structure: Disclosed herein is a semiconductor device comprising a memory cell, a local bit line coupled to the memory cell, a global bit line provided correspondingly to the local bit line, and a bit line control circuit coupled between the local bit line and the global bit line. The bit line... Agent: Elpida Memory, Inc.
20120127817 - Semiconductor device having reset function: A semiconductor device comprises a memory cell array, a row control circuit for controlling an access to the memory cell array, and a refresh control circuit for instructing the row control circuit to refresh the memory cell array. After temporarily transiting to a reset state due to an activation of... Agent: Elpida Memory, Inc.
20120127818 - Sharing access to a memory among clients: In a memory device having a set of memory banks to store content data, at least two requests to perform respective memory operations in a first memory bank are received during a single clock cycle. One or more of the at least two requests is blocked from accessing the first... Agent:05/17/2012 > 54 patent applications in 30 patent subcategories. archived by USPTO category
20120120701 - Ternary content addressable memory using phase change devices: A content addressable memory device with a plurality of memory cells storing ternary data values of high, low, and don't care. An aspect of the content addressable memory device is the use of first memory elements and second memory elements in the memory cells. The first and second memory elements... Agent: International Business Machines Corporation
20120120702 - Power saving technique in a content addressable memory during compare operations: An apparatus comprising a first circuit, a driver circuit and a memory circuit. The first circuit may be configured to generate a supply voltage that changes between (i) a first voltage when an input signal is in a first state and (ii) a second voltage when the input signal is... Agent:
20120120703 - Memory device with asymmetrical bit cell arrays and balanced resistance and capacitance: An SRAM or other semiconductor integrated circuit device includes a memory cell array having a layout portion in which a plurality of cell arrays extend along a substantially parallel pair of bit lines. Each cell array is separated from an adjacent cell array by a strap cell. As the cell... Agent: Taiwan Semiconductor Manufacturing Co., Ltd.
20120120705 - Semiconductor device having bit lines and local i/o lines: The present invention efficiently decides line failure and contact failure in a semiconductor device. The semiconductor device has a plurality of bit line groups in which connection with local I/O lines is controlled by the same column selection signal line. A failure detecting circuit compares a first data group read... Agent: Elpida Memory, Inc.
20120120706 - Semiconductor memory device: A plurality of contact plugs to be connected to a drain region or a source region of each of transistors constituting a sub-word line driver that drives a sub-word line are formed, by using a SAC line technique of selectively etching an insulation layer that covers each of the transistors... Agent: Elpida Memory, Inc.
20120120704 - Single event upset hardened static random access memory cell: A single event upset (SEU) hardened memory cell to be utilized in static random access memories is disclosed. The SEU hardened memory cell includes a first transistor, a second transistor and a first resistor connected between a source of the first transistor and a drain of the second transistor. The... Agent:
20120120707 - Semiconductor device with otp memory cell: A semiconductor device with an OTP memory cell includes a first MOS transistor having a first gate terminal connected to a first line, and a first terminal connected to a first node, a second MOS transistor having a second gate terminal connected to a second line, and a first terminal... Agent: Hynix Semiconductor Inc.
20120120708 - Method of switching out-of-plane magnetic tunnel junction cells: A method of switching the magnetization orientation of a ferromagnetic free layer of an out-of-plane magnetic tunnel junction cell, the method including: passing an AC switching current through the out-of-plane magnetic tunnel junction cell, wherein the AC switching current switches the magnetization orientation of the ferromagnetic free layer.... Agent: Seagate Technology LLC
20120120713 - Asymmetric write current compensation using gate overdrive for resistive sense memory cells: Apparatus and associated method for asymmetric write current compensation for resistive sense memory (RSM) cells, such as but not limited to spin-torque transfer random access memory (STRAM) or resistive random access memory (RRAM) cells. In accordance with some embodiments, an RSM cell includes an RSM element coupled to a switching... Agent: Seagate Technology LLC
20120120712 - Forming method for variable resistance nonvolatile memory element, and variable resistance nonvolatile memory device: An optimum forming method of performing a forming for a variable resistance element to maximize an operation window of the variable resistance element is provided. The forming method is used to initialize a variable resistance element (100). The forming method includes: a determination step (S35) of determining whether or not... Agent:
20120120714 - Memory resistor having multi-layer electrodes: Methods and means related to memory resistors are provided. A memristor includes two multi-layer electrodes and an active material layer. One multi-layer electrode forms an Ohmic contact region with the active material layer. The other multi-layer electrode forms a Schottky barrier layer with the active material layer. The active material... Agent:
20120120710 - Memory system with reversible resistivity-switching using pulses of alternatrie polarity: A memory system includes a plurality of non-volatile storage elements that each comprise a diode (or other steering device) in series with reversible resistance-switching material. One or more circuits in the memory system program the non-volatile storage elements by changing the reversible resistance-switching material of one or more non-volatile storage... Agent:
20120120711 - Memory system with reversible resistivity-switching using pulses of alternatrie polarity: A memory system includes a plurality of non-volatile storage elements that each comprise a diode (or other steering device) in series with reversible resistance-switching material. One or more circuits in the memory system program the non-volatile storage elements by changing the reversible resistance-switching material of one or more non-volatile storage... Agent:
20120120709 - Transistor driven 3d memory: A nonvolatile memory device with a first conductor extending in a first direction and a semiconductor element above the first conductor. The semiconductor element includes a source, a drain and a channel of a field effect transistor (JFET or MOSFET). The nonvolatile memory device also includes a second conductor above... Agent: Sandisk 3d LLC
20120120715 - Semiconductor device: Provided is a memory device in which memory capacity per unit area is increased without making the manufacturing process complicated. The memory device includes a plurality of memory cells, a plurality of word lines, and a plurality of bit lines. Each of the plurality of memory cells includes a switching... Agent: Semiconductor Energy Laboratory Co., Ltd.
20120120716 - Secure non-volatile memory: A secure memory includes a bistable memory cell having a programmed start-up state, and means for flipping the state of the cell in response to a flip signal. The memory may include a clock for generating the flip signal with a period, for example, smaller than the acquisition time of... Agent: Stmicroelectronics Sa
20120120717 - Sram cell: The present invention provides an SRAM cell which does not have the constraints on the size of transistors in order to realize stabilized write and read operations, which has a fewer number of control signal lines per port, and which can be easily multi-ported in the read operation as well... Agent: National Institute Of Advanced Industrial Science And Technology
20120120718 - Multi-bit magnetic memory with independently programmable free layer domains: An apparatus and associated method for a non-volatile memory cell, such as a multi-bit magnetic random access memory cell. In accordance with various embodiments, a magnetic tunnel junction (MTJ) has a ferromagnetic free layer with multiple magnetic domains that are each independently programmable to predetermined magnetizations. Those magnetizations can then... Agent: Seagate Technology LLC
20120120720 - Multilevel magnetic element: The present disclosure concerns a multilevel magnetic element comprising a first tunnel barrier layer between a soft ferromagnetic layer having a magnetization that can be freely aligned and a first hard ferromagnetic layer having a magnetization that is fixed at a first high temperature threshold and freely alignable at a... Agent: Crocus Technology Sa
20120120719 - Non-volatile magnetic tunnel junction transistor: An example embodiment is an apparatus for controlling a magnetic direction of a magnetic free layer. The apparatus includes a writer with a first magnetic write layer and a second magnetic write layer. Applying a write voltage across first and second magnetic write layers causes a magnetic anisotropy of one... Agent: International Business Machines Corporation
20120120721 - Unidirectional spin torque transfer magnetic memory cell structure: Spin torque transfer magnetic random access memory devices configured to be programmed unidirectionally and methods of programming such devices. The devices include memory cells having two pinned layers and a free layer therebetween. By utilizing two pinned layers, the spin torque effect on the free layer from each of the... Agent: Micron Technology, Inc.
20120120723 - Dynamic pulse operation for phase change memory: The control circuit performs a reset operation and a set operation that change the resistance states of phase change memory cells of the array. The control circuit changes at least one parameter, of at least one of the reset operation and the set operation for future operations. This change is... Agent: Macronix International Co., Ltd.
20120120724 - Phase change memory device: A phase change memory device includes a signal generator configured to generate first and second sensing and amplifying enable signals which are sequentially activated during an activation period of a word line selection signal and each of which has a certain activation period length, a resistance sensor configured to sense... Agent:
20120120722 - Pipeline architecture for scalable performance on memory: An apparatus for data storage is presented. In one embodiment, the apparatus includes a phase change memory device comprising phase change memory storage elements. The apparatus further includes control logic to control two or more set pipelines to serve memory requests in a staggered manner, such that set operations of... Agent:
20120120725 - Semiconductor memory device and method of operating the same: A method of operating a semiconductor memory device includes a memory array having memory cell strings including a first and a second memory cell groups having memory cells, a first and a second dummy elements, a drain select transistor and a source select transistor, wherein the first memory cell group... Agent: Hynix Semiconductor Inc.
20120120726 - Variable initial program voltage magnitude for non-volatile storage: Multiple programming processes are performed for a plurality of non-volatile storage elements. Each of the programming process operates to program at least a subset of said non-volatile storage elements to a set of target conditions using program pulses. In one embodiment, a first programming pass includes soft programming and additional... Agent:
20120120727 - Method of providing an operating voltage in a memory device and a memory controller for the memory device: A method of providing an operating voltage in a memory device includes applying a read voltage to a selected word line while applying a first pass voltage to at least one unselected word line among word lines adjacent to the selected word line; and while applying a second pass voltage... Agent:
20120120728 - Non-volatile memory device: A non-volatile memory device is provided, including a substrate formed of a single crystalline semiconductor, pillar-shaped semiconductor patterns extending perpendicular to the substrate, a plurality of gate electrodes and a plurality of interlayer dielectric layers alternately stacked perpendicular to the substrate, and a charge spread blocking layer formed between the... Agent: Samsung Electronics Co., Ltd
20120120729 - Word line kicking when sensing non-volatile storage: Methods and devices for sensing non-volatile storage are disclosed. Technology disclosed herein reduces the time for sensing operations of non-volatile storage such as read and program verify. In one embodiment, a kicking voltage is applied to a selected word line during a sensing operation. The kicking voltage may be applied... Agent:
20120120730 - Method and apparatus for adjusting maximum verify time in nonvolatile memory device: A nonvolatile memory device is programmed by decoding a received address, determining whether the received address is a first type of page address or a second type of page address, adjusting a maximum verify time of a program loop used to verify a program state of page data according to... Agent: Samsung Electronics Co., Ltd.
20120120732 - Nonvolatile memory device and read method thereof: A nonvolatile memory device has improved reliability by compensating a threshold voltage of a flash memory cell. A nonvolatile memory device includes a memory cell array and a voltage generator for supplying a select read voltage to a select word line and an unselect read voltage to unselected word lines... Agent:
20120120731 - Semiconductor memory device and related method of programming: A method of programming a nonvolatile memory device comprises applying a program voltage to a selected wordline to program selected memory cells, and performing a verify operation by applying a verify voltage to the selected wordline to determine the programming status of the selected memory cells. The verify operation applies... Agent: Samsung Electronics Co., Ltd.
20120120733 - Semiconductor device including fuse array and method of operation the same: Provided are a semiconductor device including a fuse and a method of operating the same. The semiconductor device includes a fuse array, a first register unit, and a second register unit. The fuse array includes a plurality of rows and columns. The first register unit receives at least one row... Agent: Samsung Electronics Co., Ltd.
20120120734 - Double line access to a fifo: An apparatus comprising a write data buffer circuit, a memory, and a read data buffer circuit. The write data circuit may be configured to present data in a second format in response to data received in a first format. The memory may be configured to (i) receive the data in... Agent:
20120120736 - Self pre-charging and equalizing bit line sense amplifier: A bit-line sense amplifier includes a latching unit and a control unit. The latching unit has a plurality of field effect transistors coupled between first and second bit lines. The control unit controls application of a bias voltage to a set of the field effect transistors such that respective pre-charge... Agent:
20120120735 - Semiconductor device having electrical fuse and control method thereof: To provide a plurality of fuse elements, each of which is either in a programmed state or a non-programmed state, a plurality of fuse determination circuits, each of which outputs a determination result signal that corresponds to a programmed state or a non-programmed state of the fuse element, and a... Agent: Elpida Memory, Inc.
20120120737 - Repair circuit and control method thereof: A semiconductor memory apparatus including a repair circuit may comprise: a fuse set block configured to store a repair address, compare the repair address with an input address, and generate a primary repair signal; and a redundancy control block configured to receive the primary repair signal, determine whether a repair... Agent: Hynix Semiconductor Inc.
20120120738 - Semiconductor device: The semiconductor device makes a comparison between a word-line timing signal for determining a word-line activation time and a reference signal, applies a back-gate bias for enlarging a read margin when the result of the comparison represents a low condition of the read margin, and applies a back-gate bias for... Agent: Renesas Electronics Corporation
20120120739 - Semiconductor memory device and method of controlling the same: An internal voltage generator when activated, generates an internal voltage to be supplied to an internal circuit. Operating the internal voltage generator consumes a predetermined amount of the power. In response to a control signal from the exterior, an entry circuit inactivates the internal voltage generator. When the internal voltage... Agent: Fujitsu Semiconductor Limited
20120120741 - Nonvolatile memory device, read method for nonvolatile memory device, and memory system incorporating nonvolatile memory device: A method of performing a read operation on nonvolatile memory device comprises receiving a read command, receiving addresses, detecting a transition of a read enable signal, generating a strobe signal based on the transition of the read enable signal, reading data corresponding to the received addresses, and outputting the read... Agent: Samsung Electronics Co., Ltd.
20120120740 - Nonvolatile memory devices, erasing methods thereof and memory systems including the same: Disclosed are erase methods for a memory device which includes a substrate and a plurality of cell strings provided on the substrate, each cell string including a plurality of cell transistors stacked in a direction perpendicular to the substrate. The erase method includes applying a ground voltage to a ground... Agent: Samsung Electronics, Co., Ltd.
20120120742 - Semiconductor device: An object is to provide a semiconductor device having a memory which can efficiently improve a yield by employing a structure which facilitates the use of a spare memory cell. The semiconductor device includes a memory cell array having a memory cell and a spare memory cell, a decoder connected... Agent: Semiconductor Energy Laboratory Co., Ltd.
20120120744 - Method for synchronizing signals and processing data: A method for synchronizing signals includes the steps of receiving a preamble of a data strobe signal in response to a write preamble command, and synchronizing the data strobe signal with a clock signal through the preamble of the data strobe signal.... Agent: Hynix Semiconductor Inc.
20120120745 - Semiconductor device and information processing system including the same: A semiconductor device includes: an input node supplied with an input signal; an output node provided correspondingly to the input node; first and second input circuits coupled in parallel to each other between the input and output nodes; and a control circuit configured to control the first and second input... Agent: Elpida Memory, Inc.
20120120743 - Semiconductor memory apparatus and semiconductor system including the same: A semiconductor memory apparatus includes a shared pad which is configured to output a read operation control signal in a read operation and receive a write operation control signal in a write operation.... Agent: Hynix Semiconductor Inc.
20120120747 - Semiconductor device: A first data amplifier connects to a first memory cell identified by an X-address signal and a selection signal obtained by predecoding a Y-address signal. A second data amplifier connects to a second memory cell identified by the X-address signal and a delayed selection signal obtained by delaying the selection... Agent: Elpida Memory, Inc.
20120120746 - Semiconductor memory apparatus: A semiconductor memory apparatus may comprise: an input buffer block configured to receive a write signal and a reference level signal, compare a the write signal with a the reference level signal to generate a first write control signal, and delay the first write control signal by a predetermined time... Agent: Hynix Semiconductor Inc.
20120120749 - Jtag controlled self-repair after packaging: An integrated circuit containing memory includes IEEE 1149.1 (JTAG) controlled self-repair system that permits permanent repair of the memory after the integrated circuit has been packaged. The JTAG controlled self-repair system allows a user to direct circuitry to blow fuses using an externally supplied voltage to electrically couple or isolate... Agent: Micron Technology, Inc.
20120120748 - Test apparatus and repair analysis method: A test apparatus that tests a memory under test, comprising an address fail memory that stores address fail data for each address; a block fail memory that stores block fail data for each block; a reading section that reads the address fail data from the address fail memory for each... Agent: Advantest Corporation
20120120750 - Semiconductor device having electrical fuse and control method thereof: To provide an electrical fuse that is connected to a detection node via a selective transistor, a precharge transistor that precharges the detection node in a state where the selective transistor is off; a bias transistor that passes a bias current to the detection node in a state where the... Agent: Elpida Memory, Inc.
20120120751 - Semiconductor device having equalizing circuit equalizing pair of bit lines: A semiconductor device includes: a sense amplifier including an equalizing circuit that equalizes a pair of bit lines; an equalizing control circuit that converts the amplitude of an equalizing signal into a VDD level, and a word driver that controls a sub word line based on a timing signal. The... Agent: Elpida Memory, Inc.
20120120752 - Dual-port semiconductor memory and first-in first-out (fifo) memory having electrically floating body transistor: Multi-port semiconductor memory cells including a common floating body region configured to be charged to a level indicative of a memory state of the memory cell. The multi-port semiconductor memory cells include a plurality of gates and conductive regions interfacing with said floating body region. Arrays of memory cells and... Agent:
20120120753 - Semiconductor device having point-shift type fifo circuit: For example, a semiconductor device includes latch circuits, whose input nodes are connected to an input selection circuit and whose output nodes are connected to an output selection circuit; and a control circuit, which controls the input selection circuit and the output selection circuit. The control circuit includes a shift... Agent: Elpida Memory, Inc.
20120120754 - Semiconductor device including latency counter: For example, a semiconductor device includes a first latency counter, which selects whether to give an odd-cycle latency to an internal command signal; and a second latency counter, which gives a latency to an internal command signal at intervals of two cycles. The latency counters are connected in series. Since... Agent: Elpida Memory, Inc.05/10/2012 > 38 patent applications in 30 patent subcategories. archived by USPTO category
20120113703 - System for dynamically managing power consumption in a search engine: The power consumption of a search engine such as a CAM device is dynamically adjusted to prevent performance degradation and/or damage resulting from overheating. For some embodiments, the CAM device is continuously sampled to generate sampling signals indicating the number of active states and number of compare operations performed during... Agent:
20120113704 - In-package microelectronic apparatus, and methods of using same: A mounting substrate for a processor includes a die side and a land side with a processor footprint configured on the die side. The processor footprint is coupled to at least one processor interconnect and a microelectronic die is embedded in the mounting substrate. The microelectronic die is coupled to... Agent:
20120113705 - Configurable inputs and outputs for memory stacking system and method: Embodiments of the present invention relate to configurable inputs and/or outputs for memory and memory stacking applications in processor-based systems. More specifically, embodiments of the present invention include processor-based systems with volatile-memory having memory devices that include a die having a circuit configured for enablement by a particular signal, an... Agent: Round Rock Research, LLC
20120113706 - Memristors based on mixed-metal-valence compounds: A memristor (100, 100′, 100″) based on mixed-metal-valence compounds comprises: a first electrode (115); a second electrode (120); a layer (105) of a mixed-metal-valence phase in physical contact with at least one layer (110, 110a, 110b) of a fully oxidized phase. The mixed-metal-valence phase is essentially a condensed phase of... Agent:
20120113707 - Semiconductor memory device and driving method of semiconductor memory device: A novel semiconductor memory device whose power consumption is low is provided. A source of a writing transistor WTr_n_m, a gate of a reading transistor RTr_n_m, and one electrode of a capacitor CS_n_m are connected to each other. A gate and a drain of the writing transistor WTr_n_m are connected... Agent: Semiconductor Energy Laboratory Co., Ltd.
20120113708 - Stable sram bitcell design utilizing independent gate finfet: Stable SRAM cells utilizing Independent Gate FinFET architectures provide improvements over conventional SRAM cells in device parameters such as Read Static Noise Margin (RSNM) and Write Noise Margin (WNM). Exemplary SRAM cells comprise a pair of storage nodes, a pair of bit lines, a pair of pull-up devices, a pair... Agent: Qualcomm Incorporated
20120113709 - Semiconductor integrated circuit device with reduced leakage current: The gate tunnel leakage current is increased in the up-to-date process, so that it is necessary to reduce the gate tunnel leakage current in the LSI which is driven by a battery for use in a cellular phone and which needs to be in a standby mode at a low... Agent: Renesas Electronics Corporation
20120113710 - Non-volatile memory array and evice using erase markers: A non-volatile memory device, non-volatile memory cell array and related method of operation are disclosed. The non-volatile memory cell array includes a defined data unit stored in a plurality of non-volatile memory cells capable of being electrically overwritten within the non-volatile memory cell array, and an erase marker corresponding to... Agent: Samsung Electronics Co., Ltd.
20120113711 - Using a bit specific reference level to read a memory: A voltage derived from accessing a selected bit using one read current may be utilized to read a selected bit of an untriggered phase change memory after the read current is changed. As a result, different reference voltages may be used to sense the state of more resistive versus a... Agent:
20120113712 - Method of operating semiconductor memory device with floating body transistor using silicon controlled rectifier principle: A method of maintaining the data state of a semiconductor dynamic random access memory cell is provided, wherein the memory cell comprises a substrate being made of a material having a first conductivity type selected from p-type conductivity type and n-type conductivity type; a first region having a second conductivity... Agent:
20120113714 - Method for programming a multi-state non-volatile memory (nvm): A method is provided for programming a multi-state flash memory having a plurality of memory cells. A first programming pulse is provided to the flash array; determining a threshold voltage distribution for the plurality of memory cells after providing the first programming pulse. The plurality of memory cells is categorized... Agent:
20120113715 - Non-volatile memory with improved sensing by reducing source line current: One or more sense amplifiers for sensing the conduction current of non-volatile memory is controlled by signals that are timed by a reference sense amplifier having similar characteristics and operating conditions. In one aspect, a sensing period is determined by when the reference sense amplifier sensing a reference current detects... Agent:
20120113717 - Semiconductor memory device with improved ecc efficiency: Memory cells store k bits of data (k is a natural number not less than 2) into a single cell. A number n of data storage circuits store externally supplied k bits of data to write data into the memory cells. A control circuit inputs the data on a first... Agent:
20120113716 - Structure and method for shuffling data within non-volatile memory devices: Techniques for the reading and writing of data in multi-state non-volatile memories are described. Data is written into the memory in a binary format, read into the data registers on the memory, and “folded” within the registers, and then written back into the memory in a multi-state format. In the... Agent:
20120113718 - 5t high density nvdram cell: A memory circuit includes a high voltage region providing storage of a nonvolatile bit, and a low voltage region providing at least partial storage of a volatile bit. The high and low voltage regions are isolated from one another and formed by a plurality of transistors in series between a... Agent: Cypress Semiconductor Corporation
20120113719 - Nonvolatile semiconductor storage device, nonvolatile semiconductor storage system and method of managing of defective column in nonvolatile semiconductor storage system: A nonvolatile semiconductor storage device is disclosed, which includes a memory cell array in which nonvolatile memory cells are arranged, a first data holding circuit which temporarily holds a collective processing unit of read or write data to be simultaneously read from or written to the memory cells, a circuit... Agent:
20120113720 - Semiconductor memory device and erase method thereof: A semiconductor memory device includes a plurality of memory blocks configured to include memory cells, a voltage supply circuit configured to supply an erase voltage for an erase operation of a memory block selected from the memory blocks and supply an erase verify voltage and an erase pass voltage for... Agent: Hynix Semiconductor Inc.
20120113721 - Flexible memory operations in nand flash devices: A flash memory device having at least two bank, where the each bank has an independently configurable page size and core controller. The core controller is local to each bank, and governs memory access operations for the bank that include read, program and erase operations. Each core controller controls timing... Agent: Mosaid Technologies Incorporated
20120113722 - Selecting programming voltages in response to at least a data latch in communication with a sense amplifier: Memory devices and methods of programming memory cells including selecting a voltage to apply to a control gate of the memory cell during programming of a data value of a sense amplifier to the memory cell in response to at least a data value contained in a data latch that... Agent: Micron Technology, Inc.
20120113723 - Mitigation of data corruption from back pattern and program disturb in a non-volatile memory device: In one of the disclosed embodiments, a write algorithm is used to remove errors due to back pattern effects, cell-to-cell capacitive coupling, and program disturb in memory cells. Original data to be programmed is adjusted prior to an initial programming operation of the memory cells. The original data is then... Agent: Micron Technology, Inc.
20120113713 - Methods of operating a memory device having a buried boosting plate: Memory devices are disclosed, such as those that include a semiconductor-on-insulator (SOI) NAND memory array having a boosting plate. The boosting plate may be disposed in an insulator layer of the SOI substrate such that the boosting plate exerts a capacitive coupling effect on a p-well of the memory array.... Agent: Micron Technology, Ind.
20120113725 - Nonvolatile memory device and method of programming the device: A nonvolatile memory device and a method of programming the device includes storing first data in first main and sub-registers and storing second data in second main and sub-registers, performing first program and verification operations on first memory cells based on the first data stored in the first main register,... Agent:
20120113724 - Semiconductor memory: According to one embodiment, a semiconductor memory includes a memory cell array including a plurality of memory cells, a sense amplifier circuit holding a verification result for the memory cells and including sense units, the sense units of each column block being connected in common to a first signal line,... Agent:
20120113726 - Flash memory and fabrication method and operation method for the same: The present invention discloses a flash memory and the fabrication method and the operation method for the same. The flash memory comprises two memory cells of vertical channels, wherein a lightly-doped N type (or P type) silicon is used as a substrate; a P+ region (or an N+ region) is... Agent: Peking University
20120113727 - Configuration finalization on first valid nand command: A startup method and circuit to allow high current consumption for startup processes of a low operating voltage memory device such as a NAND device until the receipt of a valid command to the memory device. Upon receipt of a valid command, startup functions are ceased at the high current... Agent: Micron Technology, Inc.
20120113730 - Ram memory element with one transistor: A memory element includes a MOS transistor having a drain, a source and a body region covered by an insulated gate, wherein the thickness of the body region is divided into two distinct regions separated by a portion of an insulating layer extending parallel to the plane of the gate.... Agent: Universiadad De Granada
20120113728 - Data input circuit: A data input circuit includes a clock sampling unit, a final clock generation unit, and a write latch signal generation unit. The sampling unit is configured to generate a shifting signal including a pulse generated after a write latency is elapsed, and generate a sampling clock by sampling an internal... Agent: Hynix Semiconductor Inc.
20120113729 - Memory interface circuit and semiconductor device: An expected value acquisition latch latches write data in synchronization with a clock signal. A WDLL outputs a write strobe signal WDQS. An RDLL outputs a delayed write strobe signal WDQS_d. A read data latch latches looped-back write data in synchronization with the delayed write strobe signal WDQS_d. A comparator... Agent: Renesas Electronics Corporation
20120113731 - Semiconductor signal processing device: A unit operator cell includes a plurality of SOI (Silicon on Insulator) transistors, write data is stored in a body region of at least two SOI transistors, and the storage SOI transistors are connected in series with each other to a read port or each of the storage SOI transistors... Agent: Renesas Electronics Corporation
20120113732 - Pseudo-open drain type output driver having de-emphasis function, semiconductor memory device, and control method thereof: A semiconductor memory device includes a memory cell array, an output driver having a pseudo-open drain (POD) structure and providing read data from the memory cell array in a de-emphasis mode, and control logic controlling the output driver in response to a read command to activate the de-emphasis mode. The... Agent: Samsung Electronics Co., Ltd.
20120113733 - Nonvolatile memory devices with on die termination circuits and control methods thereof: Non-volatile memory devices including on-die termination circuits connected to an input/output circuit and an on-die termination control logic detecting a preamble of a strobe signal based on a command and a control signal and activating the on-die termination within the preamble period.... Agent: Samsung Electronics Co., Ltd.
20120113734 - Semiconductor device: A semiconductor device includes a bit line; a data bus line corresponding to the bit line; a selection transistor that controls electrical connection between the bit line and the data bus line; a write amplifier that writes data to the bit line through the data bus; and a test circuit.... Agent: Elpida Memory, Inc.
20120113735 - Semiconductor device having current change memory cell: A semiconductor device comprises a first transistor connected between a bit line and a sense node, and a second transistor amplifying a signal of the sense node. A first potential applied to a gate of the first transistor, a second potential supplied to the sense node, and a third potential... Agent: Elpida Memory Inc.
20120113736 - Semiconductor device having hierachical bit line structure: A semiconductor device of the invention comprise a memory cell array configured with hierarchical local bit lines and global bit lines, in which there are provide local bit lines, global bit lines, switches controlling a connection between the global bit lines, sense amplifiers, and a control circuit controlling the switches.... Agent: Elpida Memory Inc.
20120113737 - Electronic device and memory device of current compensation: An electronic device includes a functional unit and a current compensation unit. The functional unit operates based on a power supplied by an external host through power supply lines and generates a control signal based on an amount of power consumption of the functional unit. The current compensation unit compensates... Agent: Samsung Electronics Co., Ltd
20120113738 - Memory device having multiple power modes: A memory device having a memory core is described. The memory device includes a clock receiver circuit, a first interface to receive a read command, a data interface, and a second interface to receive power mode information. The data interface is separate from the first interface. The second interface is... Agent:
20120113739 - Memory devices having redundant arrays for repair: Apparatus and methods are disclosed, such as those involving a memory device. One such memory device includes a memory array including a sub-array that includes a first number of columns of memory cells, and one or more global input/output (I/O) lines shared by the first number of columns for data... Agent: Micron Technology, Inc.
20120113740 - Row decoder circuit: A row decoder circuit includes a decoding unit and first and second wordline driving units. The decoding unit generates a first driving signal and a second driving signal based on a selection signal and wordline voltages. A voltage level of the first driving signal and a voltage level of the... Agent:05/03/2012 > 64 patent applications in 35 patent subcategories. archived by USPTO category
20120106224 - Nonvolatile memory apparatus, repair circuit for the same, and method for reading code addressable memory data: A nonvolatile memory apparatus includes: a memory cell array including a plurality of planes and configured to store a plurality of code addressable memory (CAM) data in independent planes. A redundancy cell array is configured to replace the memory cell array and a CAM data read unit is configured to... Agent: Hynix Semiconductor Inc.
20120106225 - Array-based integrated circuit with reduced proximity effects: An integrated circuit and method of generating a layout for an integrated circuit in which circuitry peripheral to an array of repetitive features, such as memory or logic cells, is realized according to devices constructed similarly as the cells themselves, in one or more structural levels. The distance over which... Agent: Texas Instruments Incorporated
20120106226 - Semiconductor memory device: A semiconductor memory device includes a bit line; two or more word lines; and a memory cell including two or more sub memory cells that each include a transistor and a capacitor. One of a source and a drain of the transistor is connected to the bit line, the other... Agent: Semiconductor Energy Laboratory Co., Ltd.
20120106227 - Integrated circuit: An integrated circuit includes a normal data storage unit configured to store normal data and output the stored normal data in response to a write command, a read command, and an address signal in a normal operation mode, a test data storage unit configured to store the address signal as... Agent:
20120106228 - Method and apparatus for optimizing driver load in a memory package: An apparatus is provided that includes a plurality of array dies and at least two die interconnects. The first die interconnect is in electrical communication with a data port of a first array die and a data port of a second array die and not in electrical communication with data... Agent: Netlist, Inc.
20120106229 - Semiconductor device: To include stacked plural core chips, each of which includes a first through silicon via for transferring write data and a second through silicon via for transferring read data, and an interface chip commonly connected to the core chips. The interface chip includes a data input/output terminal, an input buffer... Agent: Elpida Memory, Inc.
20120106230 - Semiconductor memory device: The memory cell array has memory cells each positioned at respective intersections between a plurality of first wirings and a plurality of second wirings. Each of the memory cells has a rectifier element and a variable resistance element connected in series. The resistance element may have at least a first... Agent: Kabushiki Kaisha Toshiba
20120106231 - Low-pin-count non-volatile memory interface: A low-pin-count non-volatile (NVM) memory to be provided in an integrated circuit. In one embodiment, the low-pin-count non-volatile (NVM) memory can use only one external control signal and one internal clock signal to generate start, stop, device ID, read/program/erase pattern, starting address, and actual read/program/erase cycles. When programming or erasing... Agent:
20120106232 - Memory cells, methods of programming memory cells, and methods of forming memory cells: Some embodiments include methods of programming a memory cell. A plurality of charge carriers may be moved within the memory cell, with an average charge across the moving charge carriers having an absolute value greater than 2. Some embodiments include methods of forming and programming an ionic-transport-based memory cell. A... Agent:
20120106233 - Reduced switching-energy magnetic elements: A system includes a continuous thin-film ferromagnetic layer, N magnetic tunnel junction (MTJ) devices, and N write structures. The continuous thin-film ferromagnetic layer includes N modified regions. Each of the N modified regions is configured to stabilize a magnetic domain wall located in the continuous thin-film ferromagnetic layer. Each of... Agent: Honeywell International Inc.
20120106234 - Semiconductor memory having both volatile and non-volatile functionality including resistance change material and method of operating: Semiconductor memory is provided wherein a memory cell includes a capacitorless transistor having a floating body configured to store data as charge therein when power is applied to the cell. The cell further includes a nonvolatile memory comprising a resistance change element configured to store data stored in the floating... Agent:
20120106235 - Implementing physically unclonable function (puf) utilizing edram memory cell capacitance variation: A method and embedded dynamic random access memory (EDRAM) circuit for implementing a physically unclonable function (PUF), and a design structure on which the subject circuit resides are provided. An embedded dynamic random access memory (EDRAM) circuit includes a first EDRAM memory cell including a memory cell true storage capacitor... Agent: International Business Machines Corporation
20120106237 - Boost circuit for generating an adjustable boost voltage: A technique for generating an adjustable boost voltage for a device includes charging, using first and second switches, a capacitor to a first voltage during a charging phase. The technique also includes stacking, using a third switch, a second voltage onto the first voltage across the capacitor in a boost... Agent: International Business Machines Corporation
20120106238 - Static random-access cell, active matrix device and array element circuit: A static random-access memory (SRAM) cell which includes: a sampling switch and a feedback switch; and a first inverter and a second inverter connected in series whereby an output of the first inverter is connected to an input of the second inverter. An input of the first inverter is connected... Agent: Sharp Kabushiki Kaisha
20120106236 - Tfet based 6t sram cell: Memory devices and methods of operation are provided. A memory device includes first and second cross-coupled inverters and first and second access transistors coupled to an input node of the second inverter. The memory device also includes a control circuit for providing a first reference voltage at a first ground... Agent: The Penn State Research Foundation
20120106240 - Compound cell spin-torque magnetic random access memory: A compound magnetic data storage cell, applicable to spin-torque random access memory (ST-RAM), is disclosed. A magnetic data storage cell includes a magnetic storage element and two terminals communicatively connected to the magnetic storage element. The magnetic storage element is configured to yield any of at least three distinct magnetoresistance... Agent: Seagate Technology LLC
20120106239 - Magnetic memory element with multi-domain storage layer: An apparatus and method for enhancing data writing and retention to a magnetic memory element, such as in a non-volatile data storage array. In accordance with various embodiments, a programmable memory element has a reference layer and a storage layer. The reference layer is provided with a fixed magnetic orientation.... Agent: Seagate Technology LLC
20120106241 - Spin-transfer torque memory self-reference read method: A spin-transfer torque memory apparatus and self-reference read schemes are described. One method of self-reference reading a spin-transfer torque memory unit includes applying a first read current through a magnetic tunnel junction data cell and forming a first bit line read voltage, the magnetic tunnel junction data cell having a... Agent: Seagate Technology LLC
20120106243 - Current control apparatus and phase change memory having the same: A current control apparatus of a phase change memory includes a temperature sensing block having an output voltage level which varies depending on temperature of an internal circuit and a write driver configured to control an amount of program current provided to a memory cell in response to the output... Agent: Hynix Semiconductor Inc.
20120106242 - Memory apparatus having storage medium dependent on temperature and method for driving the same: A memory apparatus includes a temperature detection block configured to detect temperature of an internal circuit and output a temperature detection signal, a current control block configured to receive the temperature detection signal and generate a pulse control signal, and a write driver configured to provide a program pulse having... Agent: Hynix Semiconductor Inc.
20120106244 - Phase-change memory device: A phase-change memory device and its firing method are provided. The firing method of the phase-change memory device includes applying a writing current to phase-change memory cells, identifying a state of the phase-change memory cells after applying the writing current, and applying a firing current, in which an additional current... Agent: Samsung Electronics Co., Ltd.
20120106245 - Thermally assisted magnetic random access memory element with improved endurance: The present disclosure concerns a magnetic memory element suitable for a thermally-assisted switching write operation, comprising a current line in electrical communication with one end of a magnetic tunnel junction, the magnetic tunnel junction comprising: a first ferromagnetic layer having a fixed magnetization; a second ferromagnetic layer having a magnetization... Agent: Crocus Technology Sa
20120106251 - Flash memory device configured to switch wordline and initialization voltages: Provided is a flash memory device including a wordline voltage generating unit, a switch unit, a row decoder and a control circuit. The wordline voltage generating unit generates at least one wordline voltage for read operations of a multi-level cell in the flash memory device. The switch unit receives the... Agent: Samsung Electronics Co., Ltd.
20120106247 - Flash memory device including flag cells and method of programming the same: Provided is a flash memory device and a method of programming the same. The flash memory device includes a memory cell array, a first judgment circuit and a second judgment circuit. The memory cell array includes multiple main cells and multiple flag cells. The first judgment circuit judges program pass... Agent: Samsung Electronics Co., Ltd.
20120106250 - Method and system for program pulse generation during programming of nonvolatile electronic devices: Aspects for program pulse generation during programming of nonvolatile electronic devices include providing a configurable voltage sequence generator to manage verify-pulse and pulse-verify switching as needed during modification operations of a programming algorithm for nonvolatile electronic devices, wherein more efficient modification operations result. In this manner, highly flexible bit sequence... Agent: Atmel Corporation
20120106248 - Non-volatile multilevel memory cells: The present disclosure includes methods, devices, modules, and systems for operating non-volatile multilevel memory cells. One method embodiment includes assigning, to a first cell coupled to a row select line, a first number of program states to which the first cell can be programmed. The method includes assigning, to a... Agent: Micron Technology, Inc.
20120106246 - Non-volatile semiconductor memory device, method of writing the same, and semiconductor device: A control circuit is configured to be able to perform a rough write process, a foggy write process, and a fine write process. The rough write process moves, for a memory cell to be provided with a plurality of second threshold voltage distributions, a first threshold voltage distribution in the... Agent: Kabushiki Kaisha Toshiba
20120106249 - Programming error correction code into a solid state memory device with varying bits per cell: Memory devices that, in a particular embodiment, receive and transmit analog data signals representative of bit patterns of two or more bits such as to facilitate increases in data transfer rates relative to devices communicating data signals indicative of individual bits. Programming error correction code (ECC) and metadata into such... Agent: Micron Technology, Inc.
20120106252 - Nonvolatile semiconductor memory device and method of manufacturing same: A nonvolatile semiconductor memory device includes a first region, a second region, and a plurality of word lines. The first region includes a plurality of electrically-rewritable memory transistors. The second region is located around the first region. The plurality of word lines are connected to the gates of the plurality... Agent: Kabushiki Kaisha Toshiba
20120106253 - Three-dimensional memory device incorporating segmented array line memory array: A three-dimensional (3D) high density memory array includes multiple layers of segmented bit lines (i.e., sense lines) with segment switch devices within the memory array that connect the segments to global bit lines. The segment switch devices reside on one or more layers of the integrated circuit, preferably residing on... Agent:
20120106256 - Electronic circuit with a floating gate transistor and a method for deactivating a floating gate transistor temporarily: An electronic circuit includes a floating gate transistor with a floating gate capacitor. The floating gate transistor can be programmed to be in an ON or an OFF state by charging the floating gate capacitor. The circuit further includes a deactivation capacitor adapted to store a charge sufficient for deactivating... Agent: Texas Instruments Deutschland Gmbh
20120106254 - Memory system: According to one embodiment, a memory system includes a NAND flash memory, a first unit, and an second unit. Memory cells capable of holding data and management data as a first control signal. Memory cells are arranged in a matrix in the NAND flash memory. The first unit holds a... Agent:
20120106255 - Voltage generation circuit which is capable of reducing circuit area: According to one embodiment, a voltage generation circuit includes a first boost circuit, a first output circuit, a rectifying circuit, a second output circuit, and a detection circuit. The first boost circuit outputs a first voltage in first and second operation modes. The first output circuit is connected to the... Agent:
20120106257 - Non-volatile semiconductor storage device: For data erase from an electrically erasable and programmable non-volatile memory cell, the following operations are performed: an erase operation to apply an erase pulse voltage to a memory cell for data erase, an erase verify operation to verify whether data erase is completed, and a step-up operation to increase... Agent: Kabushiki Kaisha Toshiba
20120106258 - Readout circuit and semiconductor storage device: A readout circuit has a sense amplifier to compare a cell current which changes according to whether a memory cell is on or off with a reference current, to output a comparison signal of a first logic upon detecting that the cell current is smaller than the reference current, and... Agent: Kabushiki Kaisha Toshiba
20120106259 - Adaptive control of programming currents for memory cells: A method includes performing a first programming operation on a plurality of memory cells in a same programming cycle; and performing a verification operation on the plurality of memory cells to find failed memory cells in the plurality of memory cells, wherein the failed memory cells are not successfully programmed... Agent: Taiwan Semiconductor Manufacturing Company, Ltd.
20120106260 - Semiconductor memory device and method of operating the same: A method of operating a semiconductor memory device includes performing a first program operation in order to raise threshold voltages of memory cells, performing a program verification operation for detecting fast program memory cells, each having a threshold voltage risen higher than a first sub-verification voltage from a second sub-verification... Agent:
20120106261 - Systems and methods for erasing a memory: Methods of erasing a memory, methods of operating a memory, memory devices, and systems. In one such method, an erase block is erased to an intermediate erase voltage before it is erased to a final erase voltage, such as to tighten an erase distribution. Faster erasing cells have their erasing... Agent: Micron Technology, Inc.
20120106262 - Programming method for nonvolatile memory apparatus: Provided is a method for programming a nonvolatile memory apparatus which includes a bit line selector coupled to first and second bit lines and a page buffer including a main data transmission switch coupled to the bit line selector, a first latch coupled to the main data transmission switch, a... Agent: Hynix Semiconductor Inc.
20120106263 - Input/output circuit and method of semiconductor apparatus and system with the same: A system includes a controller which is capable of operating at one of a first speed and a second speed slower than the first speed; a semiconductor memory apparatus operating at the first speed; and an input/output device which is connected between the semiconductor memory apparatus and the controller, and... Agent: Hynix Semiconductor Inc.
20120106264 - Write-leveling implementation in programmable logic devices: Circuits, methods, and apparatus for memory interfaces that compensate for skew between a clock signal and DQ/DQS signals that may be caused by a fly-by routing topology. The skew is compensated by clocking the DQ/DQS signals with a phase delayed clock signal, where the phase delay has been calibrated. In... Agent: Altera Corporation
20120106266 - Apparatus for measuring data setup/hold time: An apparatus for measuring data setup/hold time is capable of effectively measuring a setup/hold time of data, and includes a data generating unit for delaying an external clock signal according to counting signals and generating an internal clock signal and data signals from the delayed external clock signal in response... Agent: Hynix Semiconductor, Inc.
20120106265 - Semiconductor memory device and semiconductor system including the same: A semiconductor memory device includes a memory block configured to store a data inputted/outputted through a data transfer line, a data output block configured to output the data loaded on the data transfer line in response to a source clock, wherein the data output block is controlled to be coupled... Agent:
20120106267 - Circuit for generating reference voltage of semiconductor memory apparatus: A reference voltage generating circuit in a semiconductor memory apparatus comprises a driving control signal generating unit configured to generate a driving control signal according to a temperature variation, wherein the driving control signal generating unit is enabled in response to a power-up signal, a driving unit configured to control... Agent: Hynix Semiconductor Inc.
20120106268 - Synchronous type semiconductor storage device and dram: A synchronous type semiconductor storage device includes an array unit which includes a cell array and sense amplifiers. The synchronous type semiconductor storage device includes a read/write pulse generator which generates a read pulse signal and a write pulse signal according to a clock signal, the clock signal defining one... Agent: Kabushiki Kaisha Toshiba
20120106269 - Memory circuit and method of operating the same: The present application discloses a memory circuit having a first data line configured to carry a first data line signal and a second data line configured to carry a second data line signal. Further, a first driver is coupled to the first data line and the second data line and... Agent: Taiwan Semiconductor Manufacturing Company, Ltd.
20120106270 - Semiconductor memory device and method of operating the same: A semiconductor memory device includes first and second memory groups that each comprise memory cells and redundancy memory cells; first main page buffers assigned to the first memory group and second main page buffers assigned to the second memory group; first main page buffers and a first redundancy page buffer... Agent:
20120106271 - Semiconductor memory apparatus: Various embodiments of a semiconductor memory apparatus are disclosed. In one exemplary embodiment, the semiconductor memory apparatus may include: a redundancy signal generation unit configured to compare mat information set by fuse cutting with address information inputted from outside and generate a plurality of redundancy signals; a mat designation signal... Agent: Hynix Semiconductor Inc.
20120106272 - Semiconductor memory device and semiconductor system including the same: A semiconductor memory device includes a pattern data generator configured to generate certain pattern data in a training operation mode, and an output driver configured to drive the pattern data to output training data with a slew rate corresponding to an external command in the training operation mode.... Agent:
20120106276 - Data strobe signal generation circuit: A data strobe signal generation circuit includes: an enable signal generation unit configured to decode a test signal and generate an enable signal; an internal clock generation unit configured to generate a rising clock signal and a falling clock signal in response to the test signal; and a data strobe... Agent: Hynix Semiconductor Inc.
20120106275 - Ringback circuit for semiconductor memory device: A circuit for a semiconductor memory device includes: a filtering control signal generation unit configured to synchronize a seed signal activated in a pre-amble period of a data strobe signal with the data strobe signal and sequentially generate a plurality of filtering control signals in response to the seed signal;... Agent:
20120106273 - Semiconductor memory apparatus: Various embodiments of a semiconductor memory apparatus are disclosed. In one exemplary embodiment, the semiconductor memory apparatus may include: a column control signal generator configured to generate a column control signal for a pair of bit lines corresponding to a data mask during a data mask operation; and a bit... Agent: Hynix Semiconductor Inc.
20120106274 - Semiconductor memory apparatus: A semiconductor memory apparatus includes a data input enable signal generation block configured to sequentially delay a data strobe signal to generate a first delayed data strobe signal, a second delayed data strobe signal, a third delayed data strobe signal and a fourth delayed data strobe signal, and generate a... Agent: Hynix Semiconductor Inc.
20120106277 - Refresh operation control circuit, semiconductor memory device including the same, and refresh operation control method: A semiconductor memory device includes a bank including a first cell region and a second cell region, an active signal generation unit configured to generate a first row active signal and a second row active signal having different activation periods from each other in response to a refresh command, and... Agent:
20120106278 - Semiconductor memory device and method for operating the same: A semiconductor memory device includes a plurality of banks, a clock input unit configured to receive an external data clock, an internal data clock generation unit configured to receive the external data clock from the clock input unit and generate an internal data clock by delaying the external data clock... Agent:
20120106279 - Semiconductor memory apparatus, memory system, and programming method thereof: Various embodiments of a semiconductor memory apparatus are disclosed. In one exemplary embodiment, the semiconductor memory apparatus includes a core block configured to receive and store external input data, a control unit configured to activate a control signal in response to a test mode signal and a command, when the... Agent: Hynix Semiconductor Inc.
20120106280 - Self-adaptive sensing design: A clock signal having a clock pulse width duration is received. A delay time is received. A first relationship and a second relationship between the clock pulse width duration and the delay time are determined. A new clock is generated that has a first new clock pulse width duration determined... Agent: Taiwan Semiconductor Manufacturing Company, Ltd.
20120106281 - Semiconductor memory devices and semiconductor memory systems: A semiconductor memory device includes at least one memory cell block and at least one connection unit. The at least one memory cell block has a first region including at least one first memory cell connected to a first bit line, and a second region including at least one second... Agent: Samsung Electronics Co., Ltd.
20120106282 - Pattern layout in semiconductor device: According to one embodiment, a semiconductor device having a pattern layout includes a first interconnect pattern and a contact pad. The first interconnect pattern includes lines and spaces which are alternately aligned in a first direction with a predetermined pitch. The contact pad is arranged between the lines in the... Agent:
20120106283 - Row address control circuit semiconductor memory device including the same and method of controlling row address: A row address control circuit of a semiconductor memory device including dynamic memory cells includes a test mode setting unit, an address counter and a row address generating unit. The test mode setting unit is configured to provide a test mode signal that indicates whether a test operation is performed... Agent: Samsung Electronics Co., Ltd.
20120106285 - Circuits and methods for reducing minimum supply for register file cells: A register file employing a shared supply structure to improve the minimum supply voltage.... Agent:
20120106284 - Memory power supply circuit: A memory power supply circuit includes a memory module, a micro control unit (MCU), a phase switch circuit, and a multi-phase pulse-width modulation (PWM) controller. The MCU is operable to determine required current to be supplied to the memory module and output corresponding phase switch signals to the phase switch... Agent: Hon Hai Precision Industry Co., Ltd.
20120106287 - Memory arrangement for accessing matrices: A memory arrangement is provided having a plurality of memory elements, the elements being associated with a memory space that can be addressed in a row and column fashion during a write or a read access. The memory arrangement further includes a first macro bank comprising a first plurality of... Agent: Telefonaktiebolaget L M Ericsson (publ)
20120106286 - Memory circuit having decoding circuits and method of operating the same: The present application discloses a memory circuit having a first decoder coupled to a first memory bank and configured to receive a plurality of address control signals and to generate a first plurality of cell selection signals responsive to the plurality of address control signals and a second decoder coupled... Agent: Taiwan Semiconductor Manufacturing Company, Ltd.Previous industry: Electric power conversion systems
Next industry: Agitating
RSS FEED for 20141204:
Integrate FreshPatents.com into your RSS reader/aggregator or website to track weekly updates.
For more info, read this article.
Thank you for viewing Static information storage and retrieval patents on the FreshPatents.com website. These are patent applications which have been filed in the United States. There are a variety ways to browse Static information storage and retrieval patent applications on our website including browsing by date, agent, inventor, and industry. If you are interested in receiving occasional emails regarding Static information storage and retrieval patents we recommend signing up for free keyword monitoring by email.
Results in 1.95941 seconds