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Static information storage and retrieval April category listing, related patent applications 04/12Below are recently published patent applications awaiting approval from the USPTO. Recent week's RSS XML file available below.
Listing for abstract view: USPTO application #, Title, Abstract excerpt,Patent Agent. Listing format for list view: USPTO National Class full category number, title of the patent application. 04/26/2012 > 35 patent applications in 22 patent subcategories. category listing, related patent applications
20120099358 - Reference cell architectures for small memory array block activation: Systems and methods for realizing reference currents to improve reliability of sensing operations of segmented semiconductor memory arrays have been achieved. Preferred embodiments of the invention comprise MRAM arrays but the invention could be applied to any other memories requiring access on small, segmented arrays. All embodiments of the invention... Agent: Maglc Technologies, Inc.
20120099359 - Nonvolatile memory architecture: Representative implementations of memory devices have transistors between memory cells of a memory device. Memory devices may be arranged in memory arrays. The use of transistors may include alternately providing electrical isolation or current paths between pairs or groups of memory cells in a memory array.... Agent: Infineon Technologies Ag
20120099360 - Semiconductor memory device and driving method thereof: In a memory cell, a transistor with extremely high off-resistance is used as a write transistor; a drain and a source of the write transistor are connected to a write bit line and an input of an inverter, respectively; and a drain and a source of a read transistor are... Agent: Semiconductor Energy Laboratory Co., Ltd.
20120099361 - Semiconductor capacitor, one time programmable memory cell and fabricating method and operating method thereof: A one time programmable memory cell having a gate, a gate dielectric layer, a source region, a drain region, a capacitor dielectric layer and a conductive plug is provided herein. The gate dielectric layer is disposed on a substrate. The gate is disposed on the gate dielectric layer. The source... Agent: Ememory Technology Inc.
20120099367 - Cross point variable resistance nonvolatile memory device: A cross point variable resistance nonvolatile memory device includes memory cells having the same orientation for stable characteristics of all layers. Each memory cell (51) is placed at a different one of cross points of bit lines (53) in an X direction and word lines (52) in a Y direction... Agent:
20120099362 - Memory array with metal-insulator transition switching devices: A memory array with Metal-Insulator Transition (MIT) switching devices includes a set of row lines intersecting a set of column lines and a memory element disposed at an intersection between one of the row lines and one of the column lines. The memory element includes a switching layer in series... Agent:
20120099366 - Multi-resistive integrated circuit memory: A capacitor for use in integrated circuits comprises a layer of conductive material. The layer of conductive material including at least a first portion and a second portion, wherein the first portion and the second portion are arranged in a predetermined pattern relative to one another to provide a maximum... Agent:
20120099363 - Resistance change type memory: According to one embodiment, a resistance change type memory includes a first bit line extending in a first direction, a first word line extending in a second direction, a first bipolar transistor which is a first drive type and has a first emitter, a first base, and a first collector,... Agent: Kabushiki Kaisha Toshiba
20120099364 - Resistive memory devices, initialization methods, and electronic devices incorporating same: A resistive memory device and method of initialization are provided. The resistive memory device includes a first group of resistive memory cells connected between bit lines and a first plate and a second group connected between bit lines and a second plate. First and second initialization voltages are respectively applied... Agent: Samsung Electronics Co., Ltd.
20120099365 - Three dimensional programmable resistance memory device with a read/write circuit stacked under a memory cell array: A programmable resistance memory device includes a semiconductor substrate, at least one cell array, in which memory cells are arranged formed above the semiconductor substrate. Each of the memory cells has a stack structure of a programmable resistance element and an access element, the programmable resistance element storing a high... Agent: Kabushhiki Kaisha Toshiba
20120099368 - Method for driving semiconductor device: It is an object to obtain a memory element (DRAM) storing multilevel data easily. The amount of charge accumulated in a capacitor of a memory element (DRAM) is controlled by changing the potential of a wiring (a bit line), which is used for writing data to the memory element (DRAM),... Agent: Semiconductor Energy Laboratory Co., Ltd.
20120099369 - Magnetoresistive element and magnetic memory: According to one embodiment, a magnetoresistive element includes a first magnetic layer with a variable magnetization and an easy-axis in a perpendicular direction to a film surface, a second magnetic layer with an invariable magnetization and an easy-axis in the perpendicular direction, and a first nonmagnetic layer between the first... Agent:
20120099371 - Method of operating a phase-change memory device: A method of operating a phase-change memory device including a phase-change layer and a unit applying a voltage to the phase-change layer is provided. The method includes applying a reset voltage to the phase-change layer, wherein the reset voltage includes at least two pulse voltages which are continuously applied.... Agent:
20120099370 - Phase change memory device: A memory device includes a substrate and a plurality of cell arrays stacked above the substrate. The cell arrays have bit lines coupled to first ends of memory cells and word lines coupled to the other ends. Each of the memory cells includes a variable resistance element to be set... Agent: Kabushiki Kaisha Toshiba
20120099373 - Method of programming nonvolatile memory device: A method of programming a nonvolatile memory device includes sequentially programming first to (n−1)th logical pages of all the physical pages of a first memory block of the memory blocks in response to a first program command, a step of loading data of the first to (n−1)th logical pages stored... Agent:
20120099372 - Sequence detection for flash memory with inter-cell interference: A memory integrated circuit (IC) includes a read module and a sequence detector module. The read module reads S memory cells (cells) located along one of a bit line and a word line and generates S read signals, where S is an integer greater than 1. The sequence detector module... Agent:
20120099374 - Nonvolatile semiconductor memory device: A nonvolatile semiconductor memory device includes a substrate including device regions extending in a first direction, a memory cell array region including a plurality of memory cells disposed on the device regions, bit lines extending in the first direction, a sense amplifier circuit connected to ends of the bit lines,... Agent: Kabushiki Kaisha Toshiba
20120099375 - Nonvolatile memory device and method of operating the same: A method of operating a nonvolatile memory device includes performing a first program loop, including a first program operation and a first program verification operation, for memory cells of a first page, counting a number of times that the first program loop is performed and storing the counted number when... Agent:
20120099376 - Three dimensional stacked nonvolatile semiconductor memory: A three dimensional stacked nonvolatile semiconductor memory according to an example of the present invention includes a memory cell array comprised of first and second blocks. The first block has a first cell unit which includes a memory cell to be programmed and a second cell unit which does not... Agent:
20120099377 - Three dimensional stacked nonvolatile semiconductor memory: In a three dimensional stacked nonvolatile semiconductor memory according to the present invention, a first block has a selected first cell unit including a memory cell to be read and a non-selected second cell unit not including a memory cell to be read. A read potential or a transfer potential... Agent:
20120099378 - Nonvolatile memory and method for verifying the same: A nonvolatile memory device includes a cell string including a plurality of memory cells connected in series, a bit line connected to the cell string, a voltage sensing unit configured to apply a verify precharge voltage to the bit line in response to a voltage of a sensing node before... Agent:
20120099379 - Semiconductor memory apparatus and method of operating the same: A semiconductor memory apparatus includes a memory block including memory strings having respective channel layers coupled between respective bit lines and a source line, an operation circuit group configured to supply hot holes to the channel layers and to perform an erase operation on memory cells of the memory strings,... Agent:
20120099380 - Pfet nonvolatile memory: A nonvolatile memory cell is constructed using a floating-gate pFET readout transistor having its source tied to a power source (Vdd) and its drain providing a current, which can be sensed to determine the state of the cell. The gate of the pFET readout transistor provides for charge storage, which... Agent: Synopsys, Inc.
20120099381 - Embedded non-volatile memory cell, operation method and memory array thereof: The present invention discloses an embedded non-volatile memory cell, an operation method and a memory array thereof. The method includes using a gate of a selection transistor as a floating gate of a memory, and using a source electrode and a drain electrode of the selection transistor as a source... Agent: Peking University
20120099383 - Data output buffer and memory device: A data output buffer includes a driving unit and a control unit. The driving unit selectively performs a termination operation that provides a termination impedance to a transmission line coupled to an external pin, and a driving operation that provides a drive impedance to the transmission line while outputting read... Agent: Samsung Electronics Co., Ltd.
20120099382 - Reading memory data: A circuit includes a reference data line configured to receive a reference voltage value, a memory cell, a data line coupled to the memory cell and configured to have a data logic value associated with data stored in the memory cell, a first circuit coupled to the reference data line... Agent: Taiwan Semiconductor Manufacturing Company, Ltd.
20120099384 - Semiconductor device: A semiconductor memory has main bit lines paralleled by fixed potential lines in an alternating arrangement. Each main bit line is switchably connected to two sub-bit lines. The memory cells connected to one of the two sub-bit lines are placed below the main bit line. The memory cells connected to... Agent: Lapis Semiconductor Co., Ltd.
20120099385 - Nonvolatile semiconductor storage device and data write method for the same: A nonvolatile semiconductor storage device includes an identification code generating circuit, a simultaneous write bit count calculation circuit, a write range calculation circuit, and a program pulse generating circuit. The identification code generating circuit generates an identification code to be assigned to every one of bits to be written, and... Agent: Fujitsu Semiconductor Limited
20120099387 - Nonvolatile memory device and method of reading the same using different precharge voltages: A nonvolatile memory device includes a substrate, multiple doping regions, multiple cell strings and multiple page buffers. The doping regions extend in a first direction along the substrate and are spaced apart from one another in a second direction. The cell strings are provided according to a specific pattern between... Agent: Samsung Electronics Co., Ltd.
20120099386 - Semiconductor memory device and method of operating the same: A semiconductor memory device includes memory cells for storing data, page buffers each configured to comprise a dynamic latch and a static latch on which data to be programmed in to the memory cells or data read from the memory cells are latched, and a control logic configured to store... Agent: Hynix Semiconductor Inc.
20120099388 - Internal voltage generator of semiconductor memory device: An internal voltage generator of a semiconductor memory device includes a proportional to absolute temperature (PTAT) current generator configured to generate a PTAT current having a varying current in proportion to a temperature change, a current control circuit configured to generate an internal current identical with the PTAT current and... Agent: Hynix Semiconductor Inc.
20120099389 - Memory circuits, systems, and modules for performing dram refresh operations and methods of operating the same: A memory module can include a plurality of dynamic memory devices that each can include a dynamic memory cell array with respective regions therein, where the plurality of dynamic memory devices can be configured to operate the respective regions responsive to a command. A DRAM management unit can be on... Agent: Samsung Electronics Co., Ltd.
20120099391 - Method of reading data in a non-volatile memory device: A method of reading data in a non-volatile memory device compensates for a change in a reading/verifying result in accordance with a change of temperature. The method includes sensing a temperature of a memory cell, setting a first voltage and a second voltage of a bit line sensing signal in... Agent: Hynix Semiconductor Inc.
20120099390 - Semiconductor memory device: A semiconductor memory device includes a first page buffer group including a plurality of page buffers coupled to memory cells of a first memory array through bit lines, a second page buffer group, a coupling circuit configured to couple an output terminal and an inverse output terminal of a selected... Agent:
20120099392 - Storage device including reset circuit and method of resetting thereof: A data storage device including a reset circuit and a method of resetting thereof includes a memory device to receive a driving voltage through a power terminal thereof, a voltage regulator to adjust an external voltage to provide the adjusted voltage to the power terminal of the memory device, and... Agent: Samsung Electronics Co., Ltd04/19/2012 > 32 patent applications in 24 patent subcategories. category listing, related patent applications
20120092916 - Built-in self test for one-time-programmable memory: An apparatus and method of testing one-time-programmable memory provides one-time-programmable memory having one or more memory locations for storing data and corresponding programming circuitry for each memory location. In addition, each programming circuitry has a circuit element configured to permanently change state to store the data in the memory. The... Agent: Analog Devices, Inc.
20120092917 - Rom memory device: A memory device includes a plurality of read only memory cells, a precharge circuit, and a sense amplifier. A read only memory (ROM) cell of the plurality of ROM cells is coupled to a word line and a bit line. The ROM cell comprises a transistor having a first current... Agent:
20120092918 - Verification system: A verification system of the present invention is provided to perform unidirectional or bidirectional verification between a master apparatus and a slave apparatus comprising the master apparatus having a master memory capable of storing verification key code in a non-volatile manner and the slave apparatus having a slave memory capable... Agent: Rohm Co., Ltd.
20120092919 - Resistive memory element and use thereof: A resistive memory element that includes an element body and at least a pair of electrodes opposed to each other with at least a portion of the element body interposed therebetween. The element body is made of an oxide semiconductor as a polycrystalline body, which has a composition represented by... Agent: Murata Manufacturing Co., Ltd.
20120092920 - Resistive memory element and use thereof: A resistive memory element that includes an element body and at least a pair of electrodes opposed to each other with at least a portion of the element body interposed therebetween. The element body is made of an oxide semiconductor which has a composition represented by the general formula: (Ba1-xSrx)Ti1-yMyO3... Agent: Murata Manufacturing Co., Ltd.
20120092921 - Semiconductor device: A technique for increasing rewriting current without increasing a power supply voltage and also reducing location dependency inside a memory array of a resistive state after the rewriting is provided in a resistance change memory in which the resistance value of a memory cell changes between logical values “1” and... Agent: Hitachi, Ltd
20120092922 - Semiconductor integrated circuit: Flip-flop memory cells are connected to a pair of bit lines and respectively to word lines. A word line driver outputs a word line selection pulse to one of the word lines in a word line selection period. A write circuit gives a potential difference corresponding to input data to... Agent: Panasonic Corporation
20120092923 - Read distribution management for phase change memory: Subject matter disclosed herein relates to a memory device, and more particularly to write performance of a phase change memory.... Agent: Numonyx B.v.
20120092924 - Method of providing an erase activation energy of a memory device: A write-once read-many times memory device is made up of first and second electrodes, a passive layer between the first and second electrodes, and an active layer between the first and second electrode. The memory device is programmed by providing a charged species from the passive layer into the active... Agent:
20120092925 - Vertical capacitor-less dram cell, dram array and operation of the same: A vertical capacitor-less DRAM cell is described, including: a source layer having a first conductivity type, a storage layer disposed on the source layer and having a second conductivity type, an active layer disposed on the storage layer and having the first conductivity type, a drain layer disposed on the... Agent: Powerchip Technology Corporation
20120092926 - Three dimensional non-volatile memory device and method of manufacturing the same: A three dimensional non-volatile memory structure according to an aspect of this disclosure includes a plurality of interlayer dielectric layers and a plurality of control gates alternately stacked over a substrate, a channel formed to penetrate the plurality of interlayer dielectric layers and the plurality of control gates, a tunnel... Agent:
20120092927 - Memory system: A memory system includes a NAND flash memory having a page buffer capable of holding a page of data and a cell array having a plurality of pages. The system also includes a plurality of memory portions electrically connected to the NAND flash memory via a data bus, and a... Agent: Kabushiki Kaisha Toshiba
20120092928 - Semiconductor memory device: A semiconductor memory device includes: a memory-cell array provided between a first region and a second region, and including a plurality of memory cells; a first row decoder and a second row decoder; a first power line provided in the first region; a second power line provided in the first... Agent: Kabushiki Kaisha Toshiba
20120092929 - Semiconductor memory device capable of increasing writing speed: A memory cell array has a structure in which a plurality of memory cells connected with word lines and bit lines and connected in series are arranged in a matrix form. A selection transistor selects the word lines. A control circuit controls potentials of the word lines and the bit... Agent:
20120092930 - Semiconductor storage device and method of reading data therefrom: A semiconductor memory device includes a first memory cell array having a first plane which is composed of a plurality of blocks each having a plurality of memory cells, a sense circuit which reads data the memory cells, a sequencer which receives control signals from outside, a first address register,... Agent:
20120092931 - Nonvolatile semiconductor memory device: According to one embodiment, a nonvolatile semiconductor memory device includes a memory cell array, threshold voltages of memory cells being set lowest in an erase state and sequentially set higher according to data in a program state, a plurality of bit lines connected to the memory cells, a word line... Agent:
20120092932 - Programming methods and memories: Programming a memory in two parts to reduce cell disturb is disclosed. In at least one embodiment, data is programmed in two or more sequences of programming pulses with data requiring higher programming voltages programmed first. During each programming sequence, the data which is not being currently selected for programming... Agent: Micron Technology, Inc.
20120092933 - Memory erase methods and devices: Memory devices and erase methods for memories are disclosed, such as those adapted to discharge an erase voltage from a memory block while protecting low voltage string select gate transistors by maintaining the string select gate transistors in a turned on state during discharge.... Agent: Micron Technology, Inc.
20120092934 - Multiplexing circuit: A multiplexing circuit includes a plurality of first circuits and a second circuit coupled to outputs of the plurality of first circuits. A first circuit of the plurality of first circuits is configured to receive a first data line as a first input and a clock signal as a second... Agent: Taiwan Semiconductor Manufacturing Company, Ltd.
20120092936 - Semiconductor integrated circuit device for controlling a sense amplifier: A semiconductor IC device includes a command decoder that provides internal read and internal write command signals in response to external command signals, and a delay control unit that is connected with the command decoder and provides an internal read command delay signal by controlling an activation timing of the... Agent: Hynix Semiconductor Inc.
20120092937 - Method and system for a serial peripheral interface: A method for dual I/O data read in an integrated circuit which includes a serial peripheral interface memory device. In an embodiment, the memory device includes a clock signal, a plurality of pins, and a configuration register. In an embodiment, the configuration register includes a wait cycle count. The method... Agent: Macronix International Co., Ltd.
20120092938 - Semiconductor memory: Semiconductor memory including a reference amplifier and a high-speed start-up circuit having four FETs. The reference amplifier supplies the reference voltage to a sense amplifier via a reference voltage supply line. The high-speed startup circuit has four FETs. The first FET is turned on to apply a first voltage onto... Agent: Oki Semiconductor Co., Ltd.
20120092939 - Single-ended sensing scheme for memory: A memory having a single-ended sensing scheme includes a bit line, a memory cell coupled to the bit line, and a precharge circuit. The precharge circuit is configured to precharge the bit line to a precharge voltage between a power supply voltage and a ground.... Agent: Taiwan Semiconductor Manufacturing Company, Ltd.
20120092941 - Memory cell: Methods, and circuits, are disclosed for operating a programmable memory device. One method embodiment includes storing a value as a state in a first memory cell and as a complementary state in a second memory cell. Such a method further includes determining the state of the first memory cell using... Agent: Micron Technology, Inc.
20120092940 - Memory device and read operation method thereof: A read operation for a memory device. In response to an input address indicating to read data from a different page, a selected word line, first and second global bit lines and a selected first bit line group are precharged. A first cell current flowing through the selected word line,... Agent: Macronix International Co., Ltd.
20120092942 - Techniques for reading a memory cell with electrically floating body transistor: A semiconductor device along with circuits including the same and methods of operating the same are described. The device comprises a memory cell consisting essentially of one transistor. The transistor comprises a gate, an electrically floating body region, and a source region and a drain region adjacent the body region.... Agent: Micron Technology, Inc.
20120092935 - Semiconductor memory device: A semiconductor memory device includes a first memory device formed on a semiconductor substrate, including a first storage unit, a source, and a drain, a second memory device, including a second storage unit, and a bit line, wherein the second memory device is connected in series between the bit line... Agent: Hynix Semiconductor Inc.
20120092943 - Semiconductor device and test method thereof: plurality of core chips to which chip identification information different from each other is allocated and an interface chip are layered, the plurality of core chips are commonly connected to the interface chip through a first current path including at least a through silicon via, the interface chip serially supplies... Agent: Elpida Memory, Inc.
20120092945 - Command latency systems and methods: Examples of command latency systems and methods are described. In some examples, phase information associated with a received command signal is stored, a received command signal is propagated through a reduced clock flip-flop pipeline and the delayed command signal is combined with the stored phase information. The reduced clock flip-flop... Agent: Micron Technology, Inc.
20120092944 - Memory device having a clock skew generator: A memory device is provided with memory components and a clock skew generator, supporting at least two read and write operations that can occur coincidentally in read-read, read-write and write-write modes of operation of the memory device. The clock skew generator produces at least two stable and balanced clock channels... Agent: Taiwan Semiconductor Manufacturing Co., Ltd.
20120092946 - Memory devices and memory systems including discharge lines and methods of forming: A non-volatile memory device can include a word line that is operatively coupled to a non-volatile memory cell. A local bit line can be operatively coupled to the non-volatile memory cell. A discharge line that is associated with the local bit line can be configured to discharge the local bit... Agent: Samsung Electronics Co., Ltd.
20120092947 - Fuse circuit and memory device including the same: A fuse circuit includes a plurality of fuse cells, an amplification unit, and a plurality of registers. The amplification unit is configured to sequentially amplify data stored in the fuse cells. The registers are configured to sequentially store data amplified by the amplification unit.... Agent:04/12/2012 > 34 patent applications in 20 patent subcategories. category listing, related patent applications
20120087169 - Circuit for concurrent read operation and method therefor: A non-volatile memory device includes a plurality of memory units provided in an array, each memory unit having a plurality of resistive memory cells and a local word line. Each resistive memory units has a first end and a second end, the second ends of the resistive memory cells of... Agent: Crossbar, Inc.
20120087168 - Memory device including variable resistance elements: A memory device including variable resistance elements comprises a plurality of memory cells configured to store data; a first signal transmission/reception unit and a second signal transmission/reception unit configured to transmit a signal to the memory cells or receive a signal from the memory cells; a first transmission line arranged... Agent:
20120087170 - Single polysilicon non-volatile memory: A one-time-programmable memory device comprises a one-time-programmable memory cell array, a voltage pumping circuit, and a programming verification circuit. The one-time-programmable memory cell array comprises a plurality of memory cells. Each memory cell is arranged at an intersection of a bit line and a word line. The voltage pumping circuit... Agent:
20120087175 - Asymmetric write current compensation: An apparatus and method for compensating for asymmetric write current in a non-volatile unit cell. The unit cell comprises a switching device and an asymmetric resistive sense element (RSE), such as an asymmetric resistive random access memory (RRAM) element or an asymmetric spin-torque transfer random access memory (STRAM) element. The... Agent: Seagate Technology LLC
20120087173 - Memory element, stacking, memory matrix and method for operation: Disclosed is a memory element, a stack, and a memory matrix in which the memory element can be used. Also disclosed is a method for operating the memory matrix, and to a method for determining the true value of a logic operation in an array comprising memory elements. The memory... Agent:
20120087172 - Semiconductor memory and system: A semiconductor memory includes a real memory cell including a selection transistor and a resistance variable element which are connected in series between a first voltage line and a second voltage line through a connection node, a real amplification transistor having a gate connected to the connection node, a source... Agent: Fujitsu Limited
20120087171 - Semiconductor memory device including variable resistance elements and manufacturing method thereof: A semiconductor memory device with a variable resistance element includes a plurality of active areas isolated from one another by an isolation layer formed in a substrate, a plurality of word lines crossing over the plurality of active areas, an auxiliary source line disposed between two selected word lines and... Agent:
20120087174 - Two terminal re writeable non volatile ion transport memory device: A memory using mixed valence conductive oxides is disclosed. The memory includes a mixed valence conductive oxide that is less conductive in its oxygen deficient state and a mixed electronic ionic conductor that is an electrolyte to oxygen and promotes an electric field effective to cause oxygen ionic motion.... Agent: Unity Semiconductor Corporation
20120087176 - Data security for dynamic random access memory using body bias to clear data at power-up: A circuit and method erase at power-up all data stored in a DRAM chip for increased data security. All the DRAM memory cells are erased by turning on the transistors for the DRAM storage cells simultaneously by increasing the body voltage of cells. In the example circuit, the body voltage... Agent: International Business Machines Corporation
20120087178 - Semiconductor memory device: Adverse effects of a parasitic resistance and a parasitic capacitance of a driver circuit to a memory cell causes problems of thermal disturbance to a not-selected cell, unevenness of application voltage, degradation of a memory element in reading. A capacitor (C) is provided above or beneath a memory cell (MC)... Agent: Hitachi, Ltd.
20120087177 - Semiconductor memory device for data sensing: A semiconductor memory device includes a memory cell and a first reference memory cell. The memory cell includes a first switching element and a first capacitor for storing data. The first switching element is controlled by a first wordline, and has a first terminal connected to a first terminal of... Agent:
20120087179 - Magneto-resistance element and semiconductor memory device including the same: A magneto-resistance element is provided. The magneto-resistance element includes an underlying layer including a main metal selected from electrically conductive metals and an auxiliary metal selected from transition metals, a first magnetic layer stacked on the underlying layer, an insulation layer stacked on the first magnetic layer, and a second... Agent:
20120087180 - Semiconductor integrated circuit for low and high voltage operations: A semiconductor integrated circuit comprising a first circuit area for a low voltage operation and a second circuit area for a high voltage operation. The circuit areas comprise two vertically stacked backend patterned metal layers that are separated by an inter-metallic dielectric (IMD). The two metal layers and the IMD... Agent:
20120087181 - Cross-point self-aligned reduced cell size phase change memory: A programmable memory array is disclosed in which the phase change memory cells are self-aligned at the access devices and at the cross-points of the bit lines and the word lines. A method for making the array employs one line mask to define the bit lines and another line mask... Agent: Macronix International Co., Ltd.
20120087183 - Methods of operating prams using initial programmed resistances and prams using the same: A method of operating a PRAM device can be provided by reading a PRAM reference cell to determine an initial programmed resistance of the PRAM reference cell and determining whether the initial programmed resistance has been reduced to below a predetermined reference threshold resistance.... Agent: Samsung Electronics Co., Ltd.
20120087182 - Phase-change memory with multiple polarity bits having enhanced endurance and error tolerance: A Phase-Change Memory (PCM) apparatus including a data field for storing a data bits representing a data value or an inversion of the data value and a polarity field for storing a plurality of polarity bits for indicating that the data bits stored in the data field represent the data... Agent: Mosaid Technologies Incorporated
20120087185 - Magnetic latch magnetic random access memory (mram): A spin-transfer torque magnetic random access memory (STTMRAM) element is configured to store a state when electrical current is applied thereto. The STTMRAM element includes first and second free layers, each of which having an associated direction of magnetization defining the state of the STTMRAM element. Prior to the application... Agent: Avalanche Technology, Inc.
20120087184 - Magnetic random access memory (mram) layout with uniform pattern: A large scale memory array includes a uniform pattern of uniformly sized dummy bit cells and active bit cells. Sub-arrays within the large scale memory array are separated by the dummy bit cells. Signal distribution circuitry is formed with a width or height corresponding to the width or height of... Agent: Qualcomm Incorporated
20120087186 - Multi-bit memory with selectable magnetic layer: An apparatus and associated method for a multi-bit memory capable of being selected with a magnetic layer. Various embodiments of the present invention are generally directed to a first selection layer with a low coercivity that is disposed between first and second storage layers that each have a high coercivity.... Agent: Seagate Technology LLC
20120087189 - Non-volatile memory device: A non-volatile memory device includes a first sector including a first sector selection transistor and a first plurality of pages connected to the first sector selection transistor, and a second sector including a second sector selection transistor and a second plurality of pages connected to the second sector selection transistor.... Agent: Samsung Electronics Co., Ltd.
20120087188 - Structure and inhibited operation of flash memory with split gate: A method of performing a reading operation to a memory device including a plurality of flash memory cells. The method includes applying a first voltage bias to a control gate of a selected memory cell in the flash memory array and applying a second voltage bias to a word line... Agent: Taiwan Semiconductor Manufacturing Company, Ltd
20120087190 - Write bias condition for 2t-string nor flash cell: This invention discloses circuit and methods of a NAND-based 2T-string NOR flash cell structure as a building block for a fast random-read NOR flash memory. The key concept of this new set of bias conditions in cell array improves over the critical concern of punch-through issue when cell is migrating... Agent: Aplus Flash Technology, Inc.
20120087191 - Symmetric, differential nonvolatile memory cell: Some embodiments relate to a differential memory cell. The memory cell includes a first transistor having a source, a drain, a gate, and a body. A first capacitor has a first plate and a second plate, wherein the first plate is coupled to the gate of the first transistor and... Agent: Infineon Technologies Ag
20120087192 - Non-volatile memory device with program current clamp and related method: A method of programming a nonvolatile memory cell which comprises a select transistor and a memory transistor includes applying a preset limit current to a first input of the memory cell, applying a limit voltage to a current limiting circuit electrically connected to a second input of the memory cell,... Agent:
20120087187 - Method for programming a floating gate: The invention provides methods for programming a floating gate. A floating gate tunneling device is used with an analog comparing device in a circuit having a floating reference node and an offset-mitigating feedback loop for iteratively programming a floating gate, or multiple floating gates.... Agent:
20120087193 - Flash multi-level threshold distribution scheme: A threshold voltage distribution scheme for multi-level Flash cells where an erase threshold voltage and at least one programmed threshold voltage lie in an erase voltage domain. Having at least one programmed threshold voltage in the erase voltage domain reduces the Vread voltage level to minimize read disturb effects, while... Agent: Mosaid Technologies Incorporated
20120087194 - Data write training method and semiconductor device performing the same: Embodiments may be directed to a method of operating a semiconductor device, the method including receiving a first write training command, receiving a first write data responsive to the first write training command through a first data line, and transmitting the first write data through a second data line. Transmitting... Agent:
20120087195 - Semiconductor storage device and method for producing semiconductor storage device: A semiconductor storage device comprises a timing control circuit that generates a signal for controlling at least one of a read operation and a write operation; an input-signal pad; a plurality of control-signal pads; and a switch circuit coupled to at least one of the plurality of control-signal pads. The... Agent: Fujitsu Semiconductor Limited
20120087196 - Gate oxide breakdown-withstanding power switch structure: The present invention proposes a gate oxide breakdown-withstanding power switch structure, which is connected with an SRAM and comprises a first CMOS switch and a second CMOS switch respectively having different gate-oxide thicknesses or different threshold voltages. The CMOS switch, which has a normal gate-oxide thickness or a normal threshold... Agent:
20120087197 - Semiconductor memory apparatus and method for controlling the same: A semiconductor memory apparatus includes: a skew monitoring unit configured to receive a reference voltage and monitor a voltage characteristic of a corresponding MOS transistor; a voltage sensing unit configured to provide a sensing voltage corresponding to the monitoring result of the voltage characteristic; a coding unit configured to multiplex... Agent: Hynix Semiconductor Inc.
20120087198 - Semiconductor memory device with adjustable selected work line potential under low voltage condition: A level shift element adjusting a voltage level at the time of selection of a word line according to fluctuations in threshold voltage of a memory cell transistor is arranged for each word line. This level shift element lowers a driver power supply voltage, and transmits the level-shifted voltage onto... Agent: Renesas Electronics Corporation
20120087199 - Wake-up control circuit for power-gated ic: Embodiments of the present invention may provide a power-gating switch circuit. The power-gating switch circuit may comprise a first switch to connect a power supply to a virtual power supply and a second switch to connect the power supply to the virtual power supply in parallel to the first switch.... Agent: Analog Devices, Inc.
20120087200 - Internal column address generating circuit and semiconductor memory device: A semiconductor memory device includes first and second bank groups and an internal column address generating circuit. Each of the first and second bank groups includes at least one bank. The internal column address generating circuit converts a column address into a first internal column address and outputs the first... Agent: Hynix Semiconductor Inc.
20120087201 - Semiconductor memory device and memory system having the same: A semiconductor memory device includes an internal clock signal generator configured to generate an internal clock signal by dividing a frequency of an external clock signal; a default latency determiner configured to determine a default latency in outputting a signal; and a latency reflector configured to, for each of consecutive... Agent:04/05/2012 > 49 patent applications in 33 patent subcategories. category listing, related patent applications
20120081940 - Semiconductor memory device having an electrically floating body transistor: A semiconductor memory cell is formed in a semiconductor. The semiconductor memory cell includes: a floating body region defining at least a portion of a surface of the semiconductor memory cell, the floating body region having a first conductivity type; and a buried region located within the semiconductor memory cell... Agent: Zeno Semiconductor Inc.
20120081941 - Semiconductor memory device having an electrically floating body transistor: A semiconductor memory cell is formed in a semiconductor. The semiconductor memory cell includes: a floating body region defining at least a portion of a surface of the semiconductor memory cell, the floating body region having a first conductivity type; and a buried region located within the semiconductor memory cell... Agent:
20120081942 - Test cells for an unprogrammed otp memory array: Test cells are included in a one-time programmable (OTP) memory array for detecting semiconductor fabrication misalignment, which can result in a potentially defective memory array. The test cells are fabricated at the same time as the normal OTP cells, except they are smaller in size along one dimension in order... Agent: Sidense Corp.
20120081943 - Polarization-coupled ferroelectric unipolar junction memory and energy storage device: A memory device is provided. The memory device includes a plurality of memory cells and a controller to write data to and read data from the memory cells. Each memory cell includes a first semiconductor material having a spontaneous polarization, a resistive ferroelectric material having a switchable spontaneous polarization, and... Agent:
20120081944 - Crossbar array memory elements and related read methods: Apparatus and related fabrication and read methods are provided for crossbar memory elements. An exemplary crossbar memory element includes a crossbar array structure including a set of access lines, unswitched resistance elements coupled electrically in series between the set of access lines and a reference voltage node, and switched resistance... Agent: Globalfoundries Inc.
20120081945 - Memory array with graded resistance lines: A memory array with graded resistance lines includes a first set of lines intersecting a second set of lines. A line from one of the sets of lines includes a graded resistance along a length of the line.... Agent:
20120081947 - Metal-insulator-metal-insulator-metal (mimim) memory device: The present memory device includes first and second electrodes, first and second insulating layers between the electrodes, the first insulating layer being in contact with the first electrode, the second insulating layer being in contact with the second electrode, and a metal layer between the first and second insulating layers.... Agent:
20120081946 - Nonvolatile semiconductor memory device: A nonvolatile semiconductor memory device includes a memory cell array for storing user data provided by arranging memory cells each having a variable resistive element having a first electrode, a second electrode, and a variable resistor made of a metal oxide sandwiched between the first and second electrodes. The first... Agent:
20120081948 - Semiconductor memory device and driving method thereof: In a conventional DRAM, errors in reading data are likely to occur when the capacitance of a capacitor is reduced. A plurality of cells is connected to one main bit line Each cell includes a sub bit line and 2 to 32 memory cells. Further, each cell includes a selection... Agent: Semiconductor Energy Laboratory Co., Ltd.
20120081949 - Active bit line droop for read assist: A static random access memory (SRAM) includes an SRAM cell to store a bit of data. A word line accesses the SRAM cell, which, responsively, during a read, drives either a bit line true (BLT) or a bit line complement (BLC) low. Both BLT and BLC are precharged to a... Agent: International Business Machines Corporation
20120081951 - Non-volatile memory with stray magnetic field compensation: A method and apparatus for stray magnetic field compensation in a non-volatile memory cell, such as a spin-torque transfer random access memory (STRAM). In some embodiments, a first tunneling barrier is coupled to a reference structure that has a perpendicular anisotropy and a first magnetization direction. A recording structure that... Agent: Seagate Technology LLC
20120081952 - Semiconductor storage device: To write information on a memory cell of SPRAM formed of an MOS transistor and a tunnel magnetoresistive element, the memory cell is supplied with a current in a direction opposite to a direction of a current required for writing the information on the memory cell, and then, the memory... Agent:
20120081950 - Structures and methods for a field-reset spin-torque mram: An apparatus and method of programming a spin-torque magnetoresistive memory array includes a conductive reset line positioned near each of a plurality of magnetoresistive bits and configured to set the plurality of magnetoresistive memory elements to a known state having magnetization perpendicular to the film plane of the magnetoresistive bits... Agent: Everspin Technologies, Inc.
20120081954 - Phase change memory apparatus having row control cell: A semiconductor integrated circuit includes a phase change memory apparatus includes a plurality of row control cells and a plurality of phase change memory cells formed on the row control cells while being electrically connected to the row control cells. The plurality of row control cells and the plurality of... Agent: Hynix Semiconductor Inc.
20120081955 - Phase change random access memory device: A phase change random access memory device includes: a sense amplifier driving unit configured to compare an input voltage applied through an input signal line with a reference voltage and amplify an output signal in response to the comparison result; an input unit configured to receive an input signal from... Agent: Hynix Semiconductor Inc.
20120081953 - Semiconductor memory apparatus: A semiconductor memory apparatus includes: a first write control code generation unit configured to generate first write control codes which are updated with different cycles in a plurality of respective periods, in response to a programming verification flag signal and a programming enable signal, the first write control code generation... Agent: Hynix Semiconductor Inc.
20120081956 - Semiconductor phast change memory using multiple phase change layers: In accordance with some embodiments, a phase change memory may be formed in which the thermal conductivity in the region outside the programmed volume of phase change material is reduced. This may reduce the power consumption of the resulting phase change memory. The reduction in power consumption may be achieved... Agent:
20120081958 - Nonvolatile memory devices and methods forming the same: Provided are nonvolatile memory devices and methods of forming the same. The nonvolatile memory device includes a plurality of word lines, a ground select line, string select line, and a dummy word line. Each of distances between the dummy word line and the ground select line and between the dummy... Agent:
20120081959 - Memory system and programming method thereof: Provided are a non-volatile memory system and a programming method thereof. The programming method of the non-volatile memory system includes adjusting a program-verify-voltage of a selected memory cell referring to program data to be written in an interfering cell configured to provide interference for the selected memory cell and programming... Agent:
20120081960 - Semiconductor memory device: A semiconductor memory device includes a plurality of memory cell data holding transistors provided in each block; a row decoder including transfer transistors, a voltage controller and a block selector in each block, the transfer transistors electrically connected to respective of the memory cell transistors, the voltage controller connected to... Agent: Kabushiki Kaisha Toshiba
20120081961 - Nonvolatile memory apparatus capable of reducing current consumption and related driving method: Various exemplary embodiments of a nonvolatile memory apparatus are disclosed. In one exemplary embodiment, the memory apparatus may include: a page buffer; an even bit line connected to the page buffer; an odd bit line connected to the page buffer; an even memory cell string installed on the even bit... Agent: Hynix Semiconductor Inc.
20120081962 - Low voltage programming in nand flash: A memory device includes a plurality of memory cells arranged in series in the semiconductor body, such as a NAND string, having a plurality of word lines. A selected memory cell is programmed by hot carrier injection. The program operation is based on metering a flow of carriers between a... Agent: Macronix International Co., Ltd.
20120081965 - Method of evaluating a semiconductor storage device: A method of evaluating a semiconductor storage device of a floating gate type has calculating an electron density distribution of a tunnel insulating film of a memory cell by multiplying a change rate of a threshold voltage Vt of the memory cell of the semiconductor storage device with respect to... Agent: Kabushiki Kaisha Toshiba
20120081963 - Multi-step channel boosting to reduce channel to floating gate coupling in memory: In a programming operation, selected storage elements which reach a lockout condition are subject to reduced channel boosting in a program portion of the next program-verify iteration, to reduce coupling effects on the storage elements which continue to be programmed. In subsequent program-verify iterations, the locked out storage elements are... Agent:
20120081964 - Sensing for nand memory based on word line position: In a NAND non-volatile memory system, a sensing process accounts for a relative position of a selected non-volatile storage element in a NAND string. In one approach, the storage elements are assigned to groups based on their position, and each group receives a common sensing adjustment during a verify or... Agent:
20120081966 - Combined eeprom/flash non-volatile memory circuit: A non-volatile memory circuit includes memory rows and supporting circuits coupled to the memory rows, where at least one of the memory rows include at least one Electrically Erasable Programmable Read-Only Memory (EEPROM) memory element and at least one Flash memory element. The EEPROM and Flash elements are configured to... Agent: Nxp B.v.
20120081967 - Method and system for programming non-volatile memory cells based on programming of proximate memory cells: A multi-level non-volatile memory device programs cells in each row in a manner that takes into account the coupling from the programming of cells that are proximate the row to be programmed. In one example of the invention, after the row has been programmed, the proximate cells are verified by... Agent: Micron Technology, Inc.
20120081968 - N well implants to separate blocks in a flash memory device: A semiconductor memory device that has an isolated area formed from one conductivity and formed in part by a buried layer of a second conductivity that is implanted in a substrate. The walls of the isolated area are formed by implants that are formed from the second conductivity and extend... Agent: Micron Technology, Inc.
20120081969 - Programming method for non-volatile memory device: A method of programming a nonvolatile memory device comprises applying positive pulses and negative pulses simultaneously to a memory cell array to program at least one memory cell included in the memory cell array.... Agent: Samsung Electronics Co., Ltd.
20120081970 - Semiconductor memory apparatus and program verification method: A non-volatile memory apparatus includes a memory cell array, a power supply configured to generate an operation voltage according to an operation mode and provide the memory cell array with the operation voltage, and a controller configured to provide the memory cell array with a first verification voltage and a... Agent: Hynix Semiconductor Inc.
20120081957 - Flash memory device and wordline voltage generating method thereof: A word line voltage generating method of a flash memory which includes generating a program voltage using a positive voltage generator; generating a plurality of negative program verification voltages corresponding to a plurality of negative data states using a negative voltage generator; and generating at least one or more program... Agent: Samsung Electronics Co., Ltd.
20120081971 - E/p durability by using a sub-range of a full programming range: A NAND Flash memory controller is used to perform an erase operation on a NAND Flash memory chip including to a cell on the NAND Flash memory chip; the cell is configured to store a first number of bits. It is determined whether the erase operation performed on the NAND... Agent: Link_a_media Devices Corporation
20120081972 - Memory arrays and methods of operating memory: Apparatus and methods for determining pass/fail condition of memories are disclosed. In at least one embodiment, a set of common lines, one for each rank of page buffers corresponding to a page, determine the pass/fail status of all connected memory cells, and the pass/fail status results for each line can... Agent: Micron Technology, Inc.
20120081976 - Semiconductor memory device having an electrically floating body transistor: A method for performing a holding operation to a semiconductor memory array having rows and columns of memory cells, includes: applying an electrical signal to buried regions of the memory cells, wherein each of the memory cells comprises a floating body region defining at least a portion of a surface... Agent: Zeno Semiconductor Inc.
20120081977 - Semiconductor memory device having an electrically floating body transistor: A method for performing a holding operation to a semiconductor memory array having rows and columns of memory cells, includes: applying an electrical signal to buried regions of the memory cells, wherein each of the memory cells comprises a floating body region defining at least a portion of a surface... Agent:
20120081974 - Input-output line sense amplifier having adjustable output drive capability: An input-output line sense amplifier configured to drive input data signals over an input-output signal line to an output driver circuit, the input-output line sense amplifier having an output driver stage having a plurality of different programmable output drive capacities to tailor the output drive of the sense amplifier.... Agent: Micron Technology, Inc.
20120081973 - Method and apparatus for timing adjustment: A strobe signal from a memory is delayed through delay circuits of a strobe delay selection section, thus obtaining a plurality of delayed strobe signals. A strobe latch section produces check data in synchronism with each of the delayed strobe signals, and a system latch section latches, with a system... Agent: Panasonic Corporation
20120081975 - Semiconductor integrated circuit device: When a leakage type determining circuit determines that leakage current components of a gate leakage and a substrate leakage are larger in a resume standby mode, a VDDR regulator generates a power supply voltage VDDR at a first voltage level lower than a power supply voltage VDD, and supplies the... Agent: Renesas Electronics Corporation
20120081978 - Read boost circuit for memory device: A read boost circuit arranged to boost the voltage difference between a pair of complementary bit lines of a memory device during a read operation, the read boost circuit including: a first transistor adapted to be controlled by the voltage level on a first bit line of the pair of... Agent: Stmicroelectronics Crolles 2 Sas
20120081979 - Semiconductor memory apparatus: A semiconductor memory apparatus includes a first write control code generation unit configured to generate a first write control code which is updated with different cycles which have different periods, in response to a programming verification flag signal and a programming enable signal, and a data write unit configured to... Agent: Hynix Semiconductor Inc.
20120081980 - Memory: A memory including a memory cell array, a word line decoder, a first and a second reference bit line generators are provided. The memory cell array has first and last bit lines respectively disposed at two sides of the memory cell array. The word line decoder generates a pre-word line... Agent: Himax Technologies Limited
20120081981 - Nonvolatile memory apparatus with changeable operation speed and related signal control method: Various embodiments of a nonvolatile memory apparatus configured to operate in a first operation mode and a second operation mode are disclosed. In one exemplary embodiment, the apparatus may include: a controller configured to enable complementary signal input/output buffers in response to a command for entry into the first operation... Agent: Hynix Semiconductor Inc.
20120081982 - Verifying a data path in a semiconductor apparatus: A semiconductor apparatus includes a memory array configured to store write data transmitted through data transmission lines and transmit stored data to the data transmission line as read data; a data write unit configured to drive the write data to the data transmission lines in response to a data write... Agent: Hynix Semiconductor Inc.
20120081983 - Method of programming, erasing and repairing a memory device: A method of programming and erasing a memory device is provided. The memory device includes first and second electrodes and a switching layer therebetween. A first on-state resistance characteristic of the memory device is provided in programming the memory device by application of a first voltage to the gate of... Agent:
20120081984 - Three-dimensional stacked semiconductor integrated circuit: Various embodiments of a three-dimensional, stacked semiconductor integrated circuit are disclosed. In one exemplary embodiment, the circuit may include a master slice, a plurality of slave slices, and a plurality of through-silicon vias for connecting the master slice to the plurality of slave slices. At least one of the plurality... Agent: Hynix Semiconductor Inc.
20120081985 - Semiconductor apparatus: A semiconductor apparatus includes: odd and even sub word line driving units configured to selectively drive odd sub word lines and even sub word lines among a plurality of sub word lines; a bit line sense amplifier including a plurality of sense amplifier driving lines which are electrically connected with... Agent: Hynix Semiconductor Inc.
20120081986 - Semiconductor devices, operating methods thereof, and memory systems including the same: At least one example embodiment discloses a semiconductor device. The semiconductor device includes a first sense amplifier selectively connected between a first bit line and a second bit line, a second sense amplifier selectively connected between the first bit line and the second bit line, a first power supply circuit... Agent: Samsung Electronics Co., Ltd.
20120081987 - Supply voltage distribution system with reduced resistance for semiconductor devices: a voltage-to-voltage conversion circuit connected to the first supply voltage distribution line arrangement, wherein the voltage-to-voltage conversion circuit is adapted to either transfer onto the first supply voltage distribution line arrangement the semiconductor device supply voltage received from outside the semiconductor device, or to put on the first supply voltage... Agent:
20120081988 - Semiconductor circuit and semiconductor system: A semiconductor circuit includes a data driving circuit configured to change a slew rate in response to a control signal and drive data at a changed slew rate, a core/peripheral circuit block configured to provide the data to the data driving circuit, and a channel/memory module information setting unit configured... Agent: Hynix Semiconductor Inc.Previous industry: Electric power conversion systems
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